def test_pymtl3_interface_wire():
class Ifc(dsl.Interface):
def construct(s):
s.foo = dsl.Wire(Bits32)
s.bar = dsl.InPort(Bits32)
class A(dsl.Component):
def construct(s):
s.in_ = Ifc()
a = A()
a.elaborate()
# in_.foo will be silently dropped!
rt.get_rtlir(a.in_)
def test_pymtl3_list_interface_views():
a = CaseBits32MsgRdyIfcOnly.DUT()
a.elaborate()
assert rt.is_rtlir_convertible(a.in_)
assert rt.get_rtlir( a.in_ ) == \
rt.Array([5], rt.InterfaceView('Bits32MsgRdyIfc',
{'msg':rt.Port('output', rdt.Vector(32)), 'rdy':rt.Port('input', rdt.Vector(1))}))
def visit_Base(s, node):
# Mark this node as having type rt.Component
# In L1 the `s` top component is the only possible base
node.Type = rt.get_rtlir(node.base)
if not isinstance(node.Type, rt.Component):
raise PyMTLTypeError(s.blk, node.ast,
f'{node} is not a rt.Component!')
def test_pymtl3_list_consts():
class A(dsl.Component):
def construct(s):
s.in_ = [Bits32(42) for _ in range(5)]
a = A()
a.elaborate()
assert rt.is_rtlir_convertible(a.in_)
assert rt.Array([5], rt.Const(rdt.Vector(32))) == rt.get_rtlir(a.in_)
def test_pymtl_list_components():
a = CaseBits32InOutx5CompOnly.DUT()
a.elaborate()
assert rt.is_rtlir_convertible(a.b)
assert rt.get_rtlir( a.b ) == \
rt.Array([5], rt.Component( a.b[0], {
'clk':rt.Port('input', rdt.Vector(1)),
'reset':rt.Port('input', rdt.Vector(1)),
'in_':rt.Port('input', rdt.Vector(32)),
'out':rt.Port('output', rdt.Vector(32)),
}))
def test_pymtl_list_multi_dimension():
class A(dsl.Component):
def construct(s):
s.out = [[[dsl.OutPort(Bits32) for _ in range(1)] \
for _ in range(2)] for _ in range(3)]
a = A()
a.elaborate()
assert rt.is_rtlir_convertible(a.out)
assert rt.Array([3, 2, 1], rt.Port('output',
rdt.Vector(32))) == rt.get_rtlir(a.out)
def visit_FreeVar( s, node ):
if node.name not in s.freevars:
s.freevars[ node.name ] = node.obj
try:
t = rt.get_rtlir( node.obj )
except RTLIRConversionError as e:
raise PyMTLTypeError(s.blk, node.ast,
f'{node.name} cannot be converted into a valid RTLIR object!' )
if isinstance( t, rt.Const ) and isinstance( t.get_dtype(), rdt.Vector ):
node._value = mk_bits( t.get_dtype().get_length() )( node.obj )
node.Type = t
def test_pymtl_list_components():
class B(dsl.Component):
def construct(s):
s.in_ = dsl.InPort(Bits32)
s.out = dsl.OutPort(Bits32)
class A(dsl.Component):
def construct(s):
s.b = [B() for _ in range(5)]
a = A()
a.elaborate()
assert rt.is_rtlir_convertible(a.b)
assert rt.Array([5], rt.Component( a.b[0],
{'in_':rt.Port('input', rdt.Vector(32)), 'out':rt.Port('output', rdt.Vector(32))})) == \
rt.get_rtlir( a.b )
def test_pymtl3_list_interface_views():
class Ifc(dsl.Interface):
def construct(s):
s.msg = dsl.OutPort(Bits32)
s.rdy = dsl.InPort(Bits1)
class A(dsl.Component):
def construct(s):
s.in_ = [Ifc() for _ in range(5)]
a = A()
a.elaborate()
assert rt.is_rtlir_convertible(a.in_)
assert rt.Array([5],
rt.InterfaceView('Ifc',
{'msg':rt.Port('output', rdt.Vector(32)), 'rdy':rt.Port('input', rdt.Vector(1))})) == \
rt.get_rtlir( a.in_ )
def test_py_empty_list():
# This is no longer an error: empty lists will be dropped instead of
# triggering an error.
# with expected_failure( RTLIRConversionError, 'list [] is empty' ):
assert rt.get_rtlir([]) == None
def test_py_string():
with expected_failure(RTLIRConversionError):
rt.get_rtlir('abc')
def test_py_float():
with expected_failure(RTLIRConversionError):
rt.get_rtlir(3.14)
def test_pymtl_list_multi_dimension():
a = CaseBits32Outx3x2x1PortOnly.DUT()
a.elaborate()
assert rt.is_rtlir_convertible(a.out)
assert rt.get_rtlir(a.out) == rt.Array([3, 2, 1],
rt.Port('output', rdt.Vector(32)))
def test_pymtl3_list_ports():
a = CaseBits32x5PortOnly.DUT()
a.elaborate()
assert rt.is_rtlir_convertible(a.in_)
assert rt.get_rtlir(a.in_) == rt.Array([5],
rt.Port('input', rdt.Vector(32)))
def visit_Number(s, node):
# By default, number literals have bitwidth of 32
node.Type = rt.get_rtlir(node.value)
node._value = Bits32(node.value)
def test_py_untyped_list():
with expected_failure(RTLIRConversionError, 'must have the same type'):
rt.get_rtlir([4, Bits16(42)])
def test_pymtl3_interface_wire():
a = CaseBits32WireIfcOnly.DUT()
a.elaborate()
# in_.foo will be silently dropped!
assert rt.get_rtlir(a.in_) == rt.InterfaceView(
'Bits32FooWireBarInIfc', {'bar': rt.Port('input', rdt.Vector(32))})
def test_pymtl3_list_consts():
a = CaseBits32x5ConstOnly.DUT()
a.elaborate()
assert rt.is_rtlir_convertible(a.in_)
assert rt.get_rtlir(a.in_) == rt.Array([5], rt.Const(rdt.Vector(32)))