def get_imported_object(s, m):
config = s.get_config(m)
rtype = get_component_ifc_rtlir(m)
full_name = get_component_unique_name(rtype)
p_map = config.get_port_map() if config.is_port_mapped(
) else lambda x: x
no_clk, no_reset = not config.has_clk(), not config.has_reset()
_packed_ports = s.gen_packed_ports(rtype)
clk = next(filter(lambda x: x[0] == 'clk', _packed_ports))[1]
reset = next(filter(lambda x: x[0] == 'reset', _packed_ports))[1]
packed_ports = \
([('clk', '' if no_clk else p_map('clk'), clk)] if no_clk else []) + \
([('reset', '' if no_reset else p_map('reset'), reset)] if no_reset else []) + \
[ (n, p_map(n), p) for n, p in _packed_ports \
if not (n == 'clk' and no_clk or n == 'reset' and no_reset)]
cached = s.is_cached(m, full_name)
# Create a new Verilog source file if a new top-level wrapper is needed
if config.is_top_wrapper():
s.add_param_wrapper(m, config, rtype, packed_ports)
s.create_verilator_model(m, config, cached)
port_cdefs = \
s.create_verilator_c_wrapper( m, config, packed_ports, cached )
s.create_shared_lib(m, config, cached)
symbols = \
s.create_py_wrapper( m, config, rtype, packed_ports, port_cdefs, cached )
imp = s.import_component(m, config, symbols)
return imp
def fill_missing(s, m):
rtype = get_component_ifc_rtlir(m)
s.v_param = rtype.get_params()
s.is_param_wrapper = isinstance(m, Placeholder) and s.v_param
top_module = s.get_top_module()
# Check if the keys of `port_map` are port names of `m`
# Note that the keys can be expressions such as `ifc[0].foo` and
# therefore we do not check if a port name of `m` is in the keys.
if s.get_option("port_map"):
s.check_p_map(rtype)
# Fill in the top module if unspecified
# If the top-level module is not a wrapper
if not s.is_param_wrapper:
full_name = get_component_unique_name(rtype)
if not top_module:
# Default top_module is the name of component concatenated
# with parameters
s.set_option("top_module", full_name)
# If the top-level module is a wrapper
else:
# Check if all parameters are integers
assert all(isinstance(v[1], int) for v in s.v_param), \
"Only support integers as parameters of Verilog modules!"
# wrapped_module is the name of the module to be parametrized
# top_module is the name of the new top-level module
if top_module:
s.wrapped_module = top_module
s.set_option("top_module", f"{top_module}_w_params")
else:
# Default top_module is the name of component
s.wrapped_module = rtype.get_name()
s.set_option("top_module", f"{s.wrapped_module}_w_params")
top_module = s.get_top_module()
# Only try to infer the name of Verilog source file if both
# flist and the source file are not specified.
if not s.get_option("vl_src") and not s.get_option("vl_flist"):
s.set_option("vl_src", f"{top_module}.sv")
if not s.get_option("vl_mk_dir"):
s.set_option("vl_mk_dir", f"obj_dir_{top_module}")
if s.is_param_wrapper:
# If toplevel module is a param-wrapper, `vl_src` has to be specified
# because the file containing the wrapper will include `vl_src` for
# the module to be parametrized.
if not s.get_option("vl_src"):
raise InvalidPassOptionValue(
"vl_src", s.get_option("vl_src"), s.PassName,
"vl_src must be specified when Placeholder is to be imported!"
)
s.v_module2param = s.get_option("vl_src")
s.set_option("vl_src", top_module + ".sv")
def rtlir_tr_component_unique_name( s, c_rtype ): return get_component_unique_name( c_rtype )