Example #1
0
    def construct(s, EntryType):

        # Interface

        s.enq = EnqIfcRTL(EntryType)
        s.deq = DeqIfcRTL(EntryType)
        s.count = OutPort(Bits1)

        # Components

        s.entry = Wire(EntryType)
        s.full = Wire(Bits1)

        s.bypass_mux = Mux(EntryType, 2)(
            in_={
                0: s.enq.msg,
                1: s.entry
            },
            out=s.deq.ret,
            sel=s.full,
        )

        # Logic

        s.count //= s.full

        s.enq.rdy //= lambda: ~s.reset & ~s.full
        s.deq.rdy //= lambda: ~s.reset & (s.full | s.enq.en)

        @s.update_ff
        def ff_bypass1():
            s.full <<= ~s.reset & (~s.deq.en & (s.enq.en | s.full))

            if s.enq.en & ~s.deq.en:
                s.entry <<= s.enq.msg
Example #2
0
    def construct(s, EntryType):

        # Interface

        s.enq = EnqIfcRTL(EntryType)
        s.deq = DeqIfcRTL(EntryType)
        s.count = OutPort(Bits1)

        # Components

        s.entry = Wire(EntryType)
        s.full = Wire(Bits1)

        # Logic

        s.count //= s.full

        s.deq.ret //= s.entry

        s.enq.rdy //= lambda: ~s.reset & (~s.full | s.deq.en)
        s.deq.rdy //= lambda: s.full & ~s.reset

        @s.update_ff
        def ff_pipe1():
            s.full <<= ~s.reset & (s.enq.en | s.full & ~s.deq.en)

            if s.enq.en:
                s.entry <<= s.enq.msg
Example #3
0
    def construct(s, EntryType):

        # Interface

        s.enq = EnqIfcRTL(EntryType)
        s.deq = DeqIfcRTL(EntryType)
        s.count = OutPort(Bits1)

        # Components

        s.entry = Wire(EntryType)
        s.full = Wire(Bits1)

        connect(s.count, s.full)

        # Logic

        @s.update_on_edge
        def up_full():
            if s.reset:
                s.full = b1(0)
            else:
                s.full = ~s.deq.en & (s.enq.en | s.full)

        @s.update_on_edge
        def up_entry():
            if s.enq.en:
                s.entry = s.enq.msg

        @s.update
        def up_enq_rdy():
            if s.reset:
                s.enq.rdy = b1(0)
            else:
                s.enq.rdy = ~s.full

        @s.update
        def up_deq_rdy():
            s.deq.rdy = s.full & ~s.reset

        connect(s.entry, s.deq.msg)
Example #4
0
    def construct(s, EntryType, num_entries=2):

        # Interface

        s.enq = EnqIfcRTL(EntryType)
        s.deq = DeqIfcRTL(EntryType)
        s.count = OutPort(mk_bits(clog2(num_entries + 1)))

        # Components

        assert num_entries > 0
        if num_entries == 1:
            s.q = BypassQueue1EntryRTL(EntryType)
            connect(s.enq, s.q.enq)
            connect(s.deq, s.q.deq)
            connect(s.count, s.q.count)

        else:
            s.ctrl = BypassQueueCtrlRTL(num_entries)
            s.dpath = BypassQueueDpathRTL(EntryType, num_entries)

            # Connect ctrl to data path

            connect(s.ctrl.wen, s.dpath.wen)
            connect(s.ctrl.waddr, s.dpath.waddr)
            connect(s.ctrl.raddr, s.dpath.raddr)
            connect(s.ctrl.mux_sel, s.dpath.mux_sel)

            # Connect to interface

            connect(s.enq.en, s.ctrl.enq_en)
            connect(s.enq.rdy, s.ctrl.enq_rdy)
            connect(s.deq.en, s.ctrl.deq_en)
            connect(s.deq.rdy, s.ctrl.deq_rdy)
            connect(s.count, s.ctrl.count)
            connect(s.enq.msg, s.dpath.enq_msg)
            connect(s.deq.ret, s.dpath.deq_ret)