def test_alu_xor(dump_vcd, test_verilog): dut = AluRTL() config_model(dut, dump_vcd, test_verilog) run_test_vector_sim(dut, [ ('in0 in1 fn out* ops_eq* ops_lt* ops_ltu*' ), [0x00000000, 0x00000000, 7, 0x00000000, '?', '?', '?'], [0x0ffaa660, 0x00012304, 7, 0x0ffb8564, '?', '?', '?'], [0x00132050, 0xd6620040, 7, 0xd6712010, '?', '?', '?'], [0xfff0a440, 0x00004450, 7, 0xfff0e010, '?', '?', '?'], [0xfeeeeaa3, 0xf4650000, 7, 0x0a8beaa3, '?', '?', '?'], ])
def test_alu_nor(dump_vcd, test_verilog): dut = AluRTL() config_model(dut, dump_vcd, test_verilog) run_test_vector_sim(dut, [ ('in0 in1 fn out* ops_eq* ops_lt* ops_ltu*' ), [0x00000000, 0x00000000, 8, 0xffffffff, '?', '?', '?'], [0x0ffaa660, 0x00012304, 8, 0xf004589b, '?', '?', '?'], [0x00132050, 0xd6620040, 8, 0x298cdfaf, '?', '?', '?'], [0xfff0a440, 0x00004450, 8, 0x000f1baf, '?', '?', '?'], [0xfeeeeaa3, 0xf4650000, 8, 0x0110155c, '?', '?', '?'], ])
def test_alu_fn_equality(dump_vcd, test_verilog): dut = AluRTL() config_model(dut, dump_vcd, test_verilog) run_test_vector_sim(dut, [ ('in0 in1 fn out* ops_eq* ops_lt* ops_ltu*' ), [0x00000000, 0x00000000, 14, 0x00000000, 1, '?', '?'], [0x0ffaa660, 0x00012304, 14, 0x00000000, 0, '?', '?'], [0x00132050, 0xd6620040, 14, 0x00000000, 0, '?', '?'], [0xfff0a440, 0x00004450, 14, 0x00000000, 0, '?', '?'], [0xfeeeeaa3, 0xf4650000, 14, 0x00000000, 0, '?', '?'], ])
def test_32b_x_4b_mult( dump_vcd, test_verilog ): th = TestHarness() config_model( th, dump_vcd, test_verilog, [f'steps[{i}]' for i in range(4)] ) run_test_vector_sim( th, [ ('a b result*'), [ 0, 0, 0 ], [ 2, 3, 6 ], [ 4, 5, 20 ], [ 3, 4, 12 ], [ 10, 13, 130 ], [ 8, 7, 56 ], ] )
def test_basic( dump_vcd, test_verilog ): dut = IntMulNstageStepRTL() config_model( dut, dump_vcd, test_verilog ) run_test_vector_sim( dut, [ ('in_en in_a in_b in_result in_en* out_a* out_b* out_result*'), [ 0, 0x00000000, 0x00000000, 0x00000000, 0, 0x00000000, 0x00000000, 0x00000000 ], [ 1, 0x00000000, 0x00000000, 0x00000000, 1, 0x00000000, 0x00000000, 0x00000000 ], [ 1, 0x10101010, 0x00000000, 0x00000000, 1, 0x20202020, 0x00000000, 0x00000000 ], [ 1, 0x10101010, 0x00000001, 0x00000000, 1, 0x20202020, 0x00000000, 0x10101010 ], [ 1, 0x10101010, 0x00000000, 0x00000001, 1, 0x20202020, 0x00000000, 0x00000001 ], [ 1, 0x10101010, 0x00000001, 0x00000001, 1, 0x20202020, 0x00000000, 0x10101011 ], ] )
def test_verilate(dump_vcd, test_verilog): # Conflat the model model = SortUnitFlatRTL(8) # Configure the model config_model(model, dump_vcd, test_verilog) # Apply necessary passes model.apply(VerilogPlaceholderPass()) model = TranslationImportPass()(model) # Create and reset simulator model.apply(SimulationPass()) model.sim_reset() print("") # Helper function def t(in_val, in_, out_val, out): model.in_val = b1(in_val) for i, v in enumerate(in_): model.in_[i] = b8(v) model.eval_combinational() print(model.line_trace()) assert model.out_val == out_val if (out_val): for i, v in enumerate(out): assert model.out[i] == v model.tick() # Cycle-by-cycle tests t(0, [0x00, 0x00, 0x00, 0x00], 0, [0x00, 0x00, 0x00, 0x00]) t(1, [0x03, 0x09, 0x04, 0x01], 0, [0x00, 0x00, 0x00, 0x00]) t(1, [0x10, 0x23, 0x02, 0x41], 0, [0x00, 0x00, 0x00, 0x00]) t(1, [0x02, 0x55, 0x13, 0x07], 0, [0x00, 0x00, 0x00, 0x00]) t(0, [0x00, 0x00, 0x00, 0x00], 1, [0x01, 0x03, 0x04, 0x09]) t(0, [0x00, 0x00, 0x00, 0x00], 1, [0x02, 0x10, 0x23, 0x41]) t(0, [0x00, 0x00, 0x00, 0x00], 1, [0x02, 0x07, 0x13, 0x55]) t(0, [0x00, 0x00, 0x00, 0x00], 0, [0x00, 0x00, 0x00, 0x00]) t(0, [0x00, 0x00, 0x00, 0x00], 0, [0x00, 0x00, 0x00, 0x00])
def test_basic(dump_vcd, test_verilog): #dut = IntMulVarLatCalcShamtRTL() #need to change the name dut = IyVRTL(3) config_model(dut, dump_vcd, test_verilog) run_test_vector_sim( dut, [ #('req_msg_a req_msg_b presum resp_msg* a_shift*'), ('image_in[0] image_in[1] image_in[2] image_in[3] image_in[4] image_in[5] image_in[6] image_in[7] image_in[8] image_in[9] image_in[10] image_in[11] image_in[12] image_in[13] image_in[14] image_in[15] image_in[16] image_in[17] image_in[18] image_in[19] image_in[20] image_in[21] image_in[22] image_in[23] image_in[24] image_out[0]* image_out[1]* image_out[2]* image_out[3]* image_out[4]* image_out[5]* image_out[6]* image_out[7]* image_out[8]*' ), [ b32(0), b32(1), b32(2), b32(3), b32(4), b32(5), b32(6), b32(7), b32(8), b32(9), b32(10), b32(11), b32(12), b32(13), b32(14), b32(15), b32(16), b32(17), b32(18), b32(19), b32(20), b32(21), b32(22), b32(23), b32(24), b32(10), b32(10), b32(10), b32(10), b32(10), b32(10), b32(10), b32(10), b32(10) ], #[b32(0), b32(1), b32(7), b32(3), b32(0), b32(5), b32(6), b32(7), b32(8), b32(8), b32(4), b32(2), b32(9), b32(6), b32(3), b32(6), b32(6), b32(1), b32(5), b32(4), b32(-3), b32(3), b32(-1), b32(-5)], ])
def test_multiple_ones(dump_vcd, test_verilog): dut = IntMulVarLatCalcShamtRTL() config_model(dut, dump_vcd, test_verilog) run_test_vector_sim(dut, [ ('in_ out*'), [0x00000011, 1], [0x00000012, 1], [0x00000014, 2], [0x00000018, 3], [0x00000010, 4], [0x00000010, 4], ])
def test_alu_sll(dump_vcd, test_verilog): dut = AluRTL() config_model(dut, dump_vcd, test_verilog) run_test_vector_sim(dut, [ ('in0 in1 fn out* ops_eq* ops_lt* ops_ltu*' ), [0x00000000, 0x00000000, 2, 0x00000000, '?', '?', '?'], [0x05050505, 0x00000001, 2, 0x0a0a0a0a, '?', '?', '?'], [0x05050505, 0x00000002, 2, 0x14141414, '?', '?', '?'], [0x05050505, 0x00000004, 2, 0x50505050, '?', '?', '?'], [0x50505050, 0x00000008, 2, 0x50505000, '?', '?', '?'], [0x50505050, 0x0000000f, 2, 0x28280000, '?', '?', '?'], [0x50505050, 0x00000010, 2, 0x50500000, '?', '?', '?'], [0x50505050, 0x0000001f, 2, 0x00000000, '?', '?', '?'], ])
def test_gcd_rtl( test_params, dump_vcd, test_verilog ): th = TestHarness( GcdUnitRTL() ) th.set_param("top.tm.src.construct", msgs=test_params.msgs[::2], initial_delay=test_params.src_delay, interval_delay=test_params.src_delay ) th.set_param("top.tm.sink.construct", msgs=test_params.msgs[1::2], initial_delay=test_params.sink_delay, interval_delay=test_params.sink_delay ) config_model( th, dump_vcd, test_verilog, ['gcd'] ) run_sim( th )
def test_alu_srl(dump_vcd, test_verilog): dut = AluRTL() config_model(dut, dump_vcd, test_verilog) run_test_vector_sim(dut, [ ('in0 in1 fn out* ops_eq* ops_lt* ops_ltu*' ), [0x00000000, 0x00000000, 9, 0x00000000, '?', '?', '?'], [0x05050505, 0x00000001, 9, 0x02828282, '?', '?', '?'], [0x05050505, 0x00000002, 9, 0x01414141, '?', '?', '?'], [0x05050505, 0x00000004, 9, 0x00505050, '?', '?', '?'], [0x50505050, 0x00000008, 9, 0x00505050, '?', '?', '?'], [0x50505050, 0x0000000f, 9, 0x0000a0a0, '?', '?', '?'], [0x50505050, 0x00000010, 9, 0x00005050, '?', '?', '?'], [0x50505050, 0x0000001f, 9, 0x00000000, '?', '?', '?'], ])
def test(pytestconfig, test_params, dump_vcd, test_verilog): th = TestHarness() th.set_param("top.tm.src.construct", msgs=test_params.msgs[::2], initial_delay=test_params.src_delay + 3, interval_delay=test_params.src_delay) th.set_param("top.tm.sink.construct", msgs=test_params.msgs[1::2], initial_delay=test_params.sink_delay + 3, interval_delay=test_params.sink_delay) config_model(th, dump_vcd, test_verilog, ['xcel']) run_sim(th, pytestconfig=pytestconfig)
def test( test_params, dump_vcd, test_verilog ): th = TestHarness( IntMulFixedLatRTL() ) th.set_param("top.tm.src.construct", msgs=test_params.msgs[::2], initial_delay=test_params.src_delay+3, interval_delay=test_params.src_delay ) th.set_param("top.tm.sink.construct", msgs=test_params.msgs[1::2], initial_delay=test_params.sink_delay+3, interval_delay=test_params.sink_delay ) config_model( th, dump_vcd, test_verilog, ['imul'] ) run_sim( th )
def test_single_one(dump_vcd, test_verilog): dut = IntMulVarLatCalcShamtRTL() config_model(dut, dump_vcd, test_verilog) run_test_vector_sim(dut, [ ('in_ out*'), [0x00000000, 8], [0x00000001, 1], [0x00000002, 1], [0x00000004, 2], [0x00000008, 3], [0x00000010, 4], [0x00000020, 5], [0x00000040, 6], [0x00000080, 7], ])
def test_alu_sub(dump_vcd, test_verilog): dut = AluRTL() config_model(dut, dump_vcd, test_verilog) run_test_vector_sim( dut, [ ('in0 in1 fn out* ops_eq* ops_lt* ops_ltu*' ), [0x00000000, 0x00000000, 1, 0x00000000, '?', '?', '?'], [0x0ffaa660, 0x00012304, 1, 0x0ff9835c, '?', '?', '?'], # pos-neg [0x00132050, 0xd6620040, 1, 0x29b12010, '?', '?', '?'], [0xfff0a440, 0x00004450, 1, 0xfff05ff0, '?', '?', '?'], # neg-neg [0xfeeeeaa3, 0xf4650000, 1, 0x0a89eaa3, '?', '?', '?'], ])
def test_gcd_cl( test_params ): th = TestHarness( GcdUnitCL() ) th.set_param("top.tm.src.construct", msgs=test_params.msgs[::2], initial_delay=test_params.src_delay, interval_delay=test_params.src_delay ) th.set_param("top.tm.sink.construct", msgs=test_params.msgs[1::2], initial_delay=test_params.sink_delay, interval_delay=test_params.sink_delay ) config_model( th, False, False, ["gcd"] ) run_sim( th )
def test_alu_add(dump_vcd, test_verilog): dut = AluRTL() config_model(dut, dump_vcd, test_verilog) run_test_vector_sim( dut, [ ('in0 in1 fn out* ops_eq* ops_lt* ops_ltu*' ), [0x00000000, 0x00000000, 0, 0x00000000, '?', '?', '?'], [0x0ffaa660, 0x00012304, 0, 0x0ffbc964, '?', '?', '?'], #pos-neg [0x00132050, 0xd6620040, 0, 0xd6752090, '?', '?', '?'], [0xfff0a440, 0x00004450, 0, 0xfff0e890, '?', '?', '?'], # neg-neg [0xfeeeeaa3, 0xf4650000, 0, 0xf353eaa3, '?', '?', '?'], ])
def test_alu_sra(dump_vcd, test_verilog): dut = AluRTL() config_model(dut, dump_vcd, test_verilog) run_test_vector_sim(dut, [ ('in0 in1 fn out* ops_eq* ops_lt* ops_ltu*' ), [0x00000000, 0x00000000, 10, 0x00000000, '?', '?', '?'], [0x05050505, 0x00000001, 10, 0x02828282, '?', '?', '?'], [0x05050505, 0x00000002, 10, 0x01414141, '?', '?', '?'], [0x05050505, 0xffffff01, 10, 0x02828282, '?', '?', '?'], [0x05050505, 0xffffff02, 10, 0x01414141, '?', '?', '?'], [0x05050505, 0x00000004, 10, 0x00505050, '?', '?', '?'], [0x80808080, 0x00000008, 10, 0xff808080, '?', '?', '?'], [0x80808080, 0x0000000f, 10, 0xffff0101, '?', '?', '?'], [0x80808080, 0x00000010, 10, 0xffff8080, '?', '?', '?'], [0x80808080, 0x0000001f, 10, 0xffffffff, '?', '?', '?'], [0xffffffff, 0x0000001f, 10, 0xffffffff, '?', '?', '?'], ])
def test_direct_128x256_mask4(dump_vcd, test_verilog): dut = SramRTL(128, 256, mask_size=4) config_model(dut, dump_vcd, test_verilog) header_str = \ ( "port0_val", "port0_type", "port0_wben", "port0_idx", "port0_wdata", "port0_rdata*" ) run_test_vector_sim( dut, [ header_str, # val type wben idx wdata rdata [1, 1, 0b0001, 0x00, 0x00000000, '?'], # one at a time [1, 0, 0b0001, 0x00, 0x00000000, '?'], [0, 0, 0b0001, 0x00, 0x00000000, 0x00000000], [1, 1, 0b0001, 0x00, 0xdeadbeef, '?'], [1, 0, 0b0001, 0x00, 0x00000000, '?'], [0, 0, 0b0001, 0x00, 0x00000000, 0xdeadbeef], [1, 1, 0b0001, 0x01, 0xcafecafe, '?'], [1, 0, 0b0001, 0x01, 0x00000000, '?'], [0, 0, 0b0001, 0x00, 0x00000000, 0xcafecafe], [1, 1, 0b0001, 0x2f, 0x0a0a0a0a, '?'], [1, 0, 0b0001, 0x2f, 0x00000000, '?'], [0, 0, 0b0001, 0x00, 0x00000000, 0x0a0a0a0a], [1, 1, 0b0001, 0x2e, 0x0b0b0b0b, '?'], # streaming reads [1, 0, 0b0001, 0x2e, 0x00000000, '?'], [1, 0, 0b0001, 0x2f, 0x00000000, 0x0b0b0b0b], [1, 0, 0b0001, 0x01, 0x00000000, 0x0a0a0a0a], [1, 0, 0b0001, 0x00, 0x00000000, 0xcafecafe], [0, 0, 0b0001, 0x00, 0x00000000, 0xdeadbeef], [1, 1, 0b0001, 0x2d, 0x0c0c0c0c, '?'], # streaming writes/reads [1, 0, 0b0001, 0x2d, 0x00000000, '?'], [1, 1, 0b0001, 0x2c, 0x0d0d0d0d, 0x0c0c0c0c], [1, 0, 0b0001, 0x2c, 0x00000000, '?'], [1, 1, 0b0001, 0x2b, 0x0e0e0e0e, 0x0d0d0d0d], [1, 0, 0b0001, 0x2b, 0x00000000, '?'], [0, 0, 0b0001, 0x00, 0x00000000, 0x0e0e0e0e], ])
def test_direct_16x32(dump_vcd, test_verilog): dut = SramRTL(16, 32) config_model(dut, dump_vcd, test_verilog) run_test_vector_sim( dut, [ header_str, # val type idx wdata rdata [1, 1, 0x0, 0x0000, '?'], # one at a time [1, 0, 0x0, 0x0000, '?'], [0, 0, 0x0, 0x0000, 0x0000], [1, 1, 0x0, 0xbeef, '?'], [1, 0, 0x0, 0x0000, '?'], [0, 0, 0x0, 0x0000, 0xbeef], [1, 1, 0x1, 0xcafe, '?'], [1, 0, 0x1, 0x0000, '?'], [0, 0, 0x0, 0x0000, 0xcafe], [1, 1, 0xf, 0x0a0a, '?'], [1, 0, 0xf, 0x0000, '?'], [0, 0, 0x0, 0x0000, 0x0a0a], [1, 1, 0xe, 0x0b0b, '?'], # streaming reads [1, 0, 0xe, 0x0000, '?'], [1, 0, 0xf, 0x0000, 0x0b0b], [1, 0, 0x1, 0x0000, 0x0a0a], [1, 0, 0x0, 0x0000, 0xcafe], [0, 0, 0x0, 0x0000, 0xbeef], [1, 1, 0xd, 0x0c0c, '?'], # streaming writes/reads [1, 0, 0xd, 0x0000, '?'], [1, 1, 0xc, 0x0d0d, 0x0c0c], [1, 0, 0xc, 0x0000, '?'], [1, 1, 0xb, 0x0e0e, 0x0d0d], [1, 0, 0xb, 0x0000, '?'], [0, 0, 0x0, 0x0000, 0x0e0e], ])
def test_direct_32x256(dump_vcd, test_verilog): dut = SramRTL(32, 256) config_model(dut, dump_vcd, test_verilog) run_test_vector_sim( dut, [ header_str, # val type idx wdata rdata [1, 1, 0x00, 0x00000000, '?'], # one at a time [1, 0, 0x00, 0x00000000, '?'], [0, 0, 0x00, 0x00000000, 0x00000000], [1, 1, 0x00, 0xdeadbeef, '?'], [1, 0, 0x00, 0x00000000, '?'], [0, 0, 0x00, 0x00000000, 0xdeadbeef], [1, 1, 0x01, 0xcafecafe, '?'], [1, 0, 0x01, 0x00000000, '?'], [0, 0, 0x00, 0x00000000, 0xcafecafe], [1, 1, 0x1f, 0x0a0a0a0a, '?'], [1, 0, 0x1f, 0x00000000, '?'], [0, 0, 0x00, 0x00000000, 0x0a0a0a0a], [1, 1, 0x1e, 0x0b0b0b0b, '?'], # streaming reads [1, 0, 0x1e, 0x00000000, '?'], [1, 0, 0x1f, 0x00000000, 0x0b0b0b0b], [1, 0, 0x01, 0x00000000, 0x0a0a0a0a], [1, 0, 0x00, 0x00000000, 0xcafecafe], [0, 0, 0x00, 0x00000000, 0xdeadbeef], [1, 1, 0x1d, 0x0c0c0c0c, '?'], # streaming writes/reads [1, 0, 0x1d, 0x00000000, '?'], [1, 1, 0x1c, 0x0d0d0d0d, 0x0c0c0c0c], [1, 0, 0x1c, 0x00000000, '?'], [1, 1, 0x1b, 0x0e0e0e0e, 0x0d0d0d0d], [1, 0, 0x1b, 0x00000000, '?'], [0, 0, 0x00, 0x00000000, 0x0e0e0e0e], ])
def run_test_static(pytestconfig, xcel, test_params, dump_vcd=False, test_verilog=False): # Convert test data into byte array of_data = test_params.static_data image1 = of_data[::8] image2 = of_data[1::8] image3 = of_data[2::8] image4 = of_data[3::8] image5 = of_data[4::8] image6 = of_data[5::8] cornerx = of_data[6::8] cornery = of_data[7::8] #data_src0 = current_frame #data_src1 = next_frame image1_bytes = [0] * len(image1) image2_bytes = [0] * len(image2) image3_bytes = [0] * len(image3) image4_bytes = [0] * len(image4) image5_bytes = [0] * len(image5) image6_bytes = [0] * len(image6) cornerx_bytes = [0] * len(cornerx) cornery_bytes = [0] * len(cornery) for i in range(len(image1)): image1_bytes[i] = struct.pack("<{}I".format(len(image1[i])), *image1[i]) image2_bytes[i] = struct.pack("<{}I".format(len(image2[i])), *image2[i]) image3_bytes[i] = struct.pack("<{}I".format(len(image3[i])), *image3[i]) image4_bytes[i] = struct.pack("<{}I".format(len(image4[i])), *image4[i]) image5_bytes[i] = struct.pack("<{}I".format(len(image5[i])), *image5[i]) image6_bytes[i] = struct.pack("<{}I".format(len(image6[i])), *image6[i]) for i in range(len(cornerx)): cornerx_bytes[i] = struct.pack("<{}I".format(len(cornerx[i])), *cornerx[i]) cornery_bytes[i] = struct.pack("<{}I".format(len(cornery[i])), *cornery[i]) # Protocol messages xcel_protocol_msgs = [] for i in range(1): # cooment xcel_protocol_msgs = xcel_protocol_msgs + gen_xcel_protocol_msgs() xreqs = xcel_protocol_msgs[::2] xresps = xcel_protocol_msgs[1::2] # Create test harness with protocol messagse th = TestHarness(xcel) th.set_param("top.tm.src.construct", msgs=xcel_protocol_msgs[::2], initial_delay=test_params.src + 3, interval_delay=test_params.src) th.set_param("top.tm.sink.construct", msgs=xcel_protocol_msgs[1::2], initial_delay=test_params.sink + 3, interval_delay=test_params.sink) th.set_param("top.mem.construct", stall_prob=test_params.stall, latency=test_params.lat + 1) # Load the data into the test memory th.elaborate() for i in range(len(image1)): th.mem.write_mem(0x5000 + 4 * i, image1_bytes[i]) th.mem.write_mem(0x5000 + 4 * (i + 100), image2_bytes[i]) th.mem.write_mem(0x5000 + 4 * (i + 200), image3_bytes[i]) th.mem.write_mem(0x5000 + 4 * (i + 300), image4_bytes[i]) th.mem.write_mem(0x5000 + 4 * (i + 400), image5_bytes[i]) th.mem.write_mem(0x5000 + 4 * (i + 500), image6_bytes[i]) for i in range(len(cornerx)): th.mem.write_mem(0x2000 + 4 * i, cornerx_bytes[i]) th.mem.write_mem(0x2500 + 4 * i, cornery_bytes[i]) #th.mem.write_mem( 0x5000 + 4 * i, image_set[1][i] ) # Run the test config_model(th, dump_vcd, test_verilog, ['xcel']) run_sim(th, max_cycles=20000) # Retrieve data from test memory result_vx_bytes = [0] * len(cornerx) result_vy_bytes = [0] * len(cornery) result_de_bytes = [0] * len(cornerx) for i in range(1): result_vx_bytes[i] = th.mem.read_mem(0x3000 + 4 * i, len(cornerx_bytes[i])) result_vy_bytes[i] = th.mem.read_mem(0x3500 + 4 * i, len(cornerx_bytes[i])) result_de_bytes[i] = th.mem.read_mem(0x4000 + 4 * i, len(cornerx_bytes[i])) for i in range(len(result_vx_bytes)): # Convert result bytes into list of ints result_vx = list( struct.unpack("<{}I".format(len(cornerx[i])), result_vx_bytes[i])) result_vy = list( struct.unpack("<{}I".format(len(cornery[i])), result_vy_bytes[i])) result_de = list( struct.unpack("<{}I".format(len(cornerx[i])), result_de_bytes[i]))
def test_basic(dump_vcd, test_verilog): #dut = IntMulVarLatCalcShamtRTL() #need to change the name dut = ItVRTL(3) config_model(dut, dump_vcd, test_verilog) run_test_vector_sim( dut, [ #('req_msg_a req_msg_b presum resp_msg* a_shift*'), ('current_frame[0] current_frame[1] current_frame[2] current_frame[3] current_frame[4] current_frame[5] current_frame[6] current_frame[7] current_frame[8] current_frame[9] current_frame[10] current_frame[11] current_frame[12] current_frame[13] current_frame[14] current_frame[15] current_frame[16] current_frame[17] current_frame[18] current_frame[19] current_frame[20] current_frame[21] current_frame[22] current_frame[23] current_frame[24] next_frame[0] next_frame[1] next_frame[2] next_frame[3] next_frame[4] next_frame[5] next_frame[6] next_frame[7] next_frame[8] next_frame[9] next_frame[10] next_frame[11] next_frame[12] next_frame[13] next_frame[14] next_frame[15] next_frame[16] next_frame[17] next_frame[18] next_frame[19] next_frame[20] next_frame[21] next_frame[22] next_frame[23] next_frame[24] out[0]* out[1]* out[2]* out[3]* out[4]* out[5]* out[6]* out[7]* out[8]*' ), [ b32(0), b32(1), b32(2), b32(3), b32(4), b32(5), b32(6), b32(7), b32(8), b32(9), b32(10), b32(11), b32(12), b32(13), b32(14), b32(15), b32(16), b32(17), b32(18), b32(19), b32(20), b32(21), b32(22), b32(23), b32(24), b32(24), b32(23), b32(22), b32(21), b32(20), b32(19), b32(18), b32(17), b32(16), b32(15), b32(14), b32(13), b32(12), b32(11), b32(10), b32(9), b32(8), b32(7), b32(6), b32(5), b32(4), b32(3), b32(2), b32(1), b32(0), b32(12), b32(10), b32(8), b32(2), b32(0), b32(-2), b32(-8), b32(-10), b32(-12), ], #[b32(0), b32(1), b32(7), b32(3), b32(0), b32(5), b32(6), b32(7), b32(8), b32(4), b32(-1), b32(5), b32(7), b32(0), b32(2), b32(1), b32(-1), b32(2), b32(4), b32(-2), b32(-2), b32(4), b32(0), b32(-3), b32(-5), b32(-8), b32(-6), ], ])
def test_small_neg(dump_vcd, test_verilog): dut = IxVRTL(3) config_model(dut, dump_vcd, test_verilog) run_test_vector_sim( dut, [ #('req_msg_a req_msg_b presum resp_msg* a_shift*'), ('image_in[0] image_in[1] image_in[2] image_in[3] image_in[4] image_in[5] image_in[6] image_in[7] image_in[8] image_in[9] image_in[10] image_in[11] image_in[12] image_in[13] image_in[14] image_out[0]* image_out[1]* image_out[2]* image_out[3]* image_out[4]* image_out[5]* image_out[6]* image_out[7]* image_out[8]*' ), [ b32(0), b32(-2), b32(-4), b32(-6), b32(-8), b32(-10), b32(-12), b32(-14), b32(-16), b32(-18), b32(-20), b32(-22), b32(-24), b32(-26), b32(-28), b32(-4), b32(-4), b32(-4), b32(-4), b32(-4), b32(-4), b32(-4), b32(-4), b32(-4) ], [ b32(-5), b32(-1), b32(-7), b32(-1), b32(-3), b32(-9), b32(-9), b32(-3), b32(-5), b32(-2), b32(0), b32(-1), b32(-2), b32(-4), b32(-3), b32(-2), b32(0), b32(4), b32(6), b32(4), b32(1), b32(-2), b32(-3), b32(-1) ], ])
def test_large_neg(dump_vcd, test_verilog): dut = IxVRTL(3) config_model(dut, dump_vcd, test_verilog) run_test_vector_sim( dut, [ #('req_msg_a req_msg_b presum resp_msg* a_shift*'), ('image_in[0] image_in[1] image_in[2] image_in[3] image_in[4] image_in[5] image_in[6] image_in[7] image_in[8] image_in[9] image_in[10] image_in[11] image_in[12] image_in[13] image_in[14] image_out[0]* image_out[1]* image_out[2]* image_out[3]* image_out[4]* image_out[5]* image_out[6]* image_out[7]* image_out[8]*' ), [ b32(-255), b32(-255), b32(-255), b32(-255), b32(-255), b32(-255), b32(-255), b32(-255), b32(-255), b32(-255), b32(-255), b32(-255), b32(-255), b32(-255), b32(-255), b32(0), b32(0), b32(0), b32(0), b32(0), b32(0), b32(0), b32(0), b32(0) ], [ b32(-250), b32(-248), b32(-251), b32(-255), b32(-252), b32(-243), b32(-247), b32(-251), b32(-250), b32(-255), b32(-250), b32(-243), b32(-247), b32(-249), b32(-240), b32(-1), b32(-7), b32(-1), b32(-8), b32(-3), b32(-4), b32(3), b32(-6), b32(7) ], ])
def test_zeros(dump_vcd, test_verilog): #dut = IntMulVarLatCalcShamtRTL() #need to change the name dut = IxVRTL(3) config_model(dut, dump_vcd, test_verilog) run_test_vector_sim( dut, [ #('req_msg_a req_msg_b presum resp_msg* a_shift*'), ('image_in[0] image_in[1] image_in[2] image_in[3] image_in[4] image_in[5] image_in[6] image_in[7] image_in[8] image_in[9] image_in[10] image_in[11] image_in[12] image_in[13] image_in[14] image_out[0]* image_out[1]* image_out[2]* image_out[3]* image_out[4]* image_out[5]* image_out[6]* image_out[7]* image_out[8]*' ), [ b32(0), b32(0), b32(0), b32(0), b32(0), b32(0), b32(0), b32(0), b32(0), b32(0), b32(0), b32(0), b32(0), b32(0), b32(0), b32(0), b32(0), b32(0), b32(0), b32(0), b32(0), b32(0), b32(0), b32(0) ], [ b32(0), b32(7), b32(2), b32(3), b32(0), b32(0), b32(1), b32(-6), b32(5), b32(0), b32(0), b32(-1), b32(-2), b32(0), b32(0), b32(2), b32(-4), b32(-2), b32(-6), b32(4), b32(6), b32(-2), b32(1), b32(2) ], ])
def test_basic_1x2(dump_vcd, test_verilog): # Instantiate and elaborate the model model = Router(mk_mem_msg(8, 32, 32)[1], 2) config_model(model, dump_vcd, test_verilog) model.elaborate() # We can call apply if we are 100% sure the top level is not tagged model.apply(TranslationImportPass()) # Create a simulator model.apply(SimulationPass()) # Reset test harness model.sim_reset(print_line_trace=True) # Helper function def t(in_, out): # Write the input value to the input ports model.in_.en = in_[0] model.in_.msg = in_[1] model.out[0].rdy = in_[2] model.out[1].rdy = in_[3] # Ensure that all combinational concurrent blocks are called model.eval_combinational() # Display line trace model.print_line_trace() # Verify reference output port assert model.in_.rdy == out[0] assert model.out[0].en == out[1] assert model.out[0].msg == out[2] assert model.out[1].en == out[3] assert model.out[1].msg == out[4] # Tick simulator by one cycle model.tick() # Helper function to make messages def msg(type_, opaque, test, len_, data): return mk_mem_msg(8, 32, 32)[1](type_, opaque, test, len_, data) # Cycle-by-cycle tests # in_ in_ out[0] out[1] in_ out[0] out[0] out[1] out[1] # .en .msg .rdy rdy .rdy .en .msg .en .msg t([1, msg(0, 0, 0, 0, 4), 1, 1], [1, 1, msg(0, 0, 0, 0, 4), 0, msg(0, 0, 0, 0, 0)]) t([1, msg(0, 1, 0, 0, 5), 1, 1], [1, 0, msg(0, 0, 0, 0, 0), 1, msg(0, 1, 0, 0, 5)]) t([0, msg(0, 1, 0, 0, 5), 1, 1], [1, 0, msg(0, 0, 0, 0, 0), 0, msg(0, 0, 0, 0, 0)]) t([1, msg(0, 1, 0, 0, 6), 1, 1], [1, 0, msg(0, 0, 0, 0, 0), 1, msg(0, 1, 0, 0, 6)]) t([1, msg(0, 0, 0, 0, 7), 0, 1], [1, 0, msg(0, 0, 0, 0, 0), 0, msg(0, 0, 0, 0, 0)]) t([0, msg(0, 1, 0, 0, 8), 0, 1], [0, 0, msg(0, 0, 0, 0, 0), 0, msg(0, 0, 0, 0, 0)]) t([0, msg(0, 1, 0, 0, 8), 1, 1], [0, 1, msg(0, 0, 0, 0, 7), 0, msg(0, 0, 0, 0, 0)]) t([1, msg(0, 1, 0, 0, 9), 0, 1], [1, 0, msg(0, 0, 0, 0, 0), 1, msg(0, 1, 0, 0, 9)]) model.tick() model.tick() model.tick()
def test_immgen(dump_vcd, test_verilog): dut = ImmGenRTL() config_model(dut, dump_vcd, test_verilog) run_test_vector_sim( dut, [ ('imm_type inst imm*'), [ 0, 0b11111111111100000000000000000000, 0b11111111111111111111111111111111 ], # I-imm [ 0, 0b00000000000011111111111111111111, 0b00000000000000000000000000000000 ], # I-imm [ 0, 0b01111111111100000000000000000000, 0b00000000000000000000011111111111 ], # I-imm [ 0, 0b11111111111000000000000000000000, 0b11111111111111111111111111111110 ], # I-imm [ 1, 0b11111110000000000000111110000000, 0b11111111111111111111111111111111 ], # S-imm [ 1, 0b00000001111111111111000001111111, 0b00000000000000000000000000000000 ], # S-imm [ 1, 0b01111110000000000000111110000000, 0b00000000000000000000011111111111 ], # S-imm [ 1, 0b11111110000000000000111100000000, 0b11111111111111111111111111111110 ], # S-imm [ 2, 0b11111110000000000000111110000000, 0b11111111111111111111111111111110 ], # B-imm [ 2, 0b00000001111111111111000001111111, 0b00000000000000000000000000000000 ], # B-imm [ 2, 0b11000000000000000000111100000000, 0b11111111111111111111010000011110 ], # B-imm [ 3, 0b11111111111111111111000000000000, 0b11111111111111111111000000000000 ], # U-imm [ 3, 0b00000000000000000000111111111111, 0b00000000000000000000000000000000 ], # U-imm [ 4, 0b11111111111111111111000000000000, 0b11111111111111111111111111111110 ], # J-imm [ 4, 0b00000000000000000001111111111111, 0b00000000000000000001000000000000 ], # J-imm [ 4, 0b01000000000010011001000000000000, 0b00000000000010011001010000000000 ], # J-imm ])
def test_large(dump_vcd, test_verilog): #dut = IntMulVarLatCalcShamtRTL() #need to change the name dut = matrix_operaVRTL() config_model(dut, dump_vcd, test_verilog) run_test_vector_sim( dut, [ #('req_msg_a req_msg_b presum resp_msg* a_shift*'), ('req_go in_x[0] in_x[1] in_x[2] in_x[3] in_x[4] in_x[5] in_x[6] in_x[7] in_x[8] in_y[0] in_y[1] in_y[2] in_y[3] in_y[4] in_y[5] in_y[6] in_y[7] in_y[8] in_t[0] in_t[1] in_t[2] in_t[3] in_t[4] in_t[5] in_t[6] in_t[7] in_t[8] vx* vy* de* result_ok*' ), [ b1(1), b32(6), b32(2), b32(3), b32(4), b32(9), b32(5), b32(5), b32(5), b32(3), b32(6), b32(3), b32(6), b32(6), b32(0), b32(2), b32(4), b32(4), b32(5), b32(3), b32(9), b32(6), b32(0), b32(0), b32(5), b32(5), b32(7), b32(5), b32(0), b32(0), b32(0), b32(0) ], [ b1(1), b32(6), b32(2), b32(3), b32(4), b32(9), b32(5), b32(5), b32(5), b32(3), b32(6), b32(3), b32(6), b32(6), b32(0), b32(2), b32(4), b32(4), b32(5), b32(3), b32(9), b32(6), b32(0), b32(0), b32(5), b32(5), b32(7), b32(5), b32(0), b32(0), b32(0), b32(0) ], [ b1(1), b32(6), b32(2), b32(3), b32(4), b32(9), b32(5), b32(5), b32(5), b32(3), b32(6), b32(3), b32(6), b32(6), b32(0), b32(2), b32(4), b32(4), b32(5), b32(3), b32(9), b32(6), b32(0), b32(0), b32(5), b32(5), b32(7), b32(5), b32(0), b32(0), b32(0), b32(0) ], [ b1(1), b32(6), b32(2), b32(3), b32(4), b32(9), b32(5), b32(5), b32(5), b32(3), b32(6), b32(3), b32(6), b32(6), b32(0), b32(2), b32(4), b32(4), b32(5), b32(3), b32(9), b32(6), b32(0), b32(0), b32(5), b32(5), b32(7), b32(5), b32(0), b32(0), b32(0), b32(0) ], [ b1(1), b32(6), b32(2), b32(3), b32(4), b32(9), b32(5), b32(5), b32(5), b32(3), b32(6), b32(3), b32(6), b32(6), b32(0), b32(2), b32(4), b32(4), b32(5), b32(3), b32(9), b32(6), b32(0), b32(0), b32(5), b32(5), b32(7), b32(5), b32(0), b32(0), b32(0), b32(0) ], [ b1(1), b32(6), b32(2), b32(3), b32(4), b32(9), b32(5), b32(5), b32(5), b32(3), b32(6), b32(3), b32(6), b32(6), b32(0), b32(2), b32(4), b32(4), b32(5), b32(3), b32(9), b32(6), b32(0), b32(0), b32(5), b32(5), b32(7), b32(5), b32(0), b32(0), b32(0), b32(0) ], [ b1(1), b32(6), b32(2), b32(3), b32(4), b32(9), b32(5), b32(5), b32(5), b32(3), b32(6), b32(3), b32(6), b32(6), b32(0), b32(2), b32(4), b32(4), b32(5), b32(3), b32(9), b32(6), b32(0), b32(0), b32(5), b32(5), b32(7), b32(5), b32(0), b32(0), b32(0), b32(0) ], [ b1(1), b32(6), b32(2), b32(3), b32(4), b32(9), b32(5), b32(5), b32(5), b32(3), b32(6), b32(3), b32(6), b32(6), b32(0), b32(2), b32(4), b32(4), b32(5), b32(3), b32(9), b32(6), b32(0), b32(0), b32(5), b32(5), b32(7), b32(5), b32(0), b32(0), b32(0), b32(0) ], [ b1(1), b32(6), b32(2), b32(3), b32(4), b32(9), b32(5), b32(5), b32(5), b32(3), b32(6), b32(3), b32(6), b32(6), b32(0), b32(2), b32(4), b32(4), b32(5), b32(3), b32(9), b32(6), b32(0), b32(0), b32(5), b32(5), b32(7), b32(5), b32(0), b32(0), b32(0), b32(0) ], [ b1(1), b32(6), b32(2), b32(3), b32(4), b32(9), b32(5), b32(5), b32(5), b32(3), b32(6), b32(3), b32(6), b32(6), b32(0), b32(2), b32(4), b32(4), b32(5), b32(3), b32(9), b32(6), b32(0), b32(0), b32(5), b32(5), b32(7), b32(5), b32(0), b32(0), b32(0), b32(0) ], [ b1(1), b32(6), b32(2), b32(3), b32(4), b32(9), b32(5), b32(5), b32(5), b32(3), b32(6), b32(3), b32(6), b32(6), b32(0), b32(2), b32(4), b32(4), b32(5), b32(3), b32(9), b32(6), b32(0), b32(0), b32(5), b32(5), b32(7), b32(5), b32(0), b32(0), b32(0), b32(0) ], [ b1(1), b32(6), b32(2), b32(3), b32(4), b32(9), b32(5), b32(5), b32(5), b32(3), b32(6), b32(3), b32(6), b32(6), b32(0), b32(2), b32(4), b32(4), b32(5), b32(3), b32(9), b32(6), b32(0), b32(0), b32(5), b32(5), b32(7), b32(5), b32(0), b32(0), b32(0), b32(0) ], [ b1(0), b32(2), b32(1), b32(1), b32(1), b32(1), b32(1), b32(1), b32(1), b32(1), b32(1), b32(1), b32(1), b32(1), b32(1), b32(1), b32(1), b32(1), b32(1), b32(1), b32(1), b32(1), b32(1), b32(1), b32(1), b32(1), b32(1), b32(1), b32(0), b32(-19), b32(19), b32(1) ], [ b1(0), b32(2), b32(1), b32(1), b32(1), b32(1), b32(1), b32(1), b32(1), b32(1), b32(1), b32(1), b32(1), b32(1), b32(1), b32(1), b32(1), b32(1), b32(1), b32(1), b32(1), b32(1), b32(1), b32(1), b32(1), b32(1), b32(1), b32(1), b32(0), b32(-19), b32(19), b32(0) ], ])