def run_experiment(self, time, cfg=None): if self.RUN: self.connect() if cfg is None: cfg = pysthal.HICANNConfigurator() self.w.configure(cfg) if time > 0.0: runner = pysthal.ExperimentRunner(time) self.w.start(runner)
def record_membrane(output_dir, hicann, aout, placement_item, wafer_cfg, params): """ :type hicann: HICANNOnWafer :type aout: AnalogOnHICANN """ import pysthal import Coordinate as C logical_neuron = placement_item.logical_neuron() hicann_cfg = wafer_cfg[hicann] hicann_cfg.enable_aout(logical_neuron.front(), aout) db = pysthal.MagicHardwareDatabase() wafer_cfg.connect(db) configurator = pysthal.HICANNv4Configurator() wafer_cfg.configure(configurator) adc = hicann_cfg.analogRecorder(aout) recording_time = params["duration"] / 1e3 / 1e4 adc.setRecordingTime(recording_time) adc.activateTrigger() runner = pysthal.ExperimentRunner(recording_time) wafer_cfg.start(runner) if adc.hasTriggered(): v = adc.trace() t = adc.getTimestamps() membrane = np.vstack((t, v)).T else: membrane = np.empty(0) address = placement_item.address() link = C.GbitLinkOnHICANN(address.toDNCMergerOnHICANN()) spikes = hicann_cfg.receivedSpikes(link) if len(spikes): spikes = spikes[spikes[:, 1] == address.toL1Address()] return (membrane, spikes)
h.set_speed_up_gl(pysthal.SpeedUp.NORMAL) h.set_speed_up_gladapt(pysthal.SpeedUp.SLOW) h.set_speed_up_radapt(pysthal.SpeedUp.SLOW) db = pysthal.MagicHardwareDatabase() import os w.connect(db) adc = h.analogRecorder(coord_analog) recording_time = duration_ms / 1e3 / 1e4 adc.setRecordingTime(recording_time) w.configure(pysthal.HICANNv4Configurator()) runner = pysthal.ExperimentRunner(recording_time) adc.activateTrigger() w.start(runner) v = adc.trace() t = adc.getTimestamps() regions = { "exc": exc_region, "inh": inh_region, "silent1": silent_region1, "silent2": silent_region2 }
self.config_neuron_quads(h, hicann) self.config_analog_readout(h, hicann) self.flush_hicann(h) #class FooConfigurator(pysthal.HICANNConfigurator): # def config(self, fpga, handle, data): # pyhalbe.HICANN.init(handle, False) # self.config_synapse_drivers(handle, data); wafer.configure(pysthal.HICANNConfigurator()) #wafer.configure(NoneConfigurator()) #wafer.configure(FooConfigurator()) # Run experiment: runner = pysthal.ExperimentRunner(duration) # Setup ADC recorder0 = hicann.analogRecorder(Coordinate.AnalogOnHICANN(0)) recorder0.activateTrigger(duration) wafer.start(runner) outdir_str = "in_addr_"+str(in_addr_int) + "_" + args.vertical try: os.mkdir(outdir_str) except: pass # Write voltage trace
def start_runner(self, time): runner = pysthal.ExperimentRunner(time) self.w.start(runner)