def set(self, context, inst_name, field_name, value):
"""
Stores an object in the db using the context and
inst_name to create a retrieval path, and the field
name.
:param context: A handle to a component
:param inst_name: The instance name within the component
:param field_name: The field we're setting
:param value: The object to be stored
:return: None
"""
if not set(field_name).issubset(self.legal_chars):
raise error_classes.UVMNotImplemented(
f"pyuvm does not allow wildcards in field names ({field_name})"
)
context, inst_name = self._get_context_inst_name(context, inst_name)
if inst_name not in self._path_dict:
self._path_dict[inst_name] = {}
if field_name not in self._path_dict[inst_name]:
self._path_dict[inst_name][field_name] = {}
precedence = self.default_precedence
if uvm_root().running_phase is uvm_build_phase:
precedence = self.default_precedence - context.get_depth()
self._path_dict[inst_name][field_name][precedence] = value
self.trace("SET", context, inst_name, field_name, value)
def print(self):
"""
Not implemented. Use __str__() and print()
"""
raise error_classes.UVMNotImplemented(
'There are better ways to do printing in Python using'
'print() or str()')
def find_wrapper_by_name(self):
"""
There are no wrappers in pyuvm so this is not implemented.
"""
raise error_classes.UVMNotImplemented(
"There are no wrappers in pyuvm. "
"So find_wrapper_by_name is not implemented")
def get_object_type(self):
"""
Not implemented because Python can implement the factory without
these shenanigans.
"""
raise error_classes.UVMNotImplemented(
'Python provides better ways to do this '
'so the uvm_object_wrapper is unimplemented')
def set_type_alias(self, alias_type_name, original_type):
"""
Not implemented as it does not seem to exist in SystemVerilog UVM
:param alias_type_name:A string that will reference the original type
:param original_type:The original type toe be referenced
:return:None
"""
# This method does not seem to be implemented in SystemVerilog
# so I'm skipping it now.
raise error_classes.UVMNotImplemented(
"set_type_alias is not implemented in SystemVerilog")
def wait_modified(self):
raise error_classes.UVMNotImplemented(
"wait_modified not implemented pending requests for it.")
def do_execute_op(self, op):
raise error_classes.UVMNotImplemented("Policies not implemented")
def __not_implemented(self):
raise error_classes.UVMNotImplemented(
'This method is not implemented at this time.')
def reseed(self):
""" Not implemented """
raise error_classes.UVMNotImplemented('reseed not implemented')
def set_uvm_seeding(self, enable):
""" Not implemented """
raise error_classes.UVMNotImplemented(
'set_uvm_seeding not implemented')
def get_active_policy(self):
"""
Not implemented yet.
"""
raise error_classes.UVMNotImplemented("policies not implemented yet")
def get_uvm_seeding(self):
"""Not implemented"""
raise error_classes.UVMNotImplemented(
'get_uvm_seeding not implemented')
def do_record(self):
"""
Not implemented as we are not in a simulator
"""
raise error_classes.UVMNotImplemented(
'Python does not run in the simulator, so no recording')
def do_print(self):
""" not implemented. Use __str__() and print()"""
raise error_classes.UVMNotImplemented(
'There are better ways to do printing in Python')
