def _modulehead(self, terms): modulehead = '' modulehead += '`default_nettype none\n' modulehead += 'module ' + self.modulename + '(' modulehead += '\n' + (' ' * self.num_indent) modulehead += self.clock_name + ', ' modulehead += self.reset_name + ', ' modulehead += self.enable_name + ', ' modulehead += '\n' + (' ' * self.num_indent) for tk, tv in terms.items(): scope = util.getScope(tk) if util.isTopmodule(scope): termtype = self.getTermtype(tk) if signaltype.isInput(termtype) and tk == util.toTermname( (self.topmodule, self.reset_name)): continue if signaltype.isInput(termtype) and tk == util.toTermname( (self.topmodule, self.clock_name)): continue if signaltype.isInput(termtype): modulehead += util.toFlatname(tk) + ', ' elif signaltype.isInout(termtype): modulehead += util.toFlatname(tk) + ', ' elif signaltype.isOutput(termtype): modulehead += util.toFlatname(tk) + ', ' modulehead = modulehead[:-2] + ');\n\n' return modulehead
def tocode(self): flatname = util.toFlatname(self.name) scope = self.getScope(self.name) code = '' if self.isTopmodule(scope): if signaltype.isInput(self.termtype): code += 'input ' elif signaltype.isInout(self.termtype): code += 'inout ' elif signaltype.isOutput(self.termtype): code += 'output ' else: if signaltype.isInput(self.termtype): code += 'wire ' elif signaltype.isInout(self.termtype): code += 'wire ' elif signaltype.isOutput(self.termtype) and not signaltype.isReg(self.termtype): code += 'wire ' if signaltype.isReg(self.termtype): code += 'reg ' if signaltype.isRegArray(self.termtype): code += 'reg ' if signaltype.isWire(self.termtype): code += 'wire ' if signaltype.isWireArray(self.termtype): code += 'wire ' if signaltype.isInteger(self.termtype): code += 'integer ' if signaltype.isFunction(self.termtype): code += 'wire ' if signaltype.isRename(self.termtype): code += 'wire ' if (not signaltype.isInteger(self.termtype) and self.msb is not None and self.lsb is not None): code += '[' + self.msb.tocode(None) + ':' + self.lsb.tocode(None) + '] ' code += flatname # signal name if self.lenmsb is not None and self.lenlsb is not None: code += ' [' + self.lenmsb.tocode() + ':' + self.lenlsb.tocode(flatname) + ']' code += ';\n' return code
def _toCode(self, terms, parameter, assign, always_clockedge, always_combination): # module header modulehead = self._modulehead(terms) code = '' # clock, reset, control input definition code += self._system_io(self.clock_name, self.reset_name, self.enable_name) # general signal definition for tk, tv in terms.items(): termtype = self.getTermtype(tk) if signaltype.isInput(termtype) and tk == util.toTermname( (self.topmodule, self.reset_name)): continue if signaltype.isInput(termtype) and tk == util.toTermname( (self.topmodule, self.clock_name)): continue code += tv.tocode() for pk, pv in parameter.items(): code += pv.tocode() # assign for ak, avv in assign.items(): cnt = 0 for av in avv: code += av.tocode() # always (clock edge) for ck, cvv in always_clockedge.items(): for cv in cvv: code += cv.tocode() # always (combination) for ck, cvv in always_combination.items(): for cv in cvv: code += cv.tocode() # module tail moduletail = '\nendmodule\n' ret = modulehead + code + moduletail if self.flat: ret = re.sub('\.', '_', ret) return ret
def getAssignType(self, termname, bind): termtype = self.getTermtype(termname) if signaltype.isWire(termtype): return 'assign' if signaltype.isWireArray(termtype): return 'assign' if signaltype.isReg(termtype): if bind.isClockEdge(): return 'clockedge' return 'combination' if signaltype.isRegArray(termtype): if bind.isClockEdge(): return 'clockedge' return 'combination' if signaltype.isInteger(termtype): if bind.isClockEdge(): return 'clockedge' return 'combination' if signaltype.isParameter(termtype): return 'parameter' if signaltype.isLocalparam(termtype): return 'localparam' if signaltype.isOutput(termtype): return 'assign' if signaltype.isInput(termtype): return 'assign' if signaltype.isFunction(termtype): return 'assign' if signaltype.isRename(termtype): return 'assign' if signaltype.isGenvar(termtype): return 'genvar' raise verror.DefinitionError('Unexpected Assignment Type: %s : %s' % (str(termname), str(termtype)))
def chgTermsAfterMuxGen(design, termdict, bindMuxinfodict_list, sigdiffStr_Refmax, sigdiffStr_Maxbit_Design, muxterm_dict, muxtermStr_ind_dict, options): # in TERMs, the format is [scope: signals] for ti, tv in termdict.items(): ti_str = str(ti) # some signals are not in the bindlist, such as inputs if ti_str in bindMuxinfodict_list[design]: bindMuxinfo = bindMuxinfodict_list[design][ti_str] # (6-a) Consider the head-is-multi case if ti_str in sigdiffStr_Refmax: # (6-aI) case 1: entire tree multi-bit if bindMuxinfo.termMultiNum == bindMuxinfo.termNum and not bindMuxinfo.hasCmp: # Such complicated check is required because the max signals bitwidth can be the same in two designs if sigdiffStr_Refmax[ti_str][ design] == 0 and sigdiffStr_Maxbit_Design[ ti_str] == design: muxingscope = ti.scopechain[-1] muxingscope.scopename = muxingscope.scopename + "_mux" # (6-aIII) compare with the signal in muxterms_dict, remove when needed deleteMuxTerm(ti, muxtermStr_ind_dict, muxterm_dict) else: # other designs, delete that signal del termdict[ti] # (6-aII) case 2: Not all elements in tree are multi-bit, # change the signal into <signal>_mux0/1/2 else: muxingscope = ti.scopechain[-1] muxingscope.scopename = muxingscope.scopename + "_mux" + str( design) deleteMuxTerm(ti, muxtermStr_ind_dict, muxterm_dict) # If 'mux' is put as postfix, then it will be an input to mux # which means it will not be used as IO if signaltype.isInput(tv.termtype): tv.termtype.remove('Input') elif signaltype.isInout(tv.termtype): tv.termtype.remove('Inout') elif signaltype.isOutput(tv.termtype): tv.termtype.remove('Output') # (6-b) For other signals, they are added with 0/1/2 as postfix else: nonmuxingscope = ti.scopechain[-1] nonmuxingscope.scopename = nonmuxingscope.scopename + str( design) elif ti.scopechain[-1].scopename == options.clockname: if not design == 0: del termdict[ti] elif ti.scopechain[-1].scopename == options.resetname: if not design == 0: del termdict[ti] else: nonmuxingscope = ti.scopechain[-1] nonmuxingscope.scopename = nonmuxingscope.scopename + str(design)
def _toCode(self, terms, parameter, assign, always_clockedge, always_combination): # module header modulehead = self._modulehead(terms) code = '' # clock, reset, control input definition code += self._system_io(self.clock_name, self.reset_name, self.enable_name) # general signal definition for tk, tv in terms.items(): termtype = self.getTermtype(tk) if signaltype.isInput(termtype) and tk == util.toTermname((self.topmodule, self.reset_name)): continue if signaltype.isInput(termtype) and tk == util.toTermname((self.topmodule, self.clock_name)): continue code += tv.tocode() for pk, pv in parameter.items(): code += pv.tocode() # assign for ak, avv in assign.items(): cnt = 0 for av in avv: code += av.tocode() # always (clock edge) for ck, cvv in always_clockedge.items(): for cv in cvv: code += cv.tocode() # always (combination) for ck, cvv in always_combination.items(): for cv in cvv: code += cv.tocode() # module tail moduletail = '\nendmodule\n' ret = modulehead + code + moduletail if self.flat: ret = re.sub('\.', '_', ret) return ret
def _modulehead(self, terms): modulehead = '' modulehead += '`default_nettype none\n' modulehead += 'module ' + self.modulename + '(' modulehead += '\n' + (' ' * self.num_indent) modulehead += self.clock_name + ', ' modulehead += self.reset_name + ', ' modulehead += self.enable_name + ', ' modulehead += '\n' + (' ' * self.num_indent) for tk, tv in terms.items(): scope = util.getScope(tk) if util.isTopmodule(scope): termtype = self.getTermtype(tk) if signaltype.isInput(termtype) and tk == util.toTermname((self.topmodule, self.reset_name)): continue if signaltype.isInput(termtype) and tk == util.toTermname((self.topmodule, self.clock_name)): continue if signaltype.isInput(termtype): modulehead += util.toFlatname(tk) + ', ' elif signaltype.isInout(termtype): modulehead += util.toFlatname(tk) + ', ' elif signaltype.isOutput(termtype): modulehead += util.toFlatname(tk) + ', ' modulehead = modulehead[:-2] + ');\n\n' return modulehead
def walkTree(self, tree, visited=set([]), step=0, delay=False, msb=None, lsb=None, ptr=None): if tree is None: return DFUndefined(32) if isinstance(tree, DFUndefined): return tree if isinstance(tree, DFHighImpedance): return tree if isinstance(tree, DFConstant): return tree if isinstance(tree, DFEvalValue): return tree if isinstance(tree, DFTerminal): scope = util.getScope(tree.name) termname = tree.name if termname in visited: return tree termtype = self.getTermtype(termname) if util.isTopmodule(scope) and signaltype.isInput(termtype): return tree nptr = None if signaltype.isRegArray(termtype) or signaltype.isWireArray( termtype): if ptr is None: raise verror.FormatError( 'Array variable requires an pointer.') if msb is not None and lsb is not None: return tree nptr = ptr nextstep = step if signaltype.isReg(termtype) or signaltype.isRegArray(termtype): if (not self.isCombination(termname) and not signaltype.isRename(termtype) and nextstep == 0): return tree if (not self.isCombination(termname) and not signaltype.isRename(termtype)): nextstep -= 1 return self.walkTree(self.getTree(termname, nptr), visited | set([ termname, ]), nextstep, delay) if isinstance(tree, DFBranch): condnode = self.walkTree(tree.condnode, visited, step, delay) truenode = self.walkTree(tree.truenode, visited, step, delay) falsenode = self.walkTree(tree.falsenode, visited, step, delay) return DFBranch(condnode, truenode, falsenode) if isinstance(tree, DFOperator): nextnodes = [] for n in tree.nextnodes: nextnodes.append(self.walkTree(n, visited, step, delay)) return DFOperator(tuple(nextnodes), tree.operator) if isinstance(tree, DFPartselect): msb = self.walkTree(tree.msb, visited, step, delay) lsb = self.walkTree(tree.lsb, visited, step, delay) var = self.walkTree(tree.var, visited, step, delay, msb=msb, lsb=lsb) return DFPartselect(var, msb, lsb) if isinstance(tree, DFPointer): ptr = self.walkTree(tree.ptr, visited, step, delay) var = self.walkTree(tree.var, visited, step, delay, ptr=ptr) if isinstance(tree.var, DFTerminal): termtype = self.getTermtype(tree.var.name) if ((signaltype.isRegArray(termtype) or signaltype.isWireArray(termtype)) and not (isinstance(var, DFTerminal) and var.name == tree.var.name)): return var return DFPointer(var, ptr) if isinstance(tree, DFConcat): nextnodes = [] for n in tree.nextnodes: nextnodes.append(self.walkTree(n, visited, step, delay)) return DFConcat(tuple(nextnodes)) raise verror.DefinitionError('Undefined Node Type: %s : %s' % (str(type(tree)), str(tree)))
def walkTree(self, tree, visited=set([]), step=0, delay=False, msb=None, lsb=None, ptr=None): if tree is None: return DFUndefined(32) if isinstance(tree, DFUndefined): return tree if isinstance(tree, DFHighImpedance): return tree if isinstance(tree, DFConstant): return tree if isinstance(tree, DFEvalValue): return tree if isinstance(tree, DFTerminal): scope = util.getScope(tree.name) termname = tree.name if termname in visited: return tree termtype = self.getTermtype(termname) if util.isTopmodule(scope) and signaltype.isInput(termtype): return tree nptr = None if signaltype.isRegArray(termtype) or signaltype.isWireArray(termtype): if ptr is None: raise verror.FormatError("Array variable requires an pointer.") if msb is not None and lsb is not None: return tree nptr = ptr nextstep = step if signaltype.isReg(termtype) or signaltype.isRegArray(termtype): if not self.isCombination(termname) and not signaltype.isRename(termtype) and nextstep == 0: return tree if not self.isCombination(termname) and not signaltype.isRename(termtype): nextstep -= 1 return self.walkTree(self.getTree(termname, nptr), visited | set([termname]), nextstep, delay) if isinstance(tree, DFBranch): condnode = self.walkTree(tree.condnode, visited, step, delay) truenode = self.walkTree(tree.truenode, visited, step, delay) falsenode = self.walkTree(tree.falsenode, visited, step, delay) return DFBranch(condnode, truenode, falsenode) if isinstance(tree, DFOperator): nextnodes = [] for n in tree.nextnodes: nextnodes.append(self.walkTree(n, visited, step, delay)) return DFOperator(tuple(nextnodes), tree.operator) if isinstance(tree, DFPartselect): msb = self.walkTree(tree.msb, visited, step, delay) lsb = self.walkTree(tree.lsb, visited, step, delay) var = self.walkTree(tree.var, visited, step, delay, msb=msb, lsb=lsb) if isinstance(var, DFPartselect): child_lsb = self.getTerm(str(tree.var)).lsb.eval() return DFPartselect( var.var, DFIntConst(str(msb.eval() + var.lsb.eval() - child_lsb)), DFIntConst(str(lsb.eval() + var.lsb.eval() - child_lsb)), ) return DFPartselect(var, msb, lsb) if isinstance(tree, DFPointer): ptr = self.walkTree(tree.ptr, visited, step, delay) var = self.walkTree(tree.var, visited, step, delay, ptr=ptr) if isinstance(tree.var, DFTerminal): termtype = self.getTermtype(tree.var.name) if (signaltype.isRegArray(termtype) or signaltype.isWireArray(termtype)) and not ( isinstance(var, DFTerminal) and var.name == tree.var.name ): return var return DFPointer(var, ptr) if isinstance(tree, DFConcat): nextnodes = [] for n in tree.nextnodes: nextnodes.append(self.walkTree(n, visited, step, delay)) return DFConcat(tuple(nextnodes)) raise verror.DefinitionError("Undefined Node Type: %s : %s" % (str(type(tree)), str(tree)))