Example #1
0
    def _modulehead(self, terms):
        modulehead = ''
        modulehead += '`default_nettype none\n'
        modulehead += 'module ' + self.modulename + '('
        modulehead += '\n' + (' ' * self.num_indent)
        modulehead += self.clock_name + ', '
        modulehead += self.reset_name + ', '
        modulehead += self.enable_name + ', '
        modulehead += '\n' + (' ' * self.num_indent)

        for tk, tv in terms.items():
            scope = util.getScope(tk)
            if util.isTopmodule(scope):
                termtype = self.getTermtype(tk)
                if signaltype.isInput(termtype) and tk == util.toTermname(
                    (self.topmodule, self.reset_name)):
                    continue
                if signaltype.isInput(termtype) and tk == util.toTermname(
                    (self.topmodule, self.clock_name)):
                    continue
                if signaltype.isInput(termtype):
                    modulehead += util.toFlatname(tk) + ', '
                elif signaltype.isInout(termtype):
                    modulehead += util.toFlatname(tk) + ', '
                elif signaltype.isOutput(termtype):
                    modulehead += util.toFlatname(tk) + ', '
        modulehead = modulehead[:-2] + ');\n\n'
        return modulehead
Example #2
0
 def _system_io(self, clock_name, reset_name, enable_name):
     flat_clock_name = util.toFlatname( util.toTermname((self.topmodule, clock_name)) )
     flat_reset_name = util.toFlatname( util.toTermname((self.topmodule, reset_name)) )
     flat_enable_name = util.toFlatname( util.toTermname((self.topmodule, enable_name)) )
     code = ''
     code += self._input(clock_name)
     code += self._input(reset_name)
     code += self._input(enable_name)
     code += self._wire(flat_clock_name)
     code += self._wire(flat_reset_name)
     code += self._assign(flat_clock_name, clock_name)
     code += self._assign(flat_reset_name, reset_name)
     code += '\n'
     return code
Example #3
0
 def _system_io(self, clock_name, reset_name, enable_name):
     flat_clock_name = util.toFlatname( util.toTermname((self.topmodule, clock_name)) )
     flat_reset_name = util.toFlatname( util.toTermname((self.topmodule, reset_name)) )
     flat_enable_name = util.toFlatname( util.toTermname((self.topmodule, enable_name)) )
     code = ''
     code += self._input(clock_name)
     code += self._input(reset_name)
     code += self._input(enable_name)
     code += self._wire(flat_clock_name)
     code += self._wire(flat_reset_name)
     code += self._assign(flat_clock_name, clock_name)
     code += self._assign(flat_reset_name, reset_name)
     code += '\n'
     return code
Example #4
0
    def _toCode(self, terms, parameter, assign, always_clockedge,
                always_combination):
        # module header
        modulehead = self._modulehead(terms)

        code = ''
        # clock, reset, control input definition
        code += self._system_io(self.clock_name, self.reset_name,
                                self.enable_name)

        # general signal definition
        for tk, tv in terms.items():
            termtype = self.getTermtype(tk)
            if signaltype.isInput(termtype) and tk == util.toTermname(
                (self.topmodule, self.reset_name)):
                continue
            if signaltype.isInput(termtype) and tk == util.toTermname(
                (self.topmodule, self.clock_name)):
                continue
            code += tv.tocode()

        for pk, pv in parameter.items():
            code += pv.tocode()

        # assign
        for ak, avv in assign.items():
            cnt = 0
            for av in avv:
                code += av.tocode()

        # always (clock edge)
        for ck, cvv in always_clockedge.items():
            for cv in cvv:
                code += cv.tocode()

        # always (combination)
        for ck, cvv in always_combination.items():
            for cv in cvv:
                code += cv.tocode()

        # module tail
        moduletail = '\nendmodule\n'

        ret = modulehead + code + moduletail

        if self.flat:
            ret = re.sub('\.', '_', ret)

        return ret
Example #5
0
    def getBindSubset(self, termname, visited_sources=set()):
        term = self.getTerm(termname)
        if term is None: raise verror.DefinitionError('No such signal')
        bindlist = self.getBindlist(termname)
        nextsources = visited_sources.copy()
        ret_binds = collections.OrderedDict()
        for bind in bindlist:
            if not termname in ret_binds:
                ret_binds[termname] = []
            ret_binds[termname].append(bind)
            if bind.isClockEdge():
                clock_name = bind.getClockName()
                if clock_name != util.toTermname((self.topmodule, self.clock_name)):
                    r_binds, r_sources = self.getBindSubset(clock_name, nextsources)
                    nextsources |= r_sources
                    ret_binds = util.dictlistmerge(ret_binds, r_binds)

        sources = self.getBindSources(termname)
        for source in sources:
            if source in visited_sources: continue
            nextsources.add(source)
            r_binds, r_sources = self.getBindSubset(source, nextsources)
            ret_binds = util.dictlistmerge(ret_binds, r_binds)
            nextsources |= r_sources
        return ret_binds, nextsources
Example #6
0
 def walkBind(self, name, step=0):
     termname = util.toTermname(name)
     if not termname in self.terms:
         raise verror.DefinitionError('No such signals: %s' % str(name))
     tree = self.getTree(termname)
     walked_tree = self.walkTree(tree, visited=set(), step=step)
     return replace.replaceUndefined(walked_tree, termname)
Example #7
0
    def getBindSubset(self, termname, visited_sources=set()):
        term = self.getTerm(termname)
        if term is None: raise verror.DefinitionError('No such signal')
        bindlist = self.getBindlist(termname)
        nextsources = visited_sources.copy()
        ret_binds = collections.OrderedDict()
        for bind in bindlist:
            if not termname in ret_binds:
                ret_binds[termname] = []
            ret_binds[termname].append(bind)
            if bind.isClockEdge():
                clock_name = bind.getClockName()
                if clock_name != util.toTermname(
                    (self.topmodule, self.clock_name)):
                    r_binds, r_sources = self.getBindSubset(
                        clock_name, nextsources)
                    nextsources |= r_sources
                    ret_binds = util.dictlistmerge(ret_binds, r_binds)

        sources = self.getBindSources(termname)
        for source in sources:
            if source in visited_sources: continue
            nextsources.add(source)
            r_binds, r_sources = self.getBindSubset(source, nextsources)
            ret_binds = util.dictlistmerge(ret_binds, r_binds)
            nextsources |= r_sources
        return ret_binds, nextsources
Example #8
0
    def generate(self,
                 signalname,
                 identical=False,
                 walk=True,
                 step=1,
                 reorder=False,
                 delay=False):
        termname = util.toTermname(signalname)
        tree = self.treewalker.getTree(termname)
        if tree is None:
            raise verror.DefinitionError('No such signals: %s' %
                                         str(signalname))
        if walk:
            tree = self.treewalker.walkTree(tree,
                                            visited=set(),
                                            step=step,
                                            delay=delay)
            if reorder:
                tree = reorder.reorder(tree)

        tree = self.optimizer.optimize(tree)
        if reorder:
            tree = reorder.reorder(tree)

        tree = replace.replaceUndefined(tree, termname)

        name = self.rename(signalname)
        self.identical = identical
        self.add_node(name, label=signalname)
        self.visit(tree, name)
Example #9
0
 def walkBind(self, name, step=0):
     termname = util.toTermname(name)
     if not termname in self.terms:
         raise verror.DefinitionError("No such signals: %s" % str(name))
     tree = self.getTree(termname)
     walked_tree = self.walkTree(tree, visited=set(), step=step)
     return replace.replaceUndefined(walked_tree, termname)
Example #10
0
 def getBindSourceSubset(self, targets):
     visited_binddict = collections.OrderedDict()
     visited_sources = set()
     for target in targets:
         termname = util.toTermname(target)
         r_binds, r_sources = self.getBindSubset(termname, visited_sources)
         visited_sources |= r_sources
         visited_binddict = util.dictlistmerge(visited_binddict, r_binds)
     return visited_binddict, visited_sources
Example #11
0
 def getBindSourceSubset(self, targets):
     visited_binddict = collections.OrderedDict()
     visited_sources = set()
     for target in targets:
         termname = util.toTermname(target)
         r_binds, r_sources = self.getBindSubset(termname, visited_sources)
         visited_sources |= r_sources
         visited_binddict = util.dictlistmerge(visited_binddict, r_binds)
     return visited_binddict, visited_sources
Example #12
0
    def _toCode(self, terms, parameter, assign, always_clockedge, always_combination):
        # module header
        modulehead = self._modulehead(terms)

        code = ''
        # clock, reset, control input definition
        code += self._system_io(self.clock_name, self.reset_name, self.enable_name)

        # general signal definition
        for tk, tv in terms.items():
            termtype = self.getTermtype(tk)
            if signaltype.isInput(termtype) and tk == util.toTermname((self.topmodule, self.reset_name)): continue
            if signaltype.isInput(termtype) and tk == util.toTermname((self.topmodule, self.clock_name)): continue
            code += tv.tocode()

        for pk, pv in parameter.items():
            code += pv.tocode()

        # assign
        for ak, avv in assign.items():
            cnt = 0
            for av in avv:
                code += av.tocode()

        # always (clock edge)
        for ck, cvv in always_clockedge.items():
            for cv in cvv:
                code += cv.tocode()

        # always (combination)
        for ck, cvv in always_combination.items():
            for cv in cvv:
                code += cv.tocode()
            
        # module tail
        moduletail = '\nendmodule\n'

        ret = modulehead + code + moduletail
        
        if self.flat:
            ret = re.sub('\.', '_', ret)

        return ret
Example #13
0
 def _modulehead(self, terms):
     modulehead = ''
     modulehead += '`default_nettype none\n'
     modulehead += 'module ' + self.modulename + '('
     modulehead += '\n' + (' ' * self.num_indent)
     modulehead += self.clock_name + ', '
     modulehead += self.reset_name + ', '
     modulehead += self.enable_name + ', '
     modulehead += '\n' + (' ' * self.num_indent)
     
     for tk, tv in terms.items():
         scope = util.getScope(tk)
         if util.isTopmodule(scope):
             termtype = self.getTermtype(tk)
             if signaltype.isInput(termtype) and tk == util.toTermname((self.topmodule, self.reset_name)): continue
             if signaltype.isInput(termtype) and tk == util.toTermname((self.topmodule, self.clock_name)): continue
             if signaltype.isInput(termtype): modulehead += util.toFlatname(tk) + ', '
             elif signaltype.isInout(termtype): modulehead += util.toFlatname(tk) + ', '
             elif signaltype.isOutput(termtype): modulehead += util.toFlatname(tk) + ', '
     modulehead = modulehead[:-2] + ');\n\n'
     return modulehead
    def _declare_symbols(self, tree_names):
        symbols = {}
        for tree in tree_names:
            symbol_name = tree.replace('.', '_')
            scope = toTermname(str(tree))
            term = self.terms[scope]
            msb = eval_value(term.msb)
            lsb = eval_value(term.lsb)
            if msb == lsb:
                symbols[symbol_name] = Symbol(symbol_name)
            else:
                for i in range(lsb, msb + 1):
                    symbol_name_bit = term_manager().publish_new_name(symbol_name, i)
                    symbols[symbol_name_bit] = Symbol(symbol_name_bit)

        symbols = self._declare_renamed_symbols(symbols)
        return symbols
    def _declare_symbols(self, tree_names):
        symbols = {}
        for tree in tree_names:
            symbol_name = tree.replace('.', '_')
            scope = toTermname(str(tree))
            term = self.terms[scope]
            msb = eval_value(term.msb)
            lsb = eval_value(term.lsb)
            if msb == lsb:
                symbols[symbol_name] = Symbol(symbol_name)
            else:
                for i in range(lsb, msb + 1):
                    symbol_name_bit = term_manager().publish_new_name(
                        symbol_name, i)
                    symbols[symbol_name_bit] = Symbol(symbol_name_bit)

        symbols = self._declare_renamed_symbols(symbols)
        return symbols
Example #16
0
    def generate(self, signalname, identical=False, walk=True, step=1, reorder=False, delay=False):
        termname = util.toTermname(signalname)
        tree = self.treewalker.getTree(termname)
        if tree is None:
            raise verror.DefinitionError('No such signals: %s' % str(signalname))
        if walk: 
            tree = self.treewalker.walkTree(tree, visited=set(), step=step, delay=delay)
            if reorder: tree = reorder.reorder(tree)            

        tree = self.optimizer.optimize(tree)
        if reorder: tree = reorder.reorder(tree)

        tree = replace.replaceUndefined(tree, termname)

        name = self.rename(signalname)
        self.identical = identical
        self.add_node(name, label=signalname)
        self.visit(tree, name)
 def get_term(self, signal):
     scope = toTermname(signal)
     return self.terms[scope]
Example #18
0
    directives = analyzer.get_directives()
    terms = analyzer.getTerms()
    binddict = analyzer.getBinddict()

    optimizer = VerilogDataflowOptimizer(terms, binddict)

    optimizer.resolveConstant()
    resolved_terms = optimizer.getResolvedTerms()
    resolved_binddict = optimizer.getResolvedBinddict()
    constlist = optimizer.getConstlist()

    canalyzer = VerilogActiveConditionAnalyzer(options.topmodule, terms, binddict, 
                                               resolved_terms, resolved_binddict, constlist)

    for target in options.searchtarget:
        signal = util.toTermname(target)

        active_conditions = canalyzer.getActiveConditions( signal )
        #active_conditions = canalyzer.getActiveConditions( signal, condition=splitter.active_modify )
        #active_conditions = canalyzer.getActiveConditions( signal, condition=splitter.active_unmodify )

        print('Active Cases: %s' % signal)
        for fsm_sig, active_conditions in sorted(active_conditions.items(), key=lambda x:str(x[0])):
            print('FSM: %s' % fsm_sig)
            for state, active_condition in sorted(active_conditions, key=lambda x:str(x[0])):
                s = []
                s.append('state: %d -> ' % state)
                if active_condition: s.append(active_condition.tocode())
                else: s.append('empty')
                print(''.join(s))
Example #19
0
        if not os.path.exists(f): raise IOError("file not found: " + f)

    if len(filelist) == 0:
        showVersion()

    analyzer = VerilogDataflowAnalyzer(filelist, options.topmodule,
                                       noreorder=options.noreorder,
                                       nobind=options.nobind,
                                       preprocess_include=options.include,
                                       preprocess_define=options.define)
    analyzer.generate()

    directives = analyzer.get_directives()
    terms = analyzer.getTerms()
    binddict = analyzer.getBinddict()

    optimizer = VerilogDataflowOptimizer(terms, binddict)
    optimizer.resolveConstant()
    resolved_terms = optimizer.getResolvedTerms()
    resolved_binddict = optimizer.getResolvedBinddict()
    constlist = optimizer.getConstlist()

    merge = VerilogDataflowMerge(options.topmodule, terms, binddict,
                                 resolved_terms, resolved_binddict, constlist)

    for target in options.searchtarget:
        termname = util.toTermname(target)
        tree = merge.getTree(termname)
        print('target: %s' % target)
        print(tree.tostr())
Example #20
0
    if len(filelist) == 0:
        showVersion()

    analyzer = VerilogDataflowAnalyzer(filelist,
                                       options.topmodule,
                                       noreorder=options.noreorder,
                                       nobind=options.nobind,
                                       preprocess_include=options.include,
                                       preprocess_define=options.define)
    analyzer.generate()

    directives = analyzer.get_directives()
    terms = analyzer.getTerms()
    binddict = analyzer.getBinddict()

    optimizer = VerilogDataflowOptimizer(terms, binddict)
    optimizer.resolveConstant()
    resolved_terms = optimizer.getResolvedTerms()
    resolved_binddict = optimizer.getResolvedBinddict()
    constlist = optimizer.getConstlist()

    merge = VerilogDataflowMerge(options.topmodule, terms, binddict,
                                 resolved_terms, resolved_binddict, constlist)

    for target in options.searchtarget:
        termname = util.toTermname(target)
        tree = merge.getTree(termname)
        print('target: %s' % target)
        print(tree.tostr())
Example #21
0
def main():
    INFO = "Active condition analyzer"
    VERSION = pyverilog.utils.version.VERSION
    USAGE = "Usage: python example_active_analyzer.py -t TOPMODULE file ..."

    def showVersion():
        print(INFO)
        print(VERSION)
        print(USAGE)
        sys.exit()
    
    optparser = OptionParser()
    optparser.add_option("-v","--version",action="store_true",dest="showversion",
                         default=False,help="Show the version")
    optparser.add_option("-t","--top",dest="topmodule",
                         default="TOP",help="Top module, Default=TOP")
    optparser.add_option("-s","--search",dest="searchtarget",action="append",
                         default=[],help="Search Target Signal")
    (options, args) = optparser.parse_args()

    filelist = args
    if options.showversion:
        showVersion()

    for f in filelist:
        if not os.path.exists(f): raise IOError("file not found: " + f)

    if len(filelist) == 0:
        showVersion()

    analyzer = VerilogDataflowAnalyzer(filelist, options.topmodule)
    analyzer.generate()

    directives = analyzer.get_directives()
    terms = analyzer.getTerms()
    binddict = analyzer.getBinddict()

    optimizer = VerilogDataflowOptimizer(terms, binddict)

    optimizer.resolveConstant()
    resolved_terms = optimizer.getResolvedTerms()
    resolved_binddict = optimizer.getResolvedBinddict()
    constlist = optimizer.getConstlist()

    canalyzer = VerilogActiveConditionAnalyzer(options.topmodule, terms, binddict, 
                                               resolved_terms, resolved_binddict, constlist)

    for target in options.searchtarget:
        signal = util.toTermname(target)

        active_conditions = canalyzer.getActiveConditions( signal )
        #active_conditions = canalyzer.getActiveConditions( signal, condition=splitter.active_modify )
        #active_conditions = canalyzer.getActiveConditions( signal, condition=splitter.active_unmodify )

        print('Active Cases: %s' % signal)
        for fsm_sig, active_conditions in sorted(active_conditions.items(), key=lambda x:str(x[0])):
            print('FSM: %s' % fsm_sig)
            for state, active_condition in sorted(active_conditions, key=lambda x:str(x[0])):
                s = []
                s.append('state: %d -> ' % state)
                if active_condition: s.append(active_condition.tocode())
                else: s.append('empty')
                print(''.join(s))
 def get_term(self, signal):
     scope = toTermname(signal)
     return self.terms[scope]
Example #23
0
def main():
    INFO = "Active condition analyzer (Obsoluted)"
    VERSION = pyverilog.utils.version.VERSION
    USAGE = "Usage: python example_active_range.py -t TOPMODULE file ..."

    def showVersion():
        print(INFO)
        print(VERSION)
        print(USAGE)
        sys.exit()
    
    optparser = OptionParser()
    optparser.add_option("-v","--version",action="store_true",dest="showversion",
                         default=False,help="Show the version")
    optparser.add_option("-t","--top",dest="topmodule",
                         default="TOP",help="Top module, Default=TOP")
    optparser.add_option("-s","--search",dest="searchtarget",action="append",
                         default=[],help="Search Target Signal")
    (options, args) = optparser.parse_args()

    filelist = args
    if options.showversion:
        showVersion()

    for f in filelist:
        if not os.path.exists(f): raise IOError("file not found: " + f)

    if len(filelist) == 0:
        showVersion()

    analyzer = VerilogDataflowAnalyzer(filelist, options.topmodule)
    analyzer.generate()

    directives = analyzer.get_directives()
    terms = analyzer.getTerms()
    binddict = analyzer.getBinddict()

    optimizer = VerilogDataflowOptimizer(terms, binddict)

    optimizer.resolveConstant()
    resolved_terms = optimizer.getResolvedTerms()
    resolved_binddict = optimizer.getResolvedBinddict()
    constlist = optimizer.getConstlist()

    aanalyzer = VerilogActiveAnalyzer(options.topmodule, terms, binddict, 
                                      resolved_terms, resolved_binddict, constlist)

    for target in options.searchtarget:
        signal = util.toTermname(target)

        print('Active Conditions: %s' % signal)
        active_conditions = aanalyzer.getActiveConditions( signal )
        print(sorted(active_conditions, key=lambda x:str(x)))

        print('Changed Conditions')
        changed_conditions = aanalyzer.getChangedConditions( signal )
        print(sorted(changed_conditions, key=lambda x:str(x)))
    
        print('Changed Condition Dict')
        changed_conditiondict = aanalyzer.getChangedConditionsWithAssignments( signal )
        print(sorted(changed_conditiondict.items(), key=lambda x:str(x[0])))
    
        print('Unchanged Conditions')
        unchanged_conditions = aanalyzer.getUnchangedConditions( signal )
        print(sorted(unchanged_conditions, key=lambda x:str(x)))
Example #24
0
def main():
    INFO = "Dataflow merge module"
    VERSION = pyverilog.utils.version.VERSION
    USAGE = "Usage: python example_merge.py -t TOPMODULE file ..."

    def showVersion():
        print(INFO)
        print(VERSION)
        print(USAGE)
        sys.exit()
    
    optparser = OptionParser()
    optparser.add_option("-v","--version",action="store_true",dest="showversion",
                         default=False,help="Show the version")
    optparser.add_option("-I","--include",dest="include",action="append",
                         default=[],help="Include path")
    optparser.add_option("-D",dest="define",action="append",
                         default=[],help="Macro Definition")
    optparser.add_option("-t","--top",dest="topmodule",
                         default="TOP",help="Top module, Default=TOP")
    optparser.add_option("--nobind",action="store_true",dest="nobind",
                         default=False,help="No binding traversal, Default=False")
    optparser.add_option("--noreorder",action="store_true",dest="noreorder",
                         default=False,help="No reordering of binding dataflow, Default=False")
    optparser.add_option("-s","--search",dest="searchtarget",action="append",
                         default=[],help="Search Target Signal")
    (options, args) = optparser.parse_args()

    filelist = args
    if options.showversion:
        showVersion()

    for f in filelist:
        if not os.path.exists(f): raise IOError("file not found: " + f)

    if len(filelist) == 0:
        showVersion()

    analyzer = VerilogDataflowAnalyzer(filelist, options.topmodule,
                                       noreorder=options.noreorder,
                                       nobind=options.nobind,
                                       preprocess_include=options.include,
                                       preprocess_define=options.define)
    analyzer.generate()

    directives = analyzer.get_directives()
    terms = analyzer.getTerms()
    binddict = analyzer.getBinddict()

    optimizer = VerilogDataflowOptimizer(terms, binddict)
    optimizer.resolveConstant()
    resolved_terms = optimizer.getResolvedTerms()
    resolved_binddict = optimizer.getResolvedBinddict()
    constlist = optimizer.getConstlist()

    merge = VerilogDataflowMerge(options.topmodule, terms, binddict,
                                 resolved_terms, resolved_binddict, constlist)

    for target in options.searchtarget:
        termname = util.toTermname(target)
        tree = merge.getTree(termname)
        print('target: %s' % target)
        print(tree.tostr())
Example #25
0
def main():
    INFO = "Active condition analyzer (Obsoluted)"
    VERSION = pyverilog.utils.version.VERSION
    USAGE = "Usage: python example_active_range.py -t TOPMODULE file ..."

    def showVersion():
        print(INFO)
        print(VERSION)
        print(USAGE)
        sys.exit()

    optparser = OptionParser()
    optparser.add_option("-v",
                         "--version",
                         action="store_true",
                         dest="showversion",
                         default=False,
                         help="Show the version")
    optparser.add_option("-t",
                         "--top",
                         dest="topmodule",
                         default="TOP",
                         help="Top module, Default=TOP")
    optparser.add_option("-s",
                         "--search",
                         dest="searchtarget",
                         action="append",
                         default=[],
                         help="Search Target Signal")
    (options, args) = optparser.parse_args()

    filelist = args
    if options.showversion:
        showVersion()

    for f in filelist:
        if not os.path.exists(f): raise IOError("file not found: " + f)

    if len(filelist) == 0:
        showVersion()

    analyzer = VerilogDataflowAnalyzer(filelist, options.topmodule)
    analyzer.generate()

    directives = analyzer.get_directives()
    terms = analyzer.getTerms()
    binddict = analyzer.getBinddict()

    optimizer = VerilogDataflowOptimizer(terms, binddict)

    optimizer.resolveConstant()
    resolved_terms = optimizer.getResolvedTerms()
    resolved_binddict = optimizer.getResolvedBinddict()
    constlist = optimizer.getConstlist()

    aanalyzer = VerilogActiveAnalyzer(options.topmodule, terms, binddict,
                                      resolved_terms, resolved_binddict,
                                      constlist)

    for target in options.searchtarget:
        signal = util.toTermname(target)

        print('Active Conditions: %s' % signal)
        active_conditions = aanalyzer.getActiveConditions(signal)
        print(sorted(active_conditions, key=lambda x: str(x)))

        print('Changed Conditions')
        changed_conditions = aanalyzer.getChangedConditions(signal)
        print(sorted(changed_conditions, key=lambda x: str(x)))

        print('Changed Condition Dict')
        changed_conditiondict = aanalyzer.getChangedConditionsWithAssignments(
            signal)
        print(sorted(changed_conditiondict.items(), key=lambda x: str(x[0])))

        print('Unchanged Conditions')
        unchanged_conditions = aanalyzer.getUnchangedConditions(signal)
        print(sorted(unchanged_conditions, key=lambda x: str(x)))
Example #26
0
def main():
    INFO = "Dataflow merge module"
    VERSION = pyverilog.__version__
    USAGE = "Usage: python example_merge.py -t TOPMODULE file ..."

    def showVersion():
        print(INFO)
        print(VERSION)
        print(USAGE)
        sys.exit()

    optparser = OptionParser()
    optparser.add_option("-v",
                         "--version",
                         action="store_true",
                         dest="showversion",
                         default=False,
                         help="Show the version")
    optparser.add_option("-I",
                         "--include",
                         dest="include",
                         action="append",
                         default=[],
                         help="Include path")
    optparser.add_option("-D",
                         dest="define",
                         action="append",
                         default=[],
                         help="Macro Definition")
    optparser.add_option("-t",
                         "--top",
                         dest="topmodule",
                         default="TOP",
                         help="Top module, Default=TOP")
    optparser.add_option("--nobind",
                         action="store_true",
                         dest="nobind",
                         default=False,
                         help="No binding traversal, Default=False")
    optparser.add_option(
        "--noreorder",
        action="store_true",
        dest="noreorder",
        default=False,
        help="No reordering of binding dataflow, Default=False")
    optparser.add_option("-s",
                         "--search",
                         dest="searchtarget",
                         action="append",
                         default=[],
                         help="Search Target Signal")
    (options, args) = optparser.parse_args()

    filelist = args
    if options.showversion:
        showVersion()

    for f in filelist:
        if not os.path.exists(f):
            raise IOError("file not found: " + f)

    if len(filelist) == 0:
        showVersion()

    analyzer = VerilogDataflowAnalyzer(filelist,
                                       options.topmodule,
                                       noreorder=options.noreorder,
                                       nobind=options.nobind,
                                       preprocess_include=options.include,
                                       preprocess_define=options.define)
    analyzer.generate()

    directives = analyzer.get_directives()
    terms = analyzer.getTerms()
    binddict = analyzer.getBinddict()

    optimizer = VerilogDataflowOptimizer(terms, binddict)
    optimizer.resolveConstant()
    resolved_terms = optimizer.getResolvedTerms()
    resolved_binddict = optimizer.getResolvedBinddict()
    constlist = optimizer.getConstlist()

    merge = VerilogDataflowMerge(options.topmodule, terms, binddict,
                                 resolved_terms, resolved_binddict, constlist)

    for target in options.searchtarget:
        termname = util.toTermname(target)
        tree = merge.getTree(termname)
        print('target: %s' % target)
        print(tree.tostr())