def test_layout_combine(self):
"""combine_into_edge_map() method"""
layout = Layout()
layout.add((self.qr, 0))
layout.add((self.qr, 1))
another_layout = Layout()
another_layout.add((self.qr, 1))
another_layout.add((self.qr, 0))
edge_map = layout.combine_into_edge_map(another_layout)
self.assertDictEqual(edge_map, {(self.qr, 0): (self.qr, 1), (self.qr, 1): (self.qr, 0)})
def test_layout_combine(self):
"""combine_into_edge_map() method"""
layout = Layout()
layout.add(self.qr[0])
layout.add(self.qr[1])
another_layout = Layout()
another_layout.add(self.qr[1])
another_layout.add(self.qr[0])
edge_map = layout.combine_into_edge_map(another_layout)
self.assertDictEqual(edge_map, {self.qr[0]: self.qr[1], self.qr[1]: self.qr[0]})
def test_layout_combine_smaller(self):
"""combine_into_edge_map() method with another_layout is smaller and raises an Error"""
layout = Layout()
layout.add(self.qr[0])
layout.add(self.qr[1])
layout.add(self.qr[2])
another_layout = Layout()
another_layout.add(self.qr[1])
another_layout.add(self.qr[0])
with self.assertRaises(LayoutError):
_ = layout.combine_into_edge_map(another_layout)
def test_layout_combine_bigger(self):
"""combine_into_edge_map() method with another_layout is bigger"""
layout = Layout()
layout.add(self.qr[0])
layout.add(self.qr[1])
another_layout = Layout()
another_layout.add(self.qr[1])
another_layout.add(self.qr[0])
another_layout.add(self.qr[2])
edge_map = layout.combine_into_edge_map(another_layout)
self.assertDictEqual(edge_map, {
(self.qr, 0): (self.qr, 1),
(self.qr, 1): (self.qr, 0)
})
def _compose_layouts(self, initial_layout, pass_final_layout, qregs):
"""Return the real final_layout resulting from the composition
of an initial_layout with the final_layout reported by a pass.
The routing passes internally start with a trivial layout, as the
layout gets applied to the circuit prior to running them. So the
"final_layout" they report must be amended to account for the actual
initial_layout that was selected.
"""
trivial_layout = Layout.generate_trivial_layout(*qregs)
pass_final_layout = Layout({trivial_layout[v.index]: p
for v, p in pass_final_layout.get_virtual_bits().items()})
qubit_map = Layout.combine_into_edge_map(initial_layout, trivial_layout)
final_layout = {v: pass_final_layout[qubit_map[v]]
for v, _ in initial_layout.get_virtual_bits().items()}
return Layout(final_layout)
