def level_3_pass_manager(pass_manager_config: PassManagerConfig) -> PassManager:
"""Level 3 pass manager: heavy optimization by noise adaptive qubit mapping and
gate cancellation using commutativity rules and unitary synthesis.
This pass manager applies the user-given initial layout. If none is given, a search
for a perfect layout (i.e. one that satisfies all 2-qubit interactions) is conducted.
If no such layout is found, and device calibration information is available, the
circuit is mapped to the qubits with best readouts and to CX gates with highest fidelity.
The pass manager then transforms the circuit to match the coupling constraints.
It is then unrolled to the basis, and any flipped cx directions are fixed.
Finally, optimizations in the form of commutative gate cancellation, resynthesis
of two-qubit unitary blocks, and redundant reset removal are performed.
Note:
In simulators where ``coupling_map=None``, only the unrolling and
optimization stages are done.
Args:
pass_manager_config: configuration of the pass manager.
Returns:
a level 3 pass manager.
Raises:
TranspilerError: if the passmanager config is invalid.
"""
basis_gates = pass_manager_config.basis_gates
inst_map = pass_manager_config.inst_map
coupling_map = pass_manager_config.coupling_map
initial_layout = pass_manager_config.initial_layout
layout_method = pass_manager_config.layout_method or "sabre"
routing_method = pass_manager_config.routing_method or "sabre"
translation_method = pass_manager_config.translation_method or "translator"
scheduling_method = pass_manager_config.scheduling_method
instruction_durations = pass_manager_config.instruction_durations
seed_transpiler = pass_manager_config.seed_transpiler
backend_properties = pass_manager_config.backend_properties
approximation_degree = pass_manager_config.approximation_degree
unitary_synthesis_method = pass_manager_config.unitary_synthesis_method
timing_constraints = pass_manager_config.timing_constraints or TimingConstraints()
unitary_synthesis_plugin_config = pass_manager_config.unitary_synthesis_plugin_config
target = pass_manager_config.target
# 1. Unroll to 1q or 2q gates
_unroll3q = [
# Use unitary synthesis for basis aware decomposition of UnitaryGates
UnitarySynthesis(
basis_gates,
approximation_degree=approximation_degree,
method=unitary_synthesis_method,
plugin_config=unitary_synthesis_plugin_config,
min_qubits=3,
),
Unroll3qOrMore(),
]
# 2. Layout on good qubits if calibration info available, otherwise on dense links
_given_layout = SetLayout(initial_layout)
def _choose_layout_condition(property_set):
# layout hasn't been set yet
return not property_set["layout"]
def _csp_not_found_match(property_set):
# If a layout hasn't been set by the time we run csp we need to run layout
if property_set["layout"] is None:
return True
# if CSP layout stopped for any reason other than solution found we need
# to run layout since CSP didn't converge.
if (
property_set["CSPLayout_stop_reason"] is not None
and property_set["CSPLayout_stop_reason"] != "solution found"
):
return True
return False
# 2a. If layout method is not set, first try a trivial layout
_choose_layout_0 = (
[]
if pass_manager_config.layout_method
else [
TrivialLayout(coupling_map),
Layout2qDistance(coupling_map, property_name="trivial_layout_score"),
]
)
# 2b. If trivial layout wasn't perfect (ie no swaps are needed) then try
# using CSP layout to find a perfect layout
_choose_layout_1 = (
[]
if pass_manager_config.layout_method
else CSPLayout(coupling_map, call_limit=10000, time_limit=60, seed=seed_transpiler)
)
def _trivial_not_perfect(property_set):
# Verify that a trivial layout is perfect. If trivial_layout_score > 0
# the layout is not perfect. The layout property set is unconditionally
# set by trivial layout so we clear that before running CSP
if property_set["trivial_layout_score"] is not None:
if property_set["trivial_layout_score"] != 0:
return True
return False
# 2c. if CSP didn't converge on a solution use layout_method (dense).
if layout_method == "trivial":
_choose_layout_2 = TrivialLayout(coupling_map)
elif layout_method == "dense":
_choose_layout_2 = DenseLayout(coupling_map, backend_properties)
elif layout_method == "noise_adaptive":
_choose_layout_2 = NoiseAdaptiveLayout(backend_properties)
elif layout_method == "sabre":
_choose_layout_2 = SabreLayout(coupling_map, max_iterations=4, seed=seed_transpiler)
else:
raise TranspilerError("Invalid layout method %s." % layout_method)
# 3. Extend dag/layout with ancillas using the full coupling map
_embed = [FullAncillaAllocation(coupling_map), EnlargeWithAncilla(), ApplyLayout()]
# 4. Swap to fit the coupling map
_swap_check = CheckMap(coupling_map)
def _swap_condition(property_set):
return not property_set["is_swap_mapped"]
_swap = [BarrierBeforeFinalMeasurements()]
if routing_method == "basic":
_swap += [BasicSwap(coupling_map)]
elif routing_method == "stochastic":
_swap += [StochasticSwap(coupling_map, trials=200, seed=seed_transpiler)]
elif routing_method == "lookahead":
_swap += [LookaheadSwap(coupling_map, search_depth=5, search_width=6)]
elif routing_method == "sabre":
_swap += [SabreSwap(coupling_map, heuristic="decay", seed=seed_transpiler)]
elif routing_method == "none":
_swap += [
Error(
msg=(
"No routing method selected, but circuit is not routed to device. "
"CheckMap Error: {check_map_msg}"
),
action="raise",
)
]
else:
raise TranspilerError("Invalid routing method %s." % routing_method)
# 5. Unroll to the basis
if translation_method == "unroller":
_unroll = [Unroller(basis_gates)]
elif translation_method == "translator":
from qiskit.circuit.equivalence_library import SessionEquivalenceLibrary as sel
_unroll = [
UnitarySynthesis(
basis_gates,
approximation_degree=approximation_degree,
coupling_map=coupling_map,
backend_props=backend_properties,
plugin_config=unitary_synthesis_plugin_config,
method=unitary_synthesis_method,
),
UnrollCustomDefinitions(sel, basis_gates),
BasisTranslator(sel, basis_gates, target),
]
elif translation_method == "synthesis":
_unroll = [
UnitarySynthesis(
basis_gates,
approximation_degree=approximation_degree,
coupling_map=coupling_map,
backend_props=backend_properties,
method=unitary_synthesis_method,
plugin_config=unitary_synthesis_plugin_config,
min_qubits=3,
),
Unroll3qOrMore(),
Collect2qBlocks(),
ConsolidateBlocks(basis_gates=basis_gates),
UnitarySynthesis(
basis_gates,
approximation_degree=approximation_degree,
coupling_map=coupling_map,
backend_props=backend_properties,
method=unitary_synthesis_method,
plugin_config=unitary_synthesis_plugin_config,
),
]
else:
raise TranspilerError("Invalid translation method %s." % translation_method)
# 6. Fix any CX direction mismatch
_direction_check = [CheckGateDirection(coupling_map, target)]
def _direction_condition(property_set):
return not property_set["is_direction_mapped"]
_direction = [GateDirection(coupling_map, target)]
# 8. Optimize iteratively until no more change in depth. Removes useless gates
# after reset and before measure, commutes gates and optimizes contiguous blocks.
_depth_check = [Depth(), FixedPoint("depth")]
def _opt_control(property_set):
return not property_set["depth_fixed_point"]
_reset = [RemoveResetInZeroState()]
_meas = [OptimizeSwapBeforeMeasure(), RemoveDiagonalGatesBeforeMeasure()]
_opt = [
Collect2qBlocks(),
ConsolidateBlocks(basis_gates=basis_gates),
UnitarySynthesis(
basis_gates,
approximation_degree=approximation_degree,
coupling_map=coupling_map,
backend_props=backend_properties,
method=unitary_synthesis_method,
plugin_config=unitary_synthesis_plugin_config,
),
Optimize1qGatesDecomposition(basis_gates),
CommutativeCancellation(),
]
# 9. Unify all durations (either SI, or convert to dt if known)
# Schedule the circuit only when scheduling_method is supplied
_time_unit_setup = [ContainsInstruction("delay")]
_time_unit_conversion = [TimeUnitConversion(instruction_durations)]
def _contains_delay(property_set):
return property_set["contains_delay"]
_scheduling = []
if scheduling_method:
_scheduling += _time_unit_conversion
if scheduling_method in {"alap", "as_late_as_possible"}:
_scheduling += [ALAPSchedule(instruction_durations)]
elif scheduling_method in {"asap", "as_soon_as_possible"}:
_scheduling += [ASAPSchedule(instruction_durations)]
else:
raise TranspilerError("Invalid scheduling method %s." % scheduling_method)
# 10. Call measure alignment. Should come after scheduling.
if (
timing_constraints.granularity != 1
or timing_constraints.min_length != 1
or timing_constraints.acquire_alignment != 1
):
_alignments = [
ValidatePulseGates(
granularity=timing_constraints.granularity, min_length=timing_constraints.min_length
),
AlignMeasures(alignment=timing_constraints.acquire_alignment),
]
else:
_alignments = []
# Build pass manager
pm3 = PassManager()
pm3.append(_unroll3q)
pm3.append(_reset + _meas)
if coupling_map or initial_layout:
pm3.append(_given_layout)
pm3.append(_choose_layout_0, condition=_choose_layout_condition)
pm3.append(_choose_layout_1, condition=_trivial_not_perfect)
pm3.append(_choose_layout_2, condition=_csp_not_found_match)
pm3.append(_embed)
pm3.append(_swap_check)
pm3.append(_swap, condition=_swap_condition)
pm3.append(_unroll)
if (coupling_map and not coupling_map.is_symmetric) or (
target is not None and target.get_non_global_operation_names(strict_direction=True)
):
pm3.append(_direction_check)
pm3.append(_direction, condition=_direction_condition)
pm3.append(_reset)
# For transpiling to a target we need to run GateDirection in the
# optimization loop to correct for incorrect directions that might be
# inserted by UnitarySynthesis which is direction aware but only via
# the coupling map which with a target doesn't give a full picture
if target is not None:
pm3.append(_depth_check + _opt + _unroll + _direction, do_while=_opt_control)
else:
pm3.append(_depth_check + _opt + _unroll, do_while=_opt_control)
else:
pm3.append(_reset)
pm3.append(_depth_check + _opt + _unroll, do_while=_opt_control)
if inst_map and inst_map.has_custom_gate():
pm3.append(PulseGates(inst_map=inst_map))
if scheduling_method:
pm3.append(_scheduling)
elif instruction_durations:
pm3.append(_time_unit_setup)
pm3.append(_time_unit_conversion, condition=_contains_delay)
pm3.append(_alignments)
return pm3
def level_1_pass_manager(
pass_manager_config: PassManagerConfig) -> PassManager:
"""Level 1 pass manager: light optimization by simple adjacent gate collapsing.
This pass manager applies the user-given initial layout. If none is given,
and a trivial layout (i-th virtual -> i-th physical) makes the circuit fit
the coupling map, that is used.
Otherwise, the circuit is mapped to the most densely connected coupling subgraph,
and swaps are inserted to map. Any unused physical qubit is allocated as ancilla space.
The pass manager then unrolls the circuit to the desired basis, and transforms the
circuit to match the coupling map. Finally, optimizations in the form of adjacent
gate collapse and redundant reset removal are performed.
Note:
In simulators where ``coupling_map=None``, only the unrolling and
optimization stages are done.
Args:
pass_manager_config: configuration of the pass manager.
Returns:
a level 1 pass manager.
Raises:
TranspilerError: if the passmanager config is invalid.
"""
basis_gates = pass_manager_config.basis_gates
inst_map = pass_manager_config.inst_map
coupling_map = pass_manager_config.coupling_map
initial_layout = pass_manager_config.initial_layout
layout_method = pass_manager_config.layout_method or "dense"
routing_method = pass_manager_config.routing_method or "stochastic"
translation_method = pass_manager_config.translation_method or "translator"
scheduling_method = pass_manager_config.scheduling_method
instruction_durations = pass_manager_config.instruction_durations
seed_transpiler = pass_manager_config.seed_transpiler
backend_properties = pass_manager_config.backend_properties
approximation_degree = pass_manager_config.approximation_degree
unitary_synthesis_method = pass_manager_config.unitary_synthesis_method
unitary_synthesis_plugin_config = pass_manager_config.unitary_synthesis_plugin_config
timing_constraints = pass_manager_config.timing_constraints or TimingConstraints(
)
target = pass_manager_config.target
# 1. Use trivial layout if no layout given
_given_layout = SetLayout(initial_layout)
_choose_layout_and_score = [
TrivialLayout(coupling_map),
Layout2qDistance(coupling_map, property_name="trivial_layout_score"),
]
def _choose_layout_condition(property_set):
return not property_set["layout"]
# 2. Decompose so only 1-qubit and 2-qubit gates remain
_unroll3q = [
# Use unitary synthesis for basis aware decomposition of UnitaryGates
UnitarySynthesis(
basis_gates,
approximation_degree=approximation_degree,
method=unitary_synthesis_method,
min_qubits=3,
plugin_config=unitary_synthesis_plugin_config,
),
Unroll3qOrMore(),
]
# 3. Use a better layout on densely connected qubits, if circuit needs swaps
if layout_method == "trivial":
_improve_layout = TrivialLayout(coupling_map)
elif layout_method == "dense":
_improve_layout = DenseLayout(coupling_map, backend_properties)
elif layout_method == "noise_adaptive":
_improve_layout = NoiseAdaptiveLayout(backend_properties)
elif layout_method == "sabre":
_improve_layout = SabreLayout(coupling_map,
max_iterations=2,
seed=seed_transpiler)
else:
raise TranspilerError("Invalid layout method %s." % layout_method)
def _not_perfect_yet(property_set):
return (property_set["trivial_layout_score"] is not None
and property_set["trivial_layout_score"] != 0)
# 4. Extend dag/layout with ancillas using the full coupling map
_embed = [
FullAncillaAllocation(coupling_map),
EnlargeWithAncilla(),
ApplyLayout()
]
# 5. Swap to fit the coupling map
_swap_check = CheckMap(coupling_map)
def _swap_condition(property_set):
return not property_set["is_swap_mapped"]
_swap = [BarrierBeforeFinalMeasurements()]
if routing_method == "basic":
_swap += [BasicSwap(coupling_map)]
elif routing_method == "stochastic":
_swap += [
StochasticSwap(coupling_map, trials=20, seed=seed_transpiler)
]
elif routing_method == "lookahead":
_swap += [LookaheadSwap(coupling_map, search_depth=4, search_width=4)]
elif routing_method == "sabre":
_swap += [
SabreSwap(coupling_map,
heuristic="lookahead",
seed=seed_transpiler)
]
elif routing_method == "none":
_swap += [
Error(
msg=
("No routing method selected, but circuit is not routed to device. "
"CheckMap Error: {check_map_msg}"),
action="raise",
)
]
else:
raise TranspilerError("Invalid routing method %s." % routing_method)
# 6. Unroll to the basis
if translation_method == "unroller":
_unroll = [Unroller(basis_gates)]
elif translation_method == "translator":
from qiskit.circuit.equivalence_library import SessionEquivalenceLibrary as sel
_unroll = [
# Use unitary synthesis for basis aware decomposition of UnitaryGates before
# custom unrolling
UnitarySynthesis(
basis_gates,
approximation_degree=approximation_degree,
coupling_map=coupling_map,
method=unitary_synthesis_method,
backend_props=backend_properties,
plugin_config=unitary_synthesis_plugin_config,
),
UnrollCustomDefinitions(sel, basis_gates),
BasisTranslator(sel, basis_gates, target),
]
elif translation_method == "synthesis":
_unroll = [
# Use unitary synthesis for basis aware decomposition of UnitaryGates before
# collection
UnitarySynthesis(
basis_gates,
approximation_degree=approximation_degree,
coupling_map=coupling_map,
method=unitary_synthesis_method,
backend_props=backend_properties,
min_qubits=3,
),
Unroll3qOrMore(),
Collect2qBlocks(),
ConsolidateBlocks(basis_gates=basis_gates),
UnitarySynthesis(
basis_gates,
approximation_degree=approximation_degree,
coupling_map=coupling_map,
method=unitary_synthesis_method,
backend_props=backend_properties,
plugin_config=unitary_synthesis_plugin_config,
),
]
else:
raise TranspilerError("Invalid translation method %s." %
translation_method)
# 7. Fix any bad CX directions
_direction_check = [CheckGateDirection(coupling_map, target)]
def _direction_condition(property_set):
return not property_set["is_direction_mapped"]
_direction = [GateDirection(coupling_map, target)]
# 8. Remove zero-state reset
_reset = RemoveResetInZeroState()
# 9. Merge 1q rotations and cancel CNOT gates iteratively until no more change in depth
_depth_check = [Depth(), FixedPoint("depth")]
def _opt_control(property_set):
return not property_set["depth_fixed_point"]
_opt = [Optimize1qGatesDecomposition(basis_gates), CXCancellation()]
# 10. Unify all durations (either SI, or convert to dt if known)
# Schedule the circuit only when scheduling_method is supplied
_time_unit_setup = [ContainsInstruction("delay")]
_time_unit_conversion = [TimeUnitConversion(instruction_durations)]
def _contains_delay(property_set):
return property_set["contains_delay"]
_scheduling = []
if scheduling_method:
_scheduling += _time_unit_conversion
if scheduling_method in {"alap", "as_late_as_possible"}:
_scheduling += [ALAPSchedule(instruction_durations)]
elif scheduling_method in {"asap", "as_soon_as_possible"}:
_scheduling += [ASAPSchedule(instruction_durations)]
else:
raise TranspilerError("Invalid scheduling method %s." %
scheduling_method)
# 11. Call measure alignment. Should come after scheduling.
if (timing_constraints.granularity != 1
or timing_constraints.min_length != 1
or timing_constraints.acquire_alignment != 1):
_alignments = [
ValidatePulseGates(granularity=timing_constraints.granularity,
min_length=timing_constraints.min_length),
AlignMeasures(alignment=timing_constraints.acquire_alignment),
]
else:
_alignments = []
# Build pass manager
pm1 = PassManager()
if coupling_map or initial_layout:
pm1.append(_given_layout)
pm1.append(_unroll3q)
pm1.append(_choose_layout_and_score,
condition=_choose_layout_condition)
pm1.append(_improve_layout, condition=_not_perfect_yet)
pm1.append(_embed)
pm1.append(_swap_check)
pm1.append(_swap, condition=_swap_condition)
pm1.append(_unroll)
if (coupling_map and not coupling_map.is_symmetric) or (
target is not None
and target.get_non_global_operation_names(strict_direction=True)):
pm1.append(_direction_check)
pm1.append(_direction, condition=_direction_condition)
pm1.append(_reset)
pm1.append(_depth_check + _opt + _unroll, do_while=_opt_control)
if inst_map and inst_map.has_custom_gate():
pm1.append(PulseGates(inst_map=inst_map))
if scheduling_method:
pm1.append(_scheduling)
elif instruction_durations:
pm1.append(_time_unit_setup)
pm1.append(_time_unit_conversion, condition=_contains_delay)
pm1.append(_alignments)
return pm1
def level_0_pass_manager(
pass_manager_config: PassManagerConfig) -> PassManager:
"""Level 0 pass manager: no explicit optimization other than mapping to backend.
This pass manager applies the user-given initial layout. If none is given, a trivial
layout consisting of mapping the i-th virtual qubit to the i-th physical qubit is used.
Any unused physical qubit is allocated as ancilla space.
The pass manager then unrolls the circuit to the desired basis, and transforms the
circuit to match the coupling map.
Note:
In simulators where ``coupling_map=None``, only the unrolling and
optimization stages are done.
Args:
pass_manager_config: configuration of the pass manager.
Returns:
a level 0 pass manager.
Raises:
TranspilerError: if the passmanager config is invalid.
"""
basis_gates = pass_manager_config.basis_gates
inst_map = pass_manager_config.inst_map
coupling_map = pass_manager_config.coupling_map
initial_layout = pass_manager_config.initial_layout
layout_method = pass_manager_config.layout_method or "trivial"
routing_method = pass_manager_config.routing_method or "stochastic"
translation_method = pass_manager_config.translation_method or "translator"
scheduling_method = pass_manager_config.scheduling_method
instruction_durations = pass_manager_config.instruction_durations
seed_transpiler = pass_manager_config.seed_transpiler
backend_properties = pass_manager_config.backend_properties
approximation_degree = pass_manager_config.approximation_degree
timing_constraints = pass_manager_config.timing_constraints or TimingConstraints(
)
unitary_synthesis_method = pass_manager_config.unitary_synthesis_method
unitary_synthesis_plugin_config = pass_manager_config.unitary_synthesis_plugin_config
target = pass_manager_config.target
# 1. Decompose so only 1-qubit and 2-qubit gates remain
_unroll3q = [
# Use unitary synthesis for basis aware decomposition of UnitaryGates
UnitarySynthesis(
basis_gates,
approximation_degree=approximation_degree,
method=unitary_synthesis_method,
min_qubits=3,
plugin_config=unitary_synthesis_plugin_config,
),
Unroll3qOrMore(),
]
# 2. Choose an initial layout if not set by user (default: trivial layout)
_given_layout = SetLayout(initial_layout)
def _choose_layout_condition(property_set):
return not property_set["layout"]
if layout_method == "trivial":
_choose_layout = TrivialLayout(coupling_map)
elif layout_method == "dense":
_choose_layout = DenseLayout(coupling_map, backend_properties)
elif layout_method == "noise_adaptive":
_choose_layout = NoiseAdaptiveLayout(backend_properties)
elif layout_method == "sabre":
_choose_layout = SabreLayout(coupling_map,
max_iterations=1,
seed=seed_transpiler)
else:
raise TranspilerError("Invalid layout method %s." % layout_method)
# 3. Extend dag/layout with ancillas using the full coupling map
_embed = [
FullAncillaAllocation(coupling_map),
EnlargeWithAncilla(),
ApplyLayout()
]
# 4. Swap to fit the coupling map
_swap_check = CheckMap(coupling_map)
def _swap_condition(property_set):
return not property_set["is_swap_mapped"]
_swap = [BarrierBeforeFinalMeasurements()]
if routing_method == "basic":
_swap += [BasicSwap(coupling_map)]
elif routing_method == "stochastic":
_swap += [
StochasticSwap(coupling_map, trials=20, seed=seed_transpiler)
]
elif routing_method == "lookahead":
_swap += [LookaheadSwap(coupling_map, search_depth=2, search_width=2)]
elif routing_method == "sabre":
_swap += [
SabreSwap(coupling_map, heuristic="basic", seed=seed_transpiler)
]
elif routing_method == "none":
_swap += [
Error(
msg=
("No routing method selected, but circuit is not routed to device. "
"CheckMap Error: {check_map_msg}"),
action="raise",
)
]
else:
raise TranspilerError("Invalid routing method %s." % routing_method)
# 5. Unroll to the basis
if translation_method == "unroller":
_unroll = [Unroller(basis_gates)]
elif translation_method == "translator":
from qiskit.circuit.equivalence_library import SessionEquivalenceLibrary as sel
_unroll = [
UnitarySynthesis(
basis_gates,
approximation_degree=approximation_degree,
coupling_map=coupling_map,
backend_props=backend_properties,
method=unitary_synthesis_method,
plugin_config=unitary_synthesis_plugin_config,
),
UnrollCustomDefinitions(sel, basis_gates),
BasisTranslator(sel, basis_gates, target),
]
elif translation_method == "synthesis":
_unroll = [
UnitarySynthesis(
basis_gates,
approximation_degree=approximation_degree,
coupling_map=coupling_map,
backend_props=backend_properties,
method=unitary_synthesis_method,
min_qubits=3,
plugin_config=unitary_synthesis_plugin_config,
),
Unroll3qOrMore(),
Collect2qBlocks(),
Collect1qRuns(),
ConsolidateBlocks(basis_gates=basis_gates),
UnitarySynthesis(
basis_gates,
approximation_degree=approximation_degree,
coupling_map=coupling_map,
backend_props=backend_properties,
method=unitary_synthesis_method,
plugin_config=unitary_synthesis_plugin_config,
),
]
else:
raise TranspilerError("Invalid translation method %s." %
translation_method)
# 6. Fix any bad CX directions
_direction_check = [CheckGateDirection(coupling_map, target)]
def _direction_condition(property_set):
return not property_set["is_direction_mapped"]
_direction = [GateDirection(coupling_map, target)]
# 7. Unify all durations (either SI, or convert to dt if known)
# Schedule the circuit only when scheduling_method is supplied
_time_unit_setup = [ContainsInstruction("delay")]
_time_unit_conversion = [TimeUnitConversion(instruction_durations)]
def _contains_delay(property_set):
return property_set["contains_delay"]
_scheduling = []
if scheduling_method:
_scheduling += _time_unit_conversion
if scheduling_method in {"alap", "as_late_as_possible"}:
_scheduling += [ALAPSchedule(instruction_durations)]
elif scheduling_method in {"asap", "as_soon_as_possible"}:
_scheduling += [ASAPSchedule(instruction_durations)]
else:
raise TranspilerError("Invalid scheduling method %s." %
scheduling_method)
# 8. Call measure alignment. Should come after scheduling.
if (timing_constraints.granularity != 1
or timing_constraints.min_length != 1
or timing_constraints.acquire_alignment != 1):
_alignments = [
ValidatePulseGates(granularity=timing_constraints.granularity,
min_length=timing_constraints.min_length),
AlignMeasures(alignment=timing_constraints.acquire_alignment),
]
else:
_alignments = []
# Build pass manager
pm0 = PassManager()
if coupling_map or initial_layout:
pm0.append(_given_layout)
pm0.append(_unroll3q)
pm0.append(_choose_layout, condition=_choose_layout_condition)
pm0.append(_embed)
pm0.append(_swap_check)
pm0.append(_swap, condition=_swap_condition)
pm0.append(_unroll)
if (coupling_map and not coupling_map.is_symmetric) or (
target is not None
and target.get_non_global_operation_names(strict_direction=True)):
pm0.append(_direction_check)
pm0.append(_direction, condition=_direction_condition)
pm0.append(_unroll)
if inst_map and inst_map.has_custom_gate():
pm0.append(PulseGates(inst_map=inst_map))
if scheduling_method:
pm0.append(_scheduling)
elif instruction_durations:
pm0.append(_time_unit_setup)
pm0.append(_time_unit_conversion, condition=_contains_delay)
pm0.append(_alignments)
return pm0
def level_2_pass_manager(
pass_manager_config: PassManagerConfig) -> PassManager:
"""Level 2 pass manager: medium optimization by initial layout selection and
gate cancellation using commutativity rules.
This pass manager applies the user-given initial layout. If none is given, a search
for a perfect layout (i.e. one that satisfies all 2-qubit interactions) is conducted.
If no such layout is found, qubits are laid out on the most densely connected subset
which also exhibits the best gate fidelities.
The pass manager then transforms the circuit to match the coupling constraints.
It is then unrolled to the basis, and any flipped cx directions are fixed.
Finally, optimizations in the form of commutative gate cancellation and redundant
reset removal are performed.
Note:
In simulators where ``coupling_map=None``, only the unrolling and
optimization stages are done.
Args:
pass_manager_config: configuration of the pass manager.
Returns:
a level 2 pass manager.
Raises:
TranspilerError: if the passmanager config is invalid.
"""
basis_gates = pass_manager_config.basis_gates
inst_map = pass_manager_config.inst_map
coupling_map = pass_manager_config.coupling_map
initial_layout = pass_manager_config.initial_layout
layout_method = pass_manager_config.layout_method or "dense"
routing_method = pass_manager_config.routing_method or "stochastic"
translation_method = pass_manager_config.translation_method or "translator"
scheduling_method = pass_manager_config.scheduling_method
instruction_durations = pass_manager_config.instruction_durations
seed_transpiler = pass_manager_config.seed_transpiler
backend_properties = pass_manager_config.backend_properties
approximation_degree = pass_manager_config.approximation_degree
unitary_synthesis_method = pass_manager_config.unitary_synthesis_method
timing_constraints = pass_manager_config.timing_constraints or TimingConstraints(
)
# 1. Search for a perfect layout, or choose a dense layout, if no layout given
_given_layout = SetLayout(initial_layout)
def _choose_layout_condition(property_set):
# layout hasn't been set yet
return not property_set["layout"]
# 1a. If layout_method is not set, first try a trivial layout
_choose_layout_0 = ([] if pass_manager_config.layout_method else [
TrivialLayout(coupling_map),
Layout2qDistance(coupling_map, property_name="trivial_layout_score"),
])
# 1b. If a trivial layout wasn't perfect (ie no swaps are needed) then try using
# CSP layout to find a perfect layout
_choose_layout_1 = ([] if pass_manager_config.layout_method else CSPLayout(
coupling_map, call_limit=1000, time_limit=10, seed=seed_transpiler))
def _trivial_not_perfect(property_set):
# Verify that a trivial layout is perfect. If trivial_layout_score > 0
# the layout is not perfect. The layout is unconditionally set by trivial
# layout so we need to clear it before contuing.
if property_set["trivial_layout_score"] is not None:
if property_set["trivial_layout_score"] != 0:
property_set["layout"]._wrapped = None
return True
return False
def _csp_not_found_match(property_set):
# If a layout hasn't been set by the time we run csp we need to run layout
if property_set["layout"] is None:
return True
# if CSP layout stopped for any reason other than solution found we need
# to run layout since CSP didn't converge.
if (property_set["CSPLayout_stop_reason"] is not None
and property_set["CSPLayout_stop_reason"] != "solution found"):
return True
return False
# 1c. if CSP layout doesn't converge on a solution use layout_method (dense) to get a layout
if layout_method == "trivial":
_choose_layout_2 = TrivialLayout(coupling_map)
elif layout_method == "dense":
_choose_layout_2 = DenseLayout(coupling_map, backend_properties)
elif layout_method == "noise_adaptive":
_choose_layout_2 = NoiseAdaptiveLayout(backend_properties)
elif layout_method == "sabre":
_choose_layout_2 = SabreLayout(coupling_map,
max_iterations=2,
seed=seed_transpiler)
else:
raise TranspilerError("Invalid layout method %s." % layout_method)
# 2. Extend dag/layout with ancillas using the full coupling map
_embed = [
FullAncillaAllocation(coupling_map),
EnlargeWithAncilla(),
ApplyLayout()
]
# 3. Unroll to 1q or 2q gates
_unroll3q = [
# Use unitary synthesis for basis aware decomposition of UnitaryGates
UnitarySynthesis(
basis_gates,
approximation_degree=approximation_degree,
coupling_map=coupling_map,
backend_props=backend_properties,
method=unitary_synthesis_method,
min_qubits=3,
),
Unroll3qOrMore(),
]
# 4. Swap to fit the coupling map
_swap_check = CheckMap(coupling_map)
def _swap_condition(property_set):
return not property_set["is_swap_mapped"]
_swap = [BarrierBeforeFinalMeasurements()]
if routing_method == "basic":
_swap += [BasicSwap(coupling_map)]
elif routing_method == "stochastic":
_swap += [
StochasticSwap(coupling_map, trials=20, seed=seed_transpiler)
]
elif routing_method == "lookahead":
_swap += [LookaheadSwap(coupling_map, search_depth=5, search_width=5)]
elif routing_method == "sabre":
_swap += [
SabreSwap(coupling_map, heuristic="decay", seed=seed_transpiler)
]
elif routing_method == "none":
_swap += [
Error(
msg=
"No routing method selected, but circuit is not routed to device. "
"CheckMap Error: {check_map_msg}",
action="raise",
)
]
else:
raise TranspilerError("Invalid routing method %s." % routing_method)
# 5. Unroll to the basis
if translation_method == "unroller":
_unroll = [Unroller(basis_gates)]
elif translation_method == "translator":
from qiskit.circuit.equivalence_library import SessionEquivalenceLibrary as sel
_unroll = [
# Use unitary synthesis for basis aware decomposition of UnitaryGates before
# custom unrolling
UnitarySynthesis(
basis_gates,
approximation_degree=approximation_degree,
coupling_map=coupling_map,
backend_props=backend_properties,
method=unitary_synthesis_method,
),
UnrollCustomDefinitions(sel, basis_gates),
BasisTranslator(sel, basis_gates),
]
elif translation_method == "synthesis":
_unroll = [
# Use unitary synthesis for basis aware decomposition of UnitaryGates before
# collection
UnitarySynthesis(
basis_gates,
approximation_degree=approximation_degree,
coupling_map=coupling_map,
backend_props=backend_properties,
method=unitary_synthesis_method,
min_qubits=3,
),
Unroll3qOrMore(),
Collect2qBlocks(),
ConsolidateBlocks(basis_gates=basis_gates),
UnitarySynthesis(
basis_gates,
approximation_degree=approximation_degree,
coupling_map=coupling_map,
backend_props=backend_properties,
method=unitary_synthesis_method,
),
]
else:
raise TranspilerError("Invalid translation method %s." %
translation_method)
# 6. Fix any bad CX directions
_direction_check = [CheckGateDirection(coupling_map)]
def _direction_condition(property_set):
return not property_set["is_direction_mapped"]
_direction = [GateDirection(coupling_map)]
# 7. Remove zero-state reset
_reset = RemoveResetInZeroState()
# 8. 1q rotation merge and commutative cancellation iteratively until no more change in depth
_depth_check = [Depth(), FixedPoint("depth")]
def _opt_control(property_set):
return not property_set["depth_fixed_point"]
_opt = [
Optimize1qGatesDecomposition(basis_gates),
CommutativeCancellation(basis_gates=basis_gates),
]
# 9. Unify all durations (either SI, or convert to dt if known)
# Schedule the circuit only when scheduling_method is supplied
_scheduling = [TimeUnitConversion(instruction_durations)]
if scheduling_method:
if scheduling_method in {"alap", "as_late_as_possible"}:
_scheduling += [ALAPSchedule(instruction_durations)]
elif scheduling_method in {"asap", "as_soon_as_possible"}:
_scheduling += [ASAPSchedule(instruction_durations)]
else:
raise TranspilerError("Invalid scheduling method %s." %
scheduling_method)
# 10. Call measure alignment. Should come after scheduling.
_alignments = [
ValidatePulseGates(granularity=timing_constraints.granularity,
min_length=timing_constraints.min_length),
AlignMeasures(alignment=timing_constraints.acquire_alignment),
]
# Build pass manager
pm2 = PassManager()
if coupling_map or initial_layout:
pm2.append(_given_layout)
pm2.append(_choose_layout_0, condition=_choose_layout_condition)
pm2.append(_choose_layout_1, condition=_trivial_not_perfect)
pm2.append(_choose_layout_2, condition=_csp_not_found_match)
pm2.append(_embed)
pm2.append(_unroll3q)
pm2.append(_swap_check)
pm2.append(_swap, condition=_swap_condition)
pm2.append(_unroll)
if coupling_map and not coupling_map.is_symmetric:
pm2.append(_direction_check)
pm2.append(_direction, condition=_direction_condition)
pm2.append(_reset)
pm2.append(_depth_check + _opt + _unroll, do_while=_opt_control)
if inst_map and inst_map.has_custom_gate():
pm2.append(PulseGates(inst_map=inst_map))
pm2.append(_scheduling)
pm2.append(_alignments)
return pm2
def level_1_pass_manager(
pass_manager_config: PassManagerConfig) -> PassManager:
"""Level 1 pass manager: light optimization by simple adjacent gate collapsing.
This pass manager applies the user-given initial layout. If none is given,
and a trivial layout (i-th virtual -> i-th physical) makes the circuit fit
the coupling map, that is used.
Otherwise, the circuit is mapped to the most densely connected coupling subgraph,
and swaps are inserted to map. Any unused physical qubit is allocated as ancilla space.
The pass manager then unrolls the circuit to the desired basis, and transforms the
circuit to match the coupling map. Finally, optimizations in the form of adjacent
gate collapse and redundant reset removal are performed.
Note:
In simulators where ``coupling_map=None``, only the unrolling and
optimization stages are done.
Args:
pass_manager_config: configuration of the pass manager.
Returns:
a level 1 pass manager.
Raises:
TranspilerError: if the passmanager config is invalid.
"""
basis_gates = pass_manager_config.basis_gates
inst_map = pass_manager_config.inst_map
coupling_map = pass_manager_config.coupling_map
initial_layout = pass_manager_config.initial_layout
layout_method = pass_manager_config.layout_method or "dense"
routing_method = pass_manager_config.routing_method or "stochastic"
translation_method = pass_manager_config.translation_method or "translator"
scheduling_method = pass_manager_config.scheduling_method
instruction_durations = pass_manager_config.instruction_durations
seed_transpiler = pass_manager_config.seed_transpiler
backend_properties = pass_manager_config.backend_properties
approximation_degree = pass_manager_config.approximation_degree
unitary_synthesis_method = pass_manager_config.unitary_synthesis_method
unitary_synthesis_plugin_config = pass_manager_config.unitary_synthesis_plugin_config
timing_constraints = pass_manager_config.timing_constraints or TimingConstraints(
)
target = pass_manager_config.target
# 1. Use trivial layout if no layout given if that isn't perfect use vf2 layout
_given_layout = SetLayout(initial_layout)
def _choose_layout_condition(property_set):
return not property_set["layout"]
def _trivial_not_perfect(property_set):
# Verify that a trivial layout is perfect. If trivial_layout_score > 0
# the layout is not perfect. The layout is unconditionally set by trivial
# layout so we need to clear it before contuing.
if (property_set["trivial_layout_score"] is not None
and property_set["trivial_layout_score"] != 0):
return True
return False
def _vf2_match_not_found(property_set):
# If a layout hasn't been set by the time we run vf2 layout we need to
# run layout
if property_set["layout"] is None:
return True
# if VF2 layout stopped for any reason other than solution found we need
# to run layout since VF2 didn't converge.
if (property_set["VF2Layout_stop_reason"] is not None
and property_set["VF2Layout_stop_reason"]
is not VF2LayoutStopReason.SOLUTION_FOUND):
return True
return False
_choose_layout_0 = ([] if pass_manager_config.layout_method else [
TrivialLayout(coupling_map),
Layout2qDistance(coupling_map, property_name="trivial_layout_score"),
])
_choose_layout_1 = ([] if pass_manager_config.layout_method else VF2Layout(
coupling_map,
seed=seed_transpiler,
call_limit=int(5e4), # Set call limit to ~100ms with retworkx 0.10.2
time_limit=0.1,
properties=backend_properties,
target=target,
))
# 2. Decompose so only 1-qubit and 2-qubit gates remain
_unroll3q = [
# Use unitary synthesis for basis aware decomposition of UnitaryGates
UnitarySynthesis(
basis_gates,
approximation_degree=approximation_degree,
method=unitary_synthesis_method,
min_qubits=3,
plugin_config=unitary_synthesis_plugin_config,
target=target,
),
Unroll3qOrMore(),
]
# 3. Use a better layout on densely connected qubits, if circuit needs swaps
if layout_method == "trivial":
_improve_layout = TrivialLayout(coupling_map)
elif layout_method == "dense":
_improve_layout = DenseLayout(coupling_map,
backend_properties,
target=target)
elif layout_method == "noise_adaptive":
_improve_layout = NoiseAdaptiveLayout(backend_properties)
elif layout_method == "sabre":
_improve_layout = SabreLayout(coupling_map,
max_iterations=2,
seed=seed_transpiler)
else:
raise TranspilerError("Invalid layout method %s." % layout_method)
# 4. Extend dag/layout with ancillas using the full coupling map
_embed = [
FullAncillaAllocation(coupling_map),
EnlargeWithAncilla(),
ApplyLayout()
]
# 5. Swap to fit the coupling map
_swap_check = CheckMap(coupling_map)
def _swap_condition(property_set):
return not property_set["is_swap_mapped"]
_swap = [BarrierBeforeFinalMeasurements()]
if routing_method == "basic":
_swap += [BasicSwap(coupling_map)]
elif routing_method == "stochastic":
_swap += [
StochasticSwap(coupling_map, trials=20, seed=seed_transpiler)
]
elif routing_method == "lookahead":
_swap += [LookaheadSwap(coupling_map, search_depth=4, search_width=4)]
elif routing_method == "sabre":
_swap += [
SabreSwap(coupling_map,
heuristic="lookahead",
seed=seed_transpiler)
]
elif routing_method == "none":
_swap += [
Error(
msg=
("No routing method selected, but circuit is not routed to device. "
"CheckMap Error: {check_map_msg}"),
action="raise",
)
]
else:
raise TranspilerError("Invalid routing method %s." % routing_method)
# 6. Unroll to the basis
if translation_method == "unroller":
_unroll = [Unroller(basis_gates)]
elif translation_method == "translator":
from qiskit.circuit.equivalence_library import SessionEquivalenceLibrary as sel
_unroll = [
# Use unitary synthesis for basis aware decomposition of UnitaryGates before
# custom unrolling
UnitarySynthesis(
basis_gates,
approximation_degree=approximation_degree,
coupling_map=coupling_map,
method=unitary_synthesis_method,
backend_props=backend_properties,
plugin_config=unitary_synthesis_plugin_config,
target=target,
),
UnrollCustomDefinitions(sel, basis_gates),
BasisTranslator(sel, basis_gates, target),
]
elif translation_method == "synthesis":
_unroll = [
# Use unitary synthesis for basis aware decomposition of UnitaryGates before
# collection
UnitarySynthesis(
basis_gates,
approximation_degree=approximation_degree,
coupling_map=coupling_map,
method=unitary_synthesis_method,
backend_props=backend_properties,
min_qubits=3,
target=target,
),
Unroll3qOrMore(),
Collect2qBlocks(),
ConsolidateBlocks(basis_gates=basis_gates, target=target),
UnitarySynthesis(
basis_gates,
approximation_degree=approximation_degree,
coupling_map=coupling_map,
method=unitary_synthesis_method,
backend_props=backend_properties,
plugin_config=unitary_synthesis_plugin_config,
target=target,
),
]
else:
raise TranspilerError("Invalid translation method %s." %
translation_method)
# 7. Fix any bad CX directions
_direction_check = [CheckGateDirection(coupling_map, target)]
def _direction_condition(property_set):
return not property_set["is_direction_mapped"]
_direction = [GateDirection(coupling_map, target)]
# 8. Remove zero-state reset
_reset = RemoveResetInZeroState()
# 9. Merge 1q rotations and cancel CNOT gates iteratively until no more change in depth
# or size of circuit
_depth_check = [Depth(), FixedPoint("depth")]
_size_check = [Size(), FixedPoint("size")]
def _opt_control(property_set):
return (not property_set["depth_fixed_point"]) or (
not property_set["size_fixed_point"])
_opt = [Optimize1qGatesDecomposition(basis_gates), CXCancellation()]
# Build pass manager
pm1 = PassManager()
if coupling_map or initial_layout:
pm1.append(_given_layout)
pm1.append(_unroll3q)
pm1.append(_choose_layout_0, condition=_choose_layout_condition)
pm1.append(_choose_layout_1, condition=_trivial_not_perfect)
pm1.append(_improve_layout, condition=_vf2_match_not_found)
pm1.append(_embed)
pm1.append(_swap_check)
pm1.append(_swap, condition=_swap_condition)
pm1.append(_unroll)
if (coupling_map and not coupling_map.is_symmetric) or (
target is not None
and target.get_non_global_operation_names(strict_direction=True)):
pm1.append(_direction_check)
pm1.append(_direction, condition=_direction_condition)
pm1.append(_reset)
pm1.append(_depth_check + _size_check)
pm1.append(_opt + _unroll + _depth_check + _size_check,
do_while=_opt_control)
if inst_map and inst_map.has_custom_gate():
pm1.append(PulseGates(inst_map=inst_map))
# 10. Unify all durations (either SI, or convert to dt if known)
# Schedule the circuit only when scheduling_method is supplied
# Apply alignment analysis regardless of scheduling for delay validation.
if scheduling_method:
# Do scheduling after unit conversion.
scheduler = {
"alap": ALAPScheduleAnalysis,
"as_late_as_possible": ALAPScheduleAnalysis,
"asap": ASAPScheduleAnalysis,
"as_soon_as_possible": ASAPScheduleAnalysis,
}
pm1.append(TimeUnitConversion(instruction_durations))
try:
pm1.append(scheduler[scheduling_method](instruction_durations))
except KeyError as ex:
raise TranspilerError("Invalid scheduling method %s." %
scheduling_method) from ex
elif instruction_durations:
# No scheduling. But do unit conversion for delays.
def _contains_delay(property_set):
return property_set["contains_delay"]
pm1.append(ContainsInstruction("delay"))
pm1.append(TimeUnitConversion(instruction_durations),
condition=_contains_delay)
if (timing_constraints.granularity != 1
or timing_constraints.min_length != 1
or timing_constraints.acquire_alignment != 1
or timing_constraints.pulse_alignment != 1):
# Run alignment analysis regardless of scheduling.
def _require_alignment(property_set):
return property_set["reschedule_required"]
pm1.append(
InstructionDurationCheck(
acquire_alignment=timing_constraints.acquire_alignment,
pulse_alignment=timing_constraints.pulse_alignment,
))
pm1.append(
ConstrainedReschedule(
acquire_alignment=timing_constraints.acquire_alignment,
pulse_alignment=timing_constraints.pulse_alignment,
),
condition=_require_alignment,
)
pm1.append(
ValidatePulseGates(
granularity=timing_constraints.granularity,
min_length=timing_constraints.min_length,
))
if scheduling_method:
# Call padding pass if circuit is scheduled
pm1.append(PadDelay())
return pm1
def generate_scheduling(instruction_durations, scheduling_method,
timing_constraints, inst_map):
"""Generate a post optimization scheduling :class:`~qiskit.transpiler.PassManager`
Args:
instruction_durations (dict): The dictionary of instruction durations
scheduling_method (str): The scheduling method to use, can either be
``'asap'``/``'as_soon_as_possible'`` or
``'alap'``/``'as_late_as_possible'``
timing_constraints (TimingConstraints): Hardware time alignment restrictions.
inst_map (InstructionScheduleMap): Mapping object that maps gate to schedule.
Returns:
PassManager: The scheduling pass manager
Raises:
TranspilerError: If the ``scheduling_method`` kwarg is not a valid value
"""
scheduling = PassManager()
if inst_map and inst_map.has_custom_gate():
scheduling.append(PulseGates(inst_map=inst_map))
if scheduling_method:
# Do scheduling after unit conversion.
scheduler = {
"alap": ALAPScheduleAnalysis,
"as_late_as_possible": ALAPScheduleAnalysis,
"asap": ASAPScheduleAnalysis,
"as_soon_as_possible": ASAPScheduleAnalysis,
}
scheduling.append(TimeUnitConversion(instruction_durations))
try:
scheduling.append(
scheduler[scheduling_method](instruction_durations))
except KeyError as ex:
raise TranspilerError("Invalid scheduling method %s." %
scheduling_method) from ex
elif instruction_durations:
# No scheduling. But do unit conversion for delays.
def _contains_delay(property_set):
return property_set["contains_delay"]
scheduling.append(ContainsInstruction("delay"))
scheduling.append(TimeUnitConversion(instruction_durations),
condition=_contains_delay)
if (timing_constraints.granularity != 1
or timing_constraints.min_length != 1
or timing_constraints.acquire_alignment != 1
or timing_constraints.pulse_alignment != 1):
# Run alignment analysis regardless of scheduling.
def _require_alignment(property_set):
return property_set["reschedule_required"]
scheduling.append(
InstructionDurationCheck(
acquire_alignment=timing_constraints.acquire_alignment,
pulse_alignment=timing_constraints.pulse_alignment,
))
scheduling.append(
ConstrainedReschedule(
acquire_alignment=timing_constraints.acquire_alignment,
pulse_alignment=timing_constraints.pulse_alignment,
),
condition=_require_alignment,
)
scheduling.append(
ValidatePulseGates(
granularity=timing_constraints.granularity,
min_length=timing_constraints.min_length,
))
if scheduling_method:
# Call padding pass if circuit is scheduled
scheduling.append(PadDelay())
return scheduling