def test_parser1():
test_path=(pathlib.Path(__file__).parent / 'test1.sp').resolve()
sp = SpiceParser(test_path,"test1",0)
g = sp.sp_parser()[0]
assert len(g["graph"].nodes()) == 10
assert len(g["ports"]) == 4
assert 'vss' in g["ports"] # A port name 0 should be changed to vss
def test_parser3():
test_path=(pathlib.Path(__file__).parent / 'ota.sp').resolve()
sp = SpiceParser(test_path,"ota",0)
g = sp.sp_parser()[0]
assert len(g["graph"].nodes()) == 25 # number of nodes in OTA
test_path=(pathlib.Path(__file__).parent / 'basic_template.sp').resolve()
lib_sp = SpiceParser(test_path)
lib_list = lib_sp.sp_parser()
#shutil.rmtree("library_graphs")
assert len(lib_list) == 31 ## 18 subckt in basic template
return(g["graph"], lib_list)
def test_parser1():
sp = SpiceParser("test1.sp")
g = sp.sp_parser()
assert len(g.nodes()) == 10
def compiler(input_ckt, design_name, flat=0, Debug=False):
"""
Wrapper file
"""
input_dir = '/'.join(str(input_ckt).split('/')[0:-1]) + '/'
logging.info("Reading subckt %s", input_ckt)
sp = SpiceParser(input_ckt, design_name, flat)
circuit = sp.sp_parser()[0]
logging.info("template parent path: %s", pathlib.Path(__file__).parent)
lib_path = (pathlib.Path(__file__).parent /
'../basic_library/basic_template.sp').resolve()
logging.info("template library path: %s", lib_path)
basic_lib = SpiceParser(lib_path)
library = basic_lib.sp_parser()
lib_path = (pathlib.Path(__file__).parent /
'../basic_library/user_template.sp').resolve()
user_lib = SpiceParser(lib_path)
library += user_lib.sp_parser()
library = sorted(library,
key=lambda k: max_connectivity(k["graph"]),
reverse=True)
if Debug == True:
_write_circuit_graph(circuit["name"], circuit["graph"],
"./circuit_graphs/")
for lib_circuit in library:
_write_circuit_graph(lib_circuit["name"], lib_circuit["graph"],
"./circuit_graphs/")
hier_graph_dict = read_inputs(circuit["name"], circuit["graph"])
design_setup = read_setup(input_dir + design_name + '.setup')
UPDATED_CIRCUIT_LIST = []
for circuit_name, circuit in hier_graph_dict.items():
logging.info("START MATCHING in circuit: %s", circuit_name)
G1 = circuit["graph"]
if circuit_name in design_setup['DIGITAL']:
mapped_graph_list = _mapped_graph_list(G1, library,
design_setup['CLOCK'], True)
else:
define_SD(G1, design_setup['POWER'], design_setup['GND'],
design_setup['CLOCK'])
logging.info("no of nodes: %i", len(G1))
add_parallel_caps(G1)
add_series_res(G1)
preprocess_stack(G1)
initial_size = len(G1)
delta = 1
while delta > 0:
logging.info("CHECKING stacked transistors")
preprocess_stack(G1)
delta = initial_size - len(G1)
initial_size = len(G1)
mapped_graph_list = _mapped_graph_list(G1, library,
design_setup['CLOCK'],
False)
updated_circuit, Grest = reduce_graph(G1, mapped_graph_list, library)
check_nodes(updated_circuit)
UPDATED_CIRCUIT_LIST.extend(updated_circuit)
UPDATED_CIRCUIT_LIST.append({
"name": circuit_name,
"graph": Grest,
"ports": circuit["ports"],
"ports_match": circuit["connection"],
"size": len(Grest.nodes())
})
return UPDATED_CIRCUIT_LIST
def test_parser3():
sp = SpiceParser("ota.sp")
g = sp.sp_parser()
assert len(g.nodes()) == 25
def test_parser2():
test_path=(pathlib.Path(__file__).parent / 'test2.sp').resolve()
sp = SpiceParser(test_path,"test2",0)
g = sp.sp_parser()[0]
assert len(g["graph"].nodes()) == 12