Example #1
0
def DIV(i):
    (l, y, z) = (datafile.block[i].out, datafile.block[i].op1, datafile.block[i].op2)
    register.storereg('edx')
    register.storereg('eax')
    
    datafile.blockout.append("xor edx, edx")
    try :
        int(z)
        reg = register.emptyregister(i,['edx', 'eax'])
        datafile.blockout.append('mov ' + reg + ", " + z)
        datafile.zprime = reg
    except :
        if datafile.addressdescriptor[z] == None:
            reg = register.emptyregister(i,['edx', 'eax'])
            datafile.blockout.append('mov ' + reg + ", " + register.mem(z))
            datafile.zprime = reg

    try :
        int(y)
        datafile.yprime = "eax"
        datafile.blockout.append("mov eax," + y)
    except :
        datafile.blockout.append("mov eax," + register.mem(y))
        datafile.yprime = "eax"
    datafile.L = "eax"
    datafile.blockout.append("idiv " +reg)
    register.UpdateAddressDescriptor(l)
    register.freereg(y, i)
    register.freereg(z, i)
Example #2
0
def ARRAYLOAD(i):
    (l, y, z) = (datafile.block[i].out, datafile.block[i].op1, datafile.block[i].op2)
    try:
        int(z)
        datafile.zprime = z
    except:
        register.getz(z)
    if y in datafile.allvariables:
        if datafile.addressdescriptor[y] != None:
            datafile.yprime = datafile.addressdescriptor[y]
        else:
            datafile.yprime = y
    m = []
    reg = None
    if register.mem(datafile.zprime) in datafile.registerlist:
        m.append(register.mem(datafile.zprime))
    if register.mem(datafile.yprime) in datafile.registerlist:
        reg = register.mem(datafile.yprime)
    if not reg:
        reg = register.emptyregister(i,m)
    datafile.L = reg
    t = register.mem(datafile.yprime)
    if t[0] == "[":
        datafile.blockout.append("lea " + reg + "," + t)
    else:
        datafile.blockout.append("mov " + reg + "," + t)
    if (y in datafile.globalsection) or (y in datafile.setofarray) or (y in datafile.setofList):
        datafile.blockout.append("add " + reg + "," + register.mem(datafile.zprime))
    else:
        datafile.blockout.append("sub " + reg + "," + register.mem(datafile.zprime))
    datafile.blockout.append("mov " + reg  + ", [" + reg + "]"  )
    register.UpdateAddressDescriptor(l)
Example #3
0
def DIV(i):
    (l, y, z) = (datafile.block[i].out, datafile.block[i].op1, datafile.block[i].op2)
    register.storereg('edx')
    
    datafile.blockout.append("xor %edx, %edx")
    datafile.lineno = datafile.lineno + 1
    try :
        int(z)
        reg = register.emptyregister(i,['edx', 'eax'])
        datafile.blockout.append('mov $' + z + ", %" + reg)
        datafile.lineno = datafile.lineno + 1
        datafile.zprime = reg
    except :
        if datafile.addressdescriptor[z] == 'eax':
            register.storereg(z)
        register.getz(z)
        pass
    register.getreg(l, y, i, 'eax')
    try :
        int(y)
        datafile.yprime = y
    except :
        pass
    register.gety(y)
    datafile.blockout.append("idivl " + register.mem(datafile.zprime))
    datafile.lineno = datafile.lineno + 1
    register.UpdateAddressDescriptor(l)
    register.freereg(y, i)
    register.freereg(z, i)
Example #4
0
def ADD(i):
    (y, z, l) = (datafile.block[i].op1, datafile.block[i].op2, datafile.block[i].out)
    #check if z is constant or not if not get the momloc or register if it is already in register since op r_i , r_j is similar to op r_i , M
    print y,", ", z, ", ", l ,"these are y and l in add function"
    try :
        int(z)
        datafile.zprime = z
    except :
        register.getz(z)
        pass
    #get the register for L to store the output of the operation 
    register.getreg(l, y, i)
    # print datafile.L , "Hello"
    try :
        int(y)
        datafile.yprime = y
    except :
        pass
    register.gety(y)
    
    datafile.blockout.append("addl " + register.mem(datafile.zprime) + ", " + register.mem(datafile.L))
    # datafile.blockout.append("lineno" + str(datafile.lineno))
    datafile.lineno = datafile.lineno + 1
    register.UpdateAddressDescriptor(l)
    register.freereg(y, i)
    register.freereg(z, i)
Example #5
0
def DEFASSIGN(i):
    (y,l) = (datafile.block[i].op2,datafile.block[i].out)
    try :
        int(y)
        datafile.yprime = y
        if datafile.addressdescriptor[l] != None:
            reg = datafile.addressdescriptor[l]
        else:
            reg = register.emptyregister(i)
            datafile.L = reg
            register.UpdateAddressDescriptor(l)
    except :
        if datafile.addressdescriptor[y] != None:
            if datafile.addressdescriptor[l] != None:
                datafile.blockout.append("mov " + '['+datafile.addressdescriptor[l]+']' + "," + datafile.addressdescriptor[y])
                register.freereg(y, i)
                return
            else:
                reg = register.emptyregister(i,left=[datafile.addressdescriptor[y]])
                datafile.blockout.append('mov ' + reg + ',' + register.mem(l))
                datafile.blockout.append("mov " + '['+reg+']' + "," + datafile.addressdescriptor[y])
                register.freereg(y, i)
                register.freereg(reg, i)
                return
        else:
            reg = register.emptyregister(i) # for l
            reg1 = register.emptyregister(i,[reg]) # for y
            datafile.blockout.append("mov " + reg1 + "," + register.mem(y))
            datafile.L = reg
            if datafile.addressdescriptor[l] == None:
                datafile.blockout.append("mov " + reg + ", "+ register.mem(l))
            else:
                datafile.blockout.append("mov " + reg + ", "+ datafile.addressdescriptor[l])
            datafile.blockout.append("mov " + '['+reg+']' + "," + reg1)
            datafile.yprime = reg1
            register.UpdateAddressDescriptor(l)
            register.freereg(y,i)
            register.freereg(reg1,i)
            return 
    reg1 = register.emptyregister(i, [reg])
    datafile.blockout.append("mov " + reg1 + "," + y)
    datafile.blockout.append("mov " + '['+reg+']' + "," + reg1)
    register.freereg(y, i)
    register.freereg(reg, i)
Example #6
0
def ASSIGN(i):
    (y,l) = (datafile.block[i].op2,datafile.block[i].out)
    register.getreg(l,y,i)
    try :
        int(y)
        datafile.yprime = y
    except :
        pass
    register.gety(y)
    register.UpdateAddressDescriptor(l)
    register.freereg(y, i)
Example #7
0
def ARRAYLOAD(i):
    (l, y, z) = (datafile.block[i].out, datafile.block[i].op1, datafile.block[i].op2)
    #sb $0, array1($3)  index addressing mode is used here
    try:
        int(z)
        datafile.zprime = z
    except:
        register.getz(z)
    
    reg = register.emptyregister(i)
    datafile.blockout.append("movl " + register.mem(datafile.zprime) + ", " + register.mem(reg))
    datafile.lineno = datafile.lineno + 1
    datafile.L = reg
    datafile.blockout.append("movl " + y + "(, %" + reg +", 4 ), %" + reg )
    datafile.lineno = datafile.lineno + 1
    register.UpdateAddressDescriptor(l)
Example #8
0
def ADD(i):
    (y, z, l) = (datafile.block[i].op1, datafile.block[i].op2, datafile.block[i].out)
    try :
        int(z)
        datafile.zprime = z
    except :
        register.getz(z)
        pass
    register.getreg(l, y, i)
    try :
        int(y)
        datafile.yprime = y
    except :
        pass
    register.gety(y)
    
    datafile.blockout.append("add " + register.mem(datafile.L) + ", "+register.mem(datafile.zprime) )
    datafile.lineno = datafile.lineno + 1
    register.UpdateAddressDescriptor(l)
    register.freereg(y, i)
    register.freereg(z, i)
Example #9
0
def READ(i): 
    datafile.blockout.append("push eax")
    l = datafile.block[i].out
    try:
        datafile.addressdescriptor[l]
        k = datafile.addressdescriptor[l]
        datafile.blockout.append("mov eax, esp")
    except:
        k = register.mem(l)
        datafile.blockout.append("lea eax," + k)
    datafile.blockout.append("push eax")
    datafile.blockout.append("push formatin")
    datafile.blockout.append("call scanf")
    datafile.blockout.append("add esp, 8")
    try:
        datafile.addressdescriptor[l]
        datafile.blockout.append("mov " + k + ", [esp]")
    except:
        reg = register.emptyregister(i, ['eax'])
        datafile.blockout.append("mov " + reg + ", [esp]")
        datafile.L = reg
        register.UpdateAddressDescriptor(l)
    datafile.blockout.append('pop eax')
Example #10
0
def XOR(i):
    (y, z, l) = (datafile.block[i].op1, datafile.block[i].op2, datafile.block[i].out)
    #check if z is constant or not if not get the momloc or register if it is already in register since op r_i , r_j is similar to op r_i , M
    try :
        int(z)
        datafile.zprime = z
    except :
        register.getz(z)
        pass
    #get the register for L to store the output of the operation 
    register.getreg(l, y, i)
    try :
        int(y)
        datafile.yprime = y
    except :
        pass
    register.gety(y)
    
    datafile.blockout.append("xor " + register.mem(datafile.L) + ", " + register.mem(datafile.zprime) )
    datafile.lineno = datafile.lineno + 1
    register.UpdateAddressDescriptor(l)
    register.freereg(y, i)
    register.freereg(z, i)