def test_ibh(args=None):
args = tb_default_args(args)
numbytes = 13
clock = Clock(0, frequency=50e6)
glbl = Global(clock, None)
led = Signal(intbv(0)[8:])
pmod = Signal(intbv(0)[8:])
uart_tx = Signal(bool(0))
uart_rx = Signal(bool(0))
uart_dtr = Signal(bool(0))
uart_rts = Signal(bool(0))
uartmdl = UARTModel()
@myhdl.block
def bench_ibh():
tbclk = clock.gen()
tbmdl = uartmdl.process(glbl, uart_tx, uart_rx)
tbdut = icestick_blinky_host(clock, led, pmod,
uart_tx, uart_rx,
uart_dtr, uart_rts)
@instance
def tbstim():
yield delay(1000)
# send a write that should enable all five LEDs
pkt = CommandPacket(False, address=0x20, vals=[0xFF])
for bb in pkt.rawbytes:
uartmdl.write(bb)
waitticks = int((1/115200.) / 1e-9) * 10 * 28
yield delay(waitticks)
timeout = 100
yield delay(waitticks)
# get the response packet
for ii in range(PACKET_LENGTH):
rb = uartmdl.read()
while rb is None and timeout > 0:
yield clock.posedge
rb = uartmdl.read()
timeout -= 1
if rb is None:
raise TimeoutError
# the last byte should be the byte written
assert rb == 0xFF
yield delay(1000)
raise StopSimulation
return tbclk, tbmdl, tbdut, tbstim
run_testbench(bench_ibh, args=args)
inst = icestick_blinky_host(
clock, led, pmod,
uart_tx, uart_rx, uart_dtr, uart_rts
)
tb_convert(inst)
def test_uart(args=None):
# @todo: get numbytes from args
numbytes = 13
clock = Clock(0, frequency=12e6)
reset = Reset(0, active=0, isasync=True)
glbl = Global(clock, reset)
mdlsi, mdlso = Signal(bool(1)), Signal(bool(1))
uartmdl = UARTModel()
fifobus = FIFOBus()
@myhdl.block
def bench_uart():
tbmdl = uartmdl.process(glbl, mdlsi, mdlso)
tbdut = uartlite(glbl, fifobus, mdlso, mdlsi)
tbclk = clock.gen()
@always_comb
def tblpbk():
fifobus.read.next = not fifobus.empty
fifobus.write.next = fifobus.read_valid
fifobus.write_data.next = fifobus.read_data
@instance
def tbstim():
yield reset.pulse(33)
yield delay(1000)
yield clock.posedge
for ii in range(numbytes):
wb = randint(0, 255)
print("send {:02X}".format(wb))
uartmdl.write(wb)
timeout = ((clock.frequency / uartmdl.baudrate) * 40)
rb = uartmdl.read()
while rb is None and timeout > 0:
yield clock.posedge
rb = uartmdl.read()
timeout -= 1
if rb is None:
raise TimeoutError
print("received {:02X}".format(rb))
assert rb == wb, "{:02X} != {:02X}".format(rb, wb)
yield delay(100)
raise StopSimulation
return tbdut, tbmdl, tbclk, tblpbk, tbstim
run_testbench(bench_uart, args=args)
def test_uart_model(args=None):
# @todo: get numbytes from args
numbytes = 7
clock = Clock(0, frequency=50e6)
reset = Reset(0, active=0, isasync=True)
glbl = Global(clock, reset)
si, so = Signal(bool(1)), Signal(bool(1))
uartmdl = UARTModel()
@myhdl.block
def bench_uart_model():
tbdut = uartmdl.process(glbl, si, so)
tbclk = clock.gen()
@always_comb
def tblpbk():
si.next = so
@instance
def tbstim():
yield reset.pulse(33)
yield delay(1000)
yield clock.posedge
for ii in range(numbytes):
wb = randint(0, 255)
print("send {:02X}".format(wb))
uartmdl.write(wb)
timeout = ((clock.frequency / uartmdl.baudrate) * 20)
rb = uartmdl.read()
while rb is None and timeout > 0:
yield clock.posedge
rb = uartmdl.read()
timeout -= 1
if rb is None:
raise TimeoutError
print("received {:02X}".format(rb))
assert rb == wb, "{:02X} != {:02X}".format(rb, wb)
yield delay(100)
raise StopSimulation
return tbdut, tbclk, tblpbk, tbstim
run_testbench(bench_uart_model, args=args)
def test_ibh(args=None):
args = tb_default_args(args)
numbytes = 13
clock = Clock(0, frequency=50e6)
reset = Reset(0, active=0, async=True)
glbl = Global(clock, reset)
led = Signal(intbv(0)[8:])
sw = Signal(intbv(1)[8:])
pmod = Signal(intbv(0)[8:])
uart_tx = Signal(bool(0))
uart_rx = Signal(bool(0))
uartmdl = UARTModel()
baudrate = uartmdl.baudrate
baudticks = int((1 / baudrate) / 1e-9)
def _bench_ibh():
tbclk = clock.gen()
tbmdl = uartmdl.process(glbl, uart_tx, uart_rx)
tbdut = atlys_blinky_host(clock, reset, led, sw, pmod, uart_tx,
uart_rx)
@instance
def tbstim():
yield reset.pulse(33)
yield delay(1000)
# test loopback
for ii in range(5):
wb = randint(0, 255)
uartmdl.write(wb)
# wait for the send (return)
yield delay(baudticks * (8 + 2) + 2 * baudticks)
rb = uartmdl.read()
assert rb == wb
sw.next = 0
yield delay(100)
# send a write that should enable all five LEDs
pkt = CommandPacket(False, address=0x20, vals=[0xFF])
for bb in pkt.rawbytes:
uartmdl.write(bb)
waitticks = baudticks * 10 * 28
yield delay(waitticks)
timeout = 100
yield delay(waitticks)
# get the response packet
for ii in range(PACKET_LENGTH):
rb = uartmdl.read()
while rb is None and timeout > 0:
yield clock.posedge
rb = uartmdl.read()
timeout -= 1
if rb is None:
raise Exception("TimeoutError")
# the last byte should be the byte written
assert rb == 0xFF
yield delay(1000)
raise StopSimulation
return tbclk, tbmdl, tbdut, tbstim
run_testbench(_bench_ibh, args=args)
myhdl.toVerilog.directory = 'output'
myhdl.toVerilog(atlys_blinky_host, clock, reset, led, sw, pmod, uart_tx,
uart_rx)
