def gen_simulation(self, selfp):
while not self.reader.done:
yield
yield from riffa.channel_write(selfp.simulator, self.tbmem.cmd_tx, [0xF1005])
while not self.tbmem.flushack:
yield
addr = self.data_to_send[0]
num_errors = 0
for i in range(self.data_to_send[1]):
if self.tbmem.read_mem(addr) != self.results[i]:
num_errors += 1
if num_errors <= 10:
print(hex(addr) + ": " + str(self.tbmem.read_mem(addr)) + " (should be " + str(self.results[i]) + ")")
addr += 4
if num_errors > 10:
print("And " + str(num_errors-10) + " more.")
i = self.data_to_send[1] - 2
addr = self.data_to_send[0] + (i << 2)
print(hex(addr) + ": " + str(self.tbmem.read_mem(addr)))
print(self.results[i])
i = self.data_to_send[1] - 1
addr = self.data_to_send[0] + (i << 2)
print(hex(addr) + ": " + str(self.tbmem.read_mem(addr)))
print(self.results[i])
yield 10
def run_matmul(run):
# send arguments to DUT
yield from riffa.channel_write(selfp.simulator, self.rx, arg_struct)
# wait for return value
ret = yield from riffa.channel_read(selfp.simulator, self.tx)
yield from self.tbmem.send_flush_command(selfp)
print("MatMul run " + str(run) + " finished. Reports " + str(riffa.pack(ret)) + " cycles taken.")
# verify result matrix
num_errors = 0
for i in range(dim_i):
for j in range(dim_j):
# address "i"th word in range
addr = baseC + ((i * dim_j + j) << log2_int(self.wordsize//8))
# compare to expected
if self.tbmem.read_mem(addr) != expectedC[i][j]:
num_errors += 1
# print a few errors but not too many
if num_errors <= 10:
print(hex(addr) + ": " + str(self.tbmem.read_mem(addr)) + " (expected " + str(expectedC[i][j]) + ")")
if num_errors > 10:
print(str(num_errors) + " errors total.")
yield
def gen_simulation(self, selfp):
# memory area to work on
baseaddr = ?? ## TODO
size = ?? ## TODO
# function argument to send (as list of 32 bit words)
arg_struct = [baseaddr, size, ??] ## TODO
# expected return value (as list of 32 bit words)
expected_ret = [??] ## TODO
# expected memory modifications (in memory words of size 'wordsize')
expected_results = [??] ## TODO
# send arguments to DUT
yield from riffa.channel_write(selfp.simulator, self.rx, arg_struct)
# wait for return value
ret = yield from riffa.channel_read(selfp.simulator, self.tx)
# check return value
if ret != expected_ret:
## TODO
print("Wrong return value! Expected " + str(expected_ret) + ", received " + str(ret))
# check memory modifications
num_errors = 0
for i in range(size):
# address "i"th word in range
addr = baseaddr + i << log2_int(self.wordsize//8)
# compare to expected
if self.tbmem.read_mem(addr) != expected_results[i]:
num_errors += 1
# print a few errors but not too many
if num_errors <= 10:
print(hex(addr) + ": " + str(self.tbmem.read_mem(addr)) + " (expected " + str(expected_results[i]) + ")")
if num_errors > 10:
print("And " + str(num_errors-10) + " more.")
def run_matmul(run):
# send arguments to DUT
yield from riffa.channel_write(selfp.simulator, self.rx,
arg_struct)
# wait for return value
ret = yield from riffa.channel_read(selfp.simulator, self.tx)
yield from self.tbmem.send_flush_command(selfp)
print("MatMul run " + str(run) + " finished. Reports " +
str(riffa.pack(ret)) + " cycles taken.")
# verify result matrix
num_errors = 0
for i in range(dim_i):
for j in range(dim_j):
# address "i"th word in range
addr = baseC + (
(i * dim_j + j) << log2_int(self.wordsize // 8))
# compare to expected
if self.tbmem.read_mem(addr) != expectedC[i][j]:
num_errors += 1
# print a few errors but not too many
if num_errors <= 10:
print(
hex(addr) + ": " +
str(self.tbmem.read_mem(addr)) +
" (expected " + str(expectedC[i][j]) + ")")
if num_errors > 10:
print(str(num_errors) + " errors total.")
yield
def gen_simulation(self, selfp):
while not self.reader.done:
yield
yield from riffa.channel_write(selfp.simulator, self.tbmem.cmd_tx,
[0xF1005])
while not self.tbmem.flushack:
yield
addr = self.data_to_send[0]
num_errors = 0
for i in range(self.data_to_send[1]):
if self.tbmem.read_mem(addr) != self.results[i]:
num_errors += 1
if num_errors <= 10:
print(
hex(addr) + ": " + str(self.tbmem.read_mem(addr)) +
" (should be " + str(self.results[i]) + ")")
addr += 4
if num_errors > 10:
print("And " + str(num_errors - 10) + " more.")
i = self.data_to_send[1] - 2
addr = self.data_to_send[0] + (i << 2)
print(hex(addr) + ": " + str(self.tbmem.read_mem(addr)))
print(self.results[i])
i = self.data_to_send[1] - 1
addr = self.data_to_send[0] + (i << 2)
print(hex(addr) + ": " + str(self.tbmem.read_mem(addr)))
print(self.results[i])
yield 10
def gen_simulation(self, selfp):
# memory area to work on
baseaddr = 0x222000 ## TODO
size = 64 ## TODO
# function argument to send (as list of 32 bit words)
arg_struct = []
arg_struct.extend(riffa.unpack(baseaddr, 2))
arg_struct.extend(riffa.unpack(size, 2))
# expected return value (as list of 32 bit words)
expected_ret = [size] ## TODO
# expected memory modifications (in memory words of size 'wordsize')
expected_results = [i for i in range(size)] ## TODO
# send arguments to DUT
yield from riffa.channel_write(selfp.simulator, self.rx, arg_struct)
# wait for return value
ret = yield from riffa.channel_read(selfp.simulator, self.tx)
# check return value
if ret != expected_ret:
## TODO
print("Wrong return value! Expected " + str(expected_ret) +
", received " + str(ret))
yield from self.tbmem.send_flush_command(selfp)
# check memory modifications
num_errors = 0
for i in range(size):
# address "i"th word in range
addr = baseaddr + (i << log2_int(self.wordsize // 8))
# compare to expected
# print(hex(addr) + ": " + str(self.tbmem.read_mem(addr)))
if self.tbmem.read_mem(addr) != expected_results[i]:
num_errors += 1
# print a few errors but not too many
if num_errors <= 10:
print(
hex(addr) + ": " + str(self.tbmem.read_mem(addr)) +
" (expected " + str(expected_results[i]) + ")")
if num_errors > 10:
print(str(num_errors) + " errors total.")
if num_errors == 0:
print("Test passed.")
def gen_simulation(self, selfp):
# memory area to work on
baseaddr = 0x222000 ## TODO
size = 64 ## TODO
# function argument to send (as list of 32 bit words)
arg_struct = []
arg_struct.extend(riffa.unpack(baseaddr, 2))
arg_struct.extend(riffa.unpack(size, 2))
# expected return value (as list of 32 bit words)
expected_ret = [size] ## TODO
# expected memory modifications (in memory words of size 'wordsize')
expected_results = [i for i in range(size)] ## TODO
# send arguments to DUT
yield from riffa.channel_write(selfp.simulator, self.rx, arg_struct)
# wait for return value
ret = yield from riffa.channel_read(selfp.simulator, self.tx)
# check return value
if ret != expected_ret:
## TODO
print("Wrong return value! Expected " + str(expected_ret) + ", received " + str(ret))
yield from self.tbmem.send_flush_command(selfp)
# check memory modifications
num_errors = 0
for i in range(size):
# address "i"th word in range
addr = baseaddr + (i << log2_int(self.wordsize//8))
# compare to expected
# print(hex(addr) + ": " + str(self.tbmem.read_mem(addr)))
if self.tbmem.read_mem(addr) != expected_results[i]:
num_errors += 1
# print a few errors but not too many
if num_errors <= 10:
print(hex(addr) + ": " + str(self.tbmem.read_mem(addr)) + " (expected " + str(expected_results[i]) + ")")
if num_errors > 10:
print(str(num_errors) + " errors total.")
if num_errors == 0:
print("Test passed.")
def send_invalidate_command(self, selfp):
yield from riffa.channel_write(selfp.simulator, self.cmd_tx, [0xC105E])
def gen_simulation(self, selfp): addrs = [] for i in self.data_to_send: addrs.extend(riffa.unpack(i, 2)) yield from riffa.channel_write(selfp.simulator, self.channel, addrs)
def gen_simulation(self, selfp): yield from riffa.channel_write(selfp.simulator, self.channel, [i+1337 for i in range(17)]) yield yield yield
def gen_simulation(self, selfp):
ret = []
while True:
if selfp.cmd_rx.start:
# print("Receiving command...")
cmd = yield from riffa.channel_read(selfp.simulator,
self.cmd_rx)
addr = (cmd[1] << 32) | cmd[0] if self.ptrsize > 32 else cmd[0]
pg_addr = (addr >> log2_int(self.pagesize)) << log2_int(
self.pagesize)
assert (addr == pg_addr)
if cmd[2] == 0x6e706e70:
print("Fetching page " + hex(addr))
data = []
if self.wordsize < 32:
mask = 1
for i in range(self.wordsize):
mask = mask | (1 << i)
for i in range(pg_addr, pg_addr + self.pagesize, 4):
d = 0
for j in range(0, 32 // self.wordsize):
d = d | ((self.read_mem(i + j *
(self.wordsize // 8))
& mask) << j * self.wordsize)
data.append(d)
else:
for i in range(pg_addr, pg_addr + self.pagesize,
(self.wordsize // 8)):
data.extend(
riffa.unpack(self.read_mem(i),
self.wordsize // 32))
if len(data) != self.pagesize // 4:
print("Wrong page length: " + str(len(data)))
yield from riffa.channel_write(selfp.simulator,
self.data_tx, data)
# print("Finished fetching page.")
if cmd[2] == 0x61B061B0:
print("Writeback page " + hex(addr))
# print(ret)
if len(ret) < self.pagesize // 4:
print("Incomplete writeback: received only " +
str(len(ret)) + " words")
if self.wordsize >= 32:
words = [
riffa.pack(x) for x in zip(*[
ret[i::self.wordsize // 32]
for i in range(self.wordsize // 32)
])
]
else:
words = []
mask = 1
for i in range(self.wordsize):
mask = mask | (1 << i)
for i in range(len(ret)):
for j in range(32 // self.wordsize):
words.append((ret[i] >> j * self.wordsize)
& mask)
print("Modified:")
num_modified = 0
for i in range(len(words)):
if words[i] != self.read_mem(addr + i *
(self.wordsize // 8)):
num_modified += 1
self.modified[addr + i *
(self.wordsize // 8)] = words[i]
if num_modified < 10:
print(
hex(addr + i * (self.wordsize // 8)) +
": " + hex(words[i]))
if num_modified >= 10:
print("and more... " + str(num_modified) + " total.")
ret = []
# print("Finished writing back page.")
if cmd[2] == 0xD1DF1005:
self.flushack = 1
print("Cache finished flushing.")
elif selfp.data_rx.start:
# print("Receiving data...")
ret = yield from riffa.channel_read(selfp.simulator,
self.data_rx)
# print("Finished receiving data.")
else:
# print("Nothing")
yield
def gen_simulation(self, selfp):
generate_data = generate_data_fn(self.wordsize)
for addr, we in self.generate_random_transactions(24):
selfp.dut.virtmem.virt_addr = addr
selfp.dut.virtmem.num_words = 1
selfp.dut.virtmem.req = 1
selfp.dut.virtmem.write_enable = we
if we:
selfp.dut.virtmem.data_write = generate_data(addr) + 1
yield
selfp.dut.virtmem.req = 0
while not selfp.dut.virtmem.done:
yield
if we:
print("Wrote data " + hex(generate_data(addr) + 1) +
" to address " + hex(addr))
else:
print("Read data " + hex(selfp.dut.virtmem.data_read) +
" from address " + hex(addr))
selfp.dut.virtmem.virt_addr = 0
selfp.dut.virtmem.req = 0
selfp.dut.virtmem.data_write = 0
selfp.dut.virtmem.write_enable = 0
yield
num_words = 8
addr = 0x456FF0
selfp.dut.virtmem.virt_addr = addr
selfp.dut.virtmem.num_words = num_words
selfp.dut.virtmem.req = 1
print("Requesting read burst of " + str(num_words) +
" words starting from address " + hex(addr))
internal_address = addr
words_recvd = 0
while words_recvd < num_words:
yield
if selfp.dut.virtmem.data_valid:
words_recvd += 1
print("Read " + hex(selfp.dut.virtmem.data_read) +
" from address " + hex(internal_address))
internal_address = selfp.dut.virtmem.virt_addr_internal
selfp.dut.virtmem.virt_addr = 0
selfp.dut.virtmem.req = 0
selfp.dut.virtmem.data_write = 0
selfp.dut.virtmem.write_enable = 0
yield
num_words = 8
addr = 0x456FF0
selfp.dut.virtmem.virt_addr = addr
selfp.dut.virtmem.num_words = num_words
selfp.dut.virtmem.req = 1
selfp.dut.virtmem.write_enable = 1
selfp.dut.virtmem.data_write = 0xBAE
print("Requesting write burst of " + str(num_words) +
" words starting from address " + hex(addr))
internal_address = addr
words_sent = 0
while words_sent < num_words:
selfp.dut.virtmem.data_write = words_sent
yield
if selfp.dut.virtmem.write_ack:
words_sent += 1
internal_address = selfp.dut.virtmem.virt_addr_internal
print("Wrote " + hex(selfp.dut.virtmem.data_write) +
" to address " + hex(internal_address))
selfp.dut.virtmem.virt_addr = 0
selfp.dut.virtmem.req = 0
selfp.dut.virtmem.data_write = 0
selfp.dut.virtmem.write_enable = 0
# selfp.dut.virtmem.flush_all = 1
# yield 2
# while not selfp.dut.virtmem.done:
# yield
yield from riffa.channel_write(selfp.simulator, self.tbmem.cmd_tx,
[0xF1005])
while not self.tbmem.flushack:
yield
yield 20
print("Simulation took " + str(selfp.simulator.cycle_counter) +
" cycles.")
def send_flush_command(self, selfp):
self.flushack = 0
yield from riffa.channel_write(selfp.simulator, self.cmd_tx, [0xF1005])
while self.flushack == 0:
yield
self.flushack = 0
def gen_simulation(self, selfp):
addrs = []
for i in self.data_to_send:
addrs.extend(riffa.unpack(i, 2))
yield from riffa.channel_write(selfp.simulator, self.channel, addrs)
def gen_simulation(self, selfp):
ret = []
while True:
if selfp.cmd_rx.start :
# print("Receiving command...")
cmd = yield from riffa.channel_read(selfp.simulator, self.cmd_rx)
addr = (cmd[1] << 32) | cmd[0] if self.ptrsize > 32 else cmd[0]
pg_addr = (addr >> log2_int(self.pagesize)) << log2_int(self.pagesize)
assert(addr == pg_addr)
if cmd[2] == 0x6e706e70:
print("Fetching page " + hex(addr))
data = []
if self.wordsize < 32:
mask = 1
for i in range(self.wordsize):
mask = mask | (1 << i)
for i in range(pg_addr, pg_addr+self.pagesize, 4):
d = 0
for j in range(0,32//self.wordsize):
d = d | ((self.read_mem(i+ j*(self.wordsize//8)) & mask) << j*self.wordsize)
data.append(d)
else:
for i in range(pg_addr, pg_addr+self.pagesize, (self.wordsize//8)):
data.extend(riffa.unpack(self.read_mem(i), self.wordsize//32))
if len(data) != self.pagesize//4:
print("Wrong page length: " + str(len(data)))
yield from riffa.channel_write(selfp.simulator, self.data_tx, data)
# print("Finished fetching page.")
if cmd[2] == 0x61B061B0:
print("Writeback page " + hex(addr))
# print(ret)
if len(ret) < self.pagesize//4:
print("Incomplete writeback: received only " + str(len(ret)) + " words")
if self.wordsize >= 32:
words = [riffa.pack(x) for x in zip(*[ret[i::self.wordsize//32] for i in range(self.wordsize//32)])]
else:
words = []
mask = 1
for i in range(self.wordsize):
mask = mask | (1 << i)
for i in range(len(ret)):
for j in range(32//self.wordsize):
words.append((ret[i] >> j*self.wordsize) & mask)
print("Modified:")
num_modified = 0
for i in range(len(words)):
if words[i] != self.read_mem(addr+i*(self.wordsize//8)):
num_modified += 1
self.modified[addr+i*(self.wordsize//8)] = words[i]
if num_modified < 10:
print(hex(addr+i*(self.wordsize//8)) + ": " + hex(words[i]))
if num_modified >= 10:
print("and more... " + str(num_modified) + " total.")
ret = []
# print("Finished writing back page.")
if cmd[2] == 0xD1DF1005:
self.flushack = 1
print("Cache finished flushing.")
elif selfp.data_rx.start:
# print("Receiving data...")
ret = yield from riffa.channel_read(selfp.simulator, self.data_rx)
# print("Finished receiving data.")
else:
# print("Nothing")
yield
def gen_simulation(self, selfp):
generate_data = generate_data_fn(self.wordsize)
for addr, we in self.generate_random_transactions(24):
selfp.dut.virtmem.virt_addr = addr
selfp.dut.virtmem.num_words = 1
selfp.dut.virtmem.req = 1
selfp.dut.virtmem.write_enable = we
if we:
selfp.dut.virtmem.data_write = generate_data(addr) + 1
yield
selfp.dut.virtmem.req = 0
while not selfp.dut.virtmem.done:
yield
if we:
print("Wrote data " + hex(generate_data(addr) + 1) + " to address " + hex(addr))
else:
print("Read data " + hex(selfp.dut.virtmem.data_read) + " from address " + hex(addr))
selfp.dut.virtmem.virt_addr = 0
selfp.dut.virtmem.req = 0
selfp.dut.virtmem.data_write = 0
selfp.dut.virtmem.write_enable = 0
yield
num_words = 8
addr = 0x456FF0
selfp.dut.virtmem.virt_addr = addr
selfp.dut.virtmem.num_words = num_words
selfp.dut.virtmem.req = 1
print("Requesting read burst of " + str(num_words) + " words starting from address " + hex(addr))
internal_address = addr
words_recvd = 0
while words_recvd < num_words:
yield
if selfp.dut.virtmem.data_valid:
words_recvd += 1
print("Read " + hex(selfp.dut.virtmem.data_read) + " from address " + hex(internal_address))
internal_address = selfp.dut.virtmem.virt_addr_internal
selfp.dut.virtmem.virt_addr = 0
selfp.dut.virtmem.req = 0
selfp.dut.virtmem.data_write = 0
selfp.dut.virtmem.write_enable = 0
yield
num_words = 8
addr = 0x456FF0
selfp.dut.virtmem.virt_addr = addr
selfp.dut.virtmem.num_words = num_words
selfp.dut.virtmem.req = 1
selfp.dut.virtmem.write_enable = 1
selfp.dut.virtmem.data_write = 0xBAE
print("Requesting write burst of " + str(num_words) + " words starting from address " + hex(addr))
internal_address = addr
words_sent = 0
while words_sent < num_words:
selfp.dut.virtmem.data_write = words_sent
yield
if selfp.dut.virtmem.write_ack:
words_sent += 1
internal_address = selfp.dut.virtmem.virt_addr_internal
print("Wrote " + hex(selfp.dut.virtmem.data_write) + " to address " + hex(internal_address))
selfp.dut.virtmem.virt_addr = 0
selfp.dut.virtmem.req = 0
selfp.dut.virtmem.data_write = 0
selfp.dut.virtmem.write_enable = 0
# selfp.dut.virtmem.flush_all = 1
# yield 2
# while not selfp.dut.virtmem.done:
# yield
yield from riffa.channel_write(selfp.simulator, self.tbmem.cmd_tx, [0xF1005])
while not self.tbmem.flushack:
yield
yield 20
print("Simulation took " + str(selfp.simulator.cycle_counter) + " cycles.")
def send_invalidate_command(self, selfp): yield from riffa.channel_write(selfp.simulator, self.cmd_tx, [0xC105E])
def send_flush_command(self, selfp): self.flushack = 0 yield from riffa.channel_write(selfp.simulator, self.cmd_tx, [0xF1005]) while self.flushack == 0: yield self.flushack = 0