def read(self, first_address, count): data = [first_address, count] data.append(crc7(data)) with self.mutex: retcount = self.port.write(data) if retcount != len(data): raise IOError("Write error (%s != %s)" % (retcount, len(data))) # FIXME if not hal.isSimulation(): Timer.delay(0.001) data = self.port.read(True, count + 1) if len(data) != count + 1: raise IOError("Read error (%s != %s)" % (len(data), count+1)) crc = data[-1] data = data[:-1] if crc7(data) != crc: raise IOError("CRC error") return data
def write(self, address, value): data = [address | 0x80, value] data.append(crc7(data)) if self.port.write(data) != len(data): return False return True
def read(self, first_address, count): data = [first_address, count] data.append(crc7(data)) retcount = self.port.write(data) if retcount != len(data): raise IOError("Write error (%s != %s)" % (retcount, len(data))) Timer.delay(0.001) data = self.port.read(True, count + 1) if len(data) != count + 1: raise IOError("Read error (%s != %s)" % (len(data), count + 1)) crc = data[-1] data = data[:-1] if crc7(data) != crc: raise IOError("CRC error") return data