def update_files(self):
'''|
| Update the module design files according to changes in .json file
|________'''
mylog.head("Updating and generating design files: " + self.module_name)
self.overwrite = True
copy_custom_interfaces(self)
print_module_class_file(self)
print_btest_file(self)
print_compile_list_file(self)
if self.modules == []:
update_beh_file(self)
if self.verilog != {}:
if self.verilog["path"] == '':
# Generate a verilog file containing only the interface signals.
# Implementation to be provided by the designer.
print_verilog_file(self)
else:
# A third-party verilog module to be integrated
filename = self.verilog["path"] + '/' + self.verilog[
"name"] + '.v'
print_wrap_file(self, filename)
shutil.copyfile(
filename,
self.c_path + '/src/' + self.verilog["name"] + '.v')
else:
print_rtl_file(self)
else:
update_beh_file(self)
print_rtl_file(self)
def update_files(self):
'''|
| Update the module design files according to changes in .json file
|________'''
mylog.head("Updating and generating design files: " + self.module_name)
self.overwrite = True
copy_custom_interfaces(self)
print_module_class_file(self)
print_btest_file(self)
print_compile_list_file(self)
if self.modules == []:
update_beh_file(self)
if self.verilog != {}:
if self.verilog["path"]=='':
# Generate a verilog file containing only the interface signals.
# Implementation to be provided by the designer.
print_verilog_file(self)
else:
# A third-party verilog module to be integrated
filename = self.verilog["path"] + '/' + self.verilog["name"] + '.v'
print_wrap_file(self, filename)
shutil.copyfile(filename, self.c_path + '/src/' + self.verilog["name"] + '.v')
else:
print_rtl_file(self)
else:
update_beh_file(self)
print_rtl_file(self)
def generate(self, module_name):
'''|
| Generate the module design directory tree and files
|________'''
# Create the project directory structure
os.makedirs(self.c_path + '/' + self.src_path)
os.makedirs(self.c_path + '/' + self.out_path)
os.makedirs(self.c_path + '/' + self.test_path)
os.makedirs(self.c_path + '/' + self.test_path + '/vectors')
mylog.head("Generating design files: " + module_name)
# Generate empty _init_ files
StrBuilder().write(self.c_path + '/__init__.py', overwrite=True)
StrBuilder().write(self.c_path + '/' + self.src_path + '/__init__.py',
overwrite=True)
StrBuilder().write(self.c_path + '/' + self.test_path + '/__init__.py',
overwrite=True)
# git hack
StrBuilder().write(self.c_path + '/' + self.out_path + '/.gitignore',
overwrite=True)
StrBuilder().write(self.c_path + '/' + self.test_path +
'/vectors/.gitignore',
overwrite=True)
copy_custom_interfaces(self)
print_module_class_file(self)
print_btest_file(self)
print_utest_file(self)
print_compile_list_file(self)
if self.modules == []:
print_beh_file(self)
if self.verilog != {}:
if self.verilog["path"] == '':
# Generate a verilog file containing only the interface signals.
# Implementation to be provided by the designer.
print_verilog_file(self)
else:
# A third-party verilog module to be integrated
filename = self.verilog["path"] + '/' + self.verilog[
"name"] + '.v'
print_wrap_file(self, filename)
shutil.copyfile(
filename,
self.c_path + '/src/' + self.verilog["name"] + '.v')
else:
print_rtl_file(self)
else:
print_beh_file(self)
print_rtl_file(self)
def generate(self, module_name):
'''|
| Generate the module design directory tree and files
|________'''
# Create the project directory structure
os.makedirs(self.c_path + '/' + self.src_path)
os.makedirs(self.c_path + '/' + self.out_path)
os.makedirs(self.c_path + '/' + self.test_path)
os.makedirs(self.c_path + '/' + self.test_path + '/vectors')
mylog.head("Generating design files: " + module_name)
# Generate empty _init_ files
StrBuilder().write(self.c_path + '/__init__.py', overwrite=True)
StrBuilder().write(self.c_path + '/' + self.src_path + '/__init__.py', overwrite=True)
StrBuilder().write(self.c_path + '/' + self.test_path + '/__init__.py', overwrite=True)
# git hack
StrBuilder().write(self.c_path + '/' + self.out_path + '/.gitignore', overwrite=True)
StrBuilder().write(self.c_path + '/' + self.test_path + '/vectors/.gitignore', overwrite=True)
copy_custom_interfaces(self)
print_module_class_file(self)
print_btest_file(self)
print_utest_file(self)
print_compile_list_file(self)
if self.modules == []:
print_beh_file(self)
if self.verilog != {}:
if self.verilog["path"]=='':
# Generate a verilog file containing only the interface signals.
# Implementation to be provided by the designer.
print_verilog_file(self)
else:
# A third-party verilog module to be integrated
filename = self.verilog["path"] + '/' + self.verilog["name"] + '.v'
print_wrap_file(self, filename)
shutil.copyfile(filename, self.c_path + '/src/' + self.verilog["name"] + '.v')
else:
print_rtl_file(self)
else:
print_beh_file(self)
print_rtl_file(self)
