def __init__(self) -> None:
_, reg_block = load_registers()
self.regs = {} # type: Dict[str, RGReg]
self._dirty = 0
assert isinstance(reg_block, RegBlock)
for entry in reg_block.flat_regs:
assert isinstance(entry.name, str)
# reggen's validation should have checked that we have no
# duplicates.
assert entry.name not in self.regs
double_flopped = entry.name in self.double_flopped_regs
self.regs[entry.name] = RGReg.from_register(entry, double_flopped)
# Add a fake "STOP_PC" register.
#
# TODO: We might well add something like this to the actual design in
# the future (see issue #4327) but, for now, it's just used in
# simulation to help track whether RIG-generated binaries finished
# where they expected to finish.
self.regs['STOP_PC'] = make_flag_reg('STOP_PC', True)
# Add a fake "RND_REQ" register to pass it through otbn_core_model
# when OTBN_USE_MODEL parameter is enabled in system level tests.
self.regs['RND_REQ'] = make_flag_reg('RND_REQ', True)
# Add a fake "WIPE_START" register. We set this for a single cycle when
# starting secure wipe and the C++ model can use this to trigger a dump
# of internal state before it gets zeroed out.
self.regs['WIPE_START'] = make_flag_reg('WIPE_START', False)
def __init__(self) -> None:
_, reg_block = load_registers()
self.regs = {} # type: Dict[str, RGReg]
self.trace = [] # type: List[TraceExtRegChange]
assert isinstance(reg_block, RegBlock)
for entry in reg_block.flat_regs:
assert isinstance(entry.name, str)
# reggen's validation should have checked that we have no
# duplicates.
assert entry.name not in self.regs
self.regs[entry.name] = RGReg(entry)
def __init__(self) -> None:
_, reg_list = load_registers()
self.regs = {} # type: Dict[str, RGReg]
self.trace = [] # type: List[TraceExtRegChange]
# We're interested in the proper registers, and don't care about
# anything else.
for entry in reg_list:
if not isinstance(entry, Register):
continue
assert isinstance(entry.name, str)
# reggen's validation should have checked that we have no
# duplicates.
assert entry.name not in self.regs
self.regs[entry.name] = RGReg(entry)
def __init__(self) -> None:
_, reg_list = load_registers()
self.regs = {} # type: Dict[str, RGReg]
self.trace = [] # type: List[TraceExtRegChange]
# We're interested in the proper registers, and don't care about
# address tracking. So we can just ignore anything without a 'name'
# attribute.
for entry in reg_list:
name = entry.get('name')
if name is None:
continue
assert isinstance(name, str)
# reggen's validation should have checked that we have no
# duplicates.
assert name not in self.regs
self.regs[name] = RGReg(entry)
def __init__(self) -> None:
_, reg_block = load_registers()
self.regs = {} # type: Dict[str, RGReg]
self.trace = [] # type: List[TraceExtRegChange]
assert isinstance(reg_block, RegBlock)
for entry in reg_block.flat_regs:
assert isinstance(entry.name, str)
# reggen's validation should have checked that we have no
# duplicates.
assert entry.name not in self.regs
self.regs[entry.name] = RGReg.from_register(entry)
# Add a fake "STOP_PC" register.
#
# TODO: We might well add something like this to the actual design in
# the future (see issue #4327) but, for now, it's just used in
# simulation to help track whether RIG-generated binaries finished
# where they expected to finish.
self.regs['STOP_PC'] = RGReg([RGField('STOP_PC', 32, 0, 0, 'ro')])