Python fregstim Examples

Example #1

File: simReg.py Project: bojankumari/vetri

def regWrite(reg, value):
    f = simLib.fregstim()
    f.write("# WRITE\n")
    f.write("W " + "%08x\n" % CMD_WRITE)
    f.write("%08x, " % reg)  # // Address
    f.write("%08x, " % value)  # // Data
    f.write("f, -.\n")

Example #2

File: simReg.py Project: boffinnm/test

def regWrite(reg, value):
    f = simLib.fregstim()
    f.write("# WRITE\n")
    f.write("W " + "%08x\n"%CMD_WRITE)
    f.write("%08x, "%reg) # // Address
    f.write("%08x, "%value) # // Data 
    f.write("f, -.\n")

Example #3

File: simReg.py Project: mtpsa/P4-NetFPGA-MTPSA

def regDelay(nanoSeconds):
    simLib.fregstim().write("# DELAY \n")
    simLib.fregstim().write("D " + "%0d\n" % nanoSeconds)
    simLib.fregstim().write("# DELAY (MSB) " + "%08x, " %
                            (MSB_MASK & nanoSeconds) + str(nanoSeconds) +
                            " ns\n")
    simLib.fregstim().write("# DELAY (LSB) " + "%08x, " %
                            (LSB_MASK & nanoSeconds) + str(nanoSeconds) +
                            " ns\n")

Example #4

File: simReg.py Project: mtpsa/P4-NetFPGA-MTPSA

def regreadstim(reg):
    f = simLib.fregstim()
    simLib.fregstim().write("# READ\n")
    f.write("R " + "%08x\n" % CMD_READ)  # // READ
    f.write("-, -, -, " + "%08x" % reg + ".\n")

Example #5

File: simReg.py Project: sutianyu/NetFPGA-SUME-alpha

def regreadstim(reg):
    f = simLib.fregstim()
    simLib.fregstim().write("# READ\n")
    f.write("R " + "%08x\n"%CMD_READ) # // READ
    f.write("-, -, -, " + "%08x"%reg + ".\n")

Example #6

File: simReg.py Project: sutianyu/NetFPGA-SUME-alpha

def regDelay(nanoSeconds):
    simLib.fregstim().write("# DELAY \n")
    simLib.fregstim().write("D " + "%0d\n"%nanoSeconds)
    simLib.fregstim().write("# DELAY (MSB) " + "%08x, "%(MSB_MASK & nanoSeconds) + str(nanoSeconds) + " ns\n")
    simLib.fregstim().write("# DELAY (LSB) " + "%08x, "%(LSB_MASK & nanoSeconds) + str(nanoSeconds) + " ns\n")

Example #7

def barrier():
    for i in range(NUM_PORTS):  # 0,1,2,3
        simLib.fPort(i + 1).write("# BARRIER\n")
        simLib.fPort(i + 1).write("B " + "%d\n" % CMD_BARRIER)
        simLib.fPort(i + 1).write("# EXPECTED\n")
        simLib.fPort(i + 1).write("N " + "%d\n" % (numExpectedPktsPHY[i]))
        simLib.fPort(i + 1).write("# SENT\n")
        simLib.fPort(i + 1).write("S " + "%d\n\n" % (numSendPktsPHY[i]))
    simLib.fDMA().write("# BARRIER\n")
    simLib.fDMA().write("B " + "%d\n" % CMD_BARRIER)
    simLib.fDMA().write("# EXPECTED\n")
    simLib.fDMA().write("N " + "%d\n" % (numExpectedPktsDMA[0]))
    simLib.fDMA().write("# SENT\n")
    simLib.fDMA().write("S " + "%d\n\n" % (numSendPktsDMA[0]))
    simLib.fregstim().write("# BARRIER\n")
    simLib.fregstim().write("B " + "%d\n" % CMD_BARRIER_REG)
    for i in range(NUM_PORTS):
        simLib.fregstim().write("# Interface " + "%d\n" % (i))
        simLib.fregstim().write("N " + "%d\n" % (numExpectedPktsPHY[i]))
        simLib.fregstim().write("S " + "%d\n" % (numSendPktsPHY[i]))
    simLib.fregstim().write("# DMA\n")
    simLib.fregstim().write("N " + "%d\n" % (numExpectedPktsDMA[i]))
    simLib.fregstim().write("S " + "%d\n" % (numSendPktsDMA[i]))

    resetBarrier()

Example #8

File: simPkt.py Project: CharlieBashford/P33

def barrier():
    for i in range(NUM_PORTS): # 0,1,2,3
	simLib.fPort(i + 1).write("# BARRIER\n")
	simLib.fPort(i + 1).write("B " + "%d\n"%CMD_BARRIER)   
	simLib.fPort(i + 1).write("# EXPECTED\n") 
	simLib.fPort(i + 1).write("N " + "%d\n"%(numExpectedPktsPHY[i]))
	simLib.fPort(i + 1).write("# SENT\n") 
	simLib.fPort(i + 1).write("S " + "%d\n\n"%(numSendPktsPHY[i]))
    simLib.fDMA().write("# BARRIER\n")
    simLib.fDMA().write("B " + "%d\n"%CMD_BARRIER)   
    simLib.fDMA().write("# EXPECTED\n") 
    simLib.fDMA().write("N " + "%d\n"%(numExpectedPktsDMA[0]))
    simLib.fDMA().write("# SENT\n") 
    simLib.fDMA().write("S " + "%d\n\n"%(numSendPktsDMA[0]))
    simLib.fregstim().write("# BARRIER\n")
    simLib.fregstim().write("B " + "%d\n"%CMD_BARRIER_REG)
    for i in range(NUM_PORTS):
	#if numSendPktsPHY[i] == 0:
	#    simLib.fregstim().write("")
	#else: 
	#if numExpectedPktsPHY[i] == numSendPktsPHY[i]:
	#    simLib.fregstim().write("N " + "%d\n"%(numSendPktsPHY[i]))
	#    simLib.fregstim().write("N " + "%d\n"%(numExpectedPktsPHY[i]))
	#else:
	simLib.fregstim().write("# Interface " + "%d\n"%(i)) 
	#simLib.fregstim().write("S " + "%d\n"%(numSendPktsPHY[i]))
        simLib.fregstim().write("N " + "%d\n"%(numExpectedPktsPHY[i]))
	simLib.fregstim().write("S " + "%d\n"%(numSendPktsPHY[i]))
    #if numSendPktsDMA[i] == 0:
#	simLib.fregstim().write("")
#    else:
    simLib.fregstim().write("# DMA\n")
    #simLib.fregstim().write("S " + "%d\n"%(numSendPktsDMA[i]))
    simLib.fregstim().write("N " + "%d\n"%(numExpectedPktsDMA[i])) 
    simLib.fregstim().write("S " + "%d\n"%(numSendPktsDMA[i]))
    #simLib.fregexpect().write("# BARRIER\n")
    #simLib.fregexpect().write("B " + "%d\n"%CMD_BARRIER_REG)
       
    resetBarrier()