def __init__(self, platform, spiboot=False, **kwargs):
if ICE40:
SoCCore.mem_map = {
} # clear the default map provided by the simulation
SoCCore.mem_map["rom"] = 0x0
SoCCore.mem_map["sram"] = 0x01000000
SoCCore.mem_map["com"] = 0xd0000000 # when simulating ICE40
SoCCore.mem_map["csr"] = 0xe0000000
else:
SoCCore.mem_map["wifi"] = 0xe0010000 # when simulating 7-series
Sim.__init__(self,
platform,
custom_clocks=local_clocks,
spiboot=spiboot,
vex_verilog_path=VEX_CPU_PATH,
**kwargs) # SoC magic is in here
# FIXME: the SpiFifoPeripheral core inside spi_ice40 is *not* the code used in the EC
# FIXME: the EC currently keeps it in an "rtl" directory. This should be fixed to point to "gateware"
# SPI interface
self.submodules.spicontroller = ClockDomainsRenamer({"sys": "spi"})(
spi_7series.SPIController(platform.request("com")))
self.add_csr("spicontroller")
self.submodules.com = ClockDomainsRenamer({"spi_peripheral": "spi"})(
spi_ice40.SpiFifoPeripheral(platform.request("peripheral")))
self.add_wb_slave(self.mem_map["com"], self.com.bus, 4)
self.add_memory_region("com", self.mem_map["com"], 4, type='io')
self.add_csr("com")
self.add_interrupt("com")
def __init__(self, platform, spiboot=False, **kwargs):
Sim.__init__(self,
platform,
custom_clocks=local_clocks,
spiboot=spiboot,
**kwargs) # SoC magic is in here
# LCD interface
self.submodules.memlcd = memlcd.MemLCD(platform.request("lcd"))
self.add_csr("memlcd")
self.register_mem("memlcd",
self.mem_map["memlcd"],
self.memlcd.bus,
size=self.memlcd.fb_depth * 4)
# external SRAM for testing the build system
self.submodules.sram_ext = sram_32.SRAM32(platform.request("sram"),
rd_timing=7,
wr_timing=6,
page_rd_timing=2)
self.add_csr("sram_ext")
self.register_mem("sram_ext",
self.mem_map["sram_ext"],
self.sram_ext.bus,
size=0x1000000)
def __init__(self, platform, spiboot=False, **kwargs):
Sim.__init__(self,
platform,
custom_clocks=local_clocks,
spiboot=spiboot,
**kwargs) # SoC magic is in here
# add a key for the i2s_duplex sim block
SoCCore.mem_map["i2s_duplex"] = 0xe0001000
# shallow fifodepth allows us to work the end points a bit faster in simulation
self.submodules.i2s_duplex = S7I2S(platform.request("i2s", 0),
fifo_depth=8)
self.bus.add_slave(
"i2s_duplex", self.i2s_duplex.bus,
SoCRegion(origin=self.mem_map["i2s_duplex"],
size=0x4,
cached=False))
self.add_csr("i2s_duplex")
self.add_interrupt("i2s_duplex")
self.submodules.audio = S7I2S(platform.request("i2s", 1), fifo_depth=8)
self.bus.add_slave(
"audio", self.audio.bus,
SoCRegion(origin=self.mem_map["audio"], size=0x4, cached=False))
self.add_csr("audio")
self.add_interrupt("audio")
def __init__(self, platform, spiboot=False, **kwargs):
Sim.__init__(self, platform, custom_clocks=local_clocks, spiboot=spiboot, **kwargs) # SoC magic is in here
# SHA block --------------------------------------------------------------------------------
self.submodules.sha2 = sha2.Hmac(platform)
self.add_csr("sha2")
self.add_interrupt("sha2")
self.bus.add_slave("sha2", self.sha2.bus, SoCRegion(origin=self.mem_map["sha2"], size=0x4, cached=False))
def __init__(self, platform, spiboot=False, **kwargs):
Sim.__init__(self, platform, custom_clocks=local_clocks, spiboot=spiboot, **kwargs) # SoC magic is in here
# external SRAM
self.submodules.sram_ext = sram_32.SRAM32(platform.request("sram"), rd_timing=7, wr_timing=6, page_rd_timing=6)
self.add_csr("sram_ext")
self.register_mem("sram_ext", self.mem_map["sram_ext"],
self.sram_ext.bus, size=0x1000000)
def __init__(self, platform, spiboot=False, **kwargs):
Sim.__init__(self,
platform,
custom_clocks=local_clocks,
spiboot=spiboot,
**kwargs) # SoC magic is in here
platform.toolchain.attr_translate["KEEP"] = ("KEEP", "TRUE")
platform.toolchain.attr_translate["DONT_TOUCH"] = ("DONT_TOUCH",
"TRUE")
from litex.soc.cores.xadc import analog_layout
analog_pads = Record(analog_layout)
analog = platform.request("analog")
# DVT is solidly an xc7s50-only build
dummy4 = Signal(4, reset=0)
dummy5 = Signal(5, reset=0)
dummy1 = Signal(1, reset=0)
self.comb += analog_pads.vauxp.eq(
Cat(
dummy4, # 0,1,2,3
analog.noise1, # 4
dummy1, # 5
analog.vbus_div, # 6
dummy5, # 7,8,9,10,11
analog.noise0, # 12
dummy1, # 13
analog.usbdet_p, # 14
analog.usbdet_n, # 15
)),
self.comb += analog_pads.vauxn.eq(
Cat(
dummy4, # 0,1,2,3
analog.noise1_n, # 4
dummy1, # 5
analog.vbus_div_n, # 6
dummy5, # 7,8,9,10,11
analog.noise0_n, # 12
dummy1, # 13
analog.usbdet_p_n, # 14
analog.usbdet_n_n, # 15
)),
from gateware.trng.trng_managed import TrngManaged, TrngManagedKernel, TrngManagedServer
self.submodules.trng_kernel = TrngManagedKernel()
self.add_csr("trng_kernel")
self.add_interrupt("trng_kernel")
self.submodules.trng_server = TrngManagedServer()
self.add_csr("trng_server")
self.add_interrupt("trng_server")
self.submodules.trng = TrngManaged(platform,
analog_pads,
platform.request("noise"),
server=self.trng_server,
kernel=self.trng_kernel,
sim=True)
self.add_csr("trng")
def __init__(self, platform, spiboot=False, **kwargs):
Sim.__init__(self,
platform,
custom_clocks=local_clocks,
spiboot=spiboot,
**kwargs) # SoC magic is in here
self.submodules.keyrom = KeyRom(platform)
self.add_csr("keyrom")
def __init__(self, platform, spiboot=False, **kwargs):
Sim.__init__(self,
platform,
custom_clocks=local_clocks,
spiboot=spiboot,
**kwargs) # SoC magic is in here
# Add something to simulate: Demo module for the template
self.submodules.aes = aes_opentitan.Aes(platform)
self.add_csr("aes")
def __init__(self, platform, spiboot=False, **kwargs):
Sim.__init__(self,
platform,
custom_clocks=local_clocks,
spiboot=spiboot,
**kwargs) # SoC magic is in here
# Add something to simulate: Demo module for the template
self.submodules.demo = Demo(platform.request("template"))
self.add_csr("demo")
def __init__(self, platform, spiboot=False, **kwargs):
Sim.__init__(self, platform, custom_clocks=local_clocks, spiboot=spiboot, **kwargs) # SoC magic is in here
# Keyboard module
self.submodules.keyboard = ClockDomainsRenamer(cd_remapping={"kbd":"lpclk"})(keyboard.KeyScan(platform.request("kbd")))
self.add_csr("keyboard")
self.add_interrupt("keyboard")
self.clock_domains.cd_lpclk = ClockDomain()
self.comb += self.cd_lpclk.clk.eq(platform.request("lpclk"))
def __init__(self, platform, spiboot=False, **kwargs):
Sim.__init__(self,
platform,
custom_clocks=local_clocks,
spiboot=spiboot,
**kwargs) # SoC magic is in here
# SPI interface
self.submodules.spicontroller = spi_7series.SPIController(
platform.request("com")
) # replace with spi_ice40 to simulate the ice40 controller
self.add_csr("spicontroller")
self.submodules.spiperipheral = spi_7series.SPIPeripheral(
platform.request("peripheral"))
self.add_csr("spiperipheral")
def __init__(self, platform, spiboot=False, **kwargs):
Sim.__init__(self,
platform,
custom_clocks=local_clocks,
spiboot=spiboot,
**kwargs) # SoC magic is in here
from gateware.wdt import WDT
self.submodules.wdt = WDT(platform)
self.add_csr("wdt")
# emulate the patches to the STARTUPE2 blocks...
self.comb += [
platform.request("wdt").wdt_reset.eq(self.wdt.gsr),
self.wdt.cfgmclk.eq(ClockSignal("cfgmclk")),
]
def __init__(self, platform, spiboot=False, **kwargs):
Sim.__init__(self,
platform,
custom_clocks=local_clocks,
spiboot=spiboot,
bus_timeout=200,
**kwargs) # SoC magic is in here
# Add an IDELAYCTRL primitive for the SpiOpi block
reset_counter = Signal(5, reset=31) # 155ns @ 200MHz, min 59.28ns
ic_reset = Signal(reset=1)
self.sync.idelay_ref += \
If(reset_counter != 0,
reset_counter.eq(reset_counter - 1)
).Else(
ic_reset.eq(0)
)
self.delay_rdy = Signal()
self.specials += Instance("IDELAYCTRL",
i_REFCLK=ClockSignal("idelay_ref"),
i_RST=ic_reset,
o_RDY=self.delay_rdy)
self.ready = CSRStatus()
self.comb += self.ready.status.eq(self.delay_rdy)
# spi control -- that's the point of this simulation!
SPI_FLASH_SIZE = 128 * 1024 * 1024
sclk_instance_name = "SCLK_ODDR"
iddr_instance_name = "SPI_IDDR"
cipo_instance_name = "cipo_FDRE"
self.submodules.spinor = S7SPIOPI(platform.request("spiflash_8x"),
sclk_name=sclk_instance_name,
iddr_name=iddr_instance_name,
cipo_name=cipo_instance_name,
sim=True)
platform.add_source(
"../../gateware/spimemio.v"
) ### NOTE: this actually doesn't help for SIM, but it reminds us to scroll to the bottom of this file and add it to the xvlog imports
self.register_mem("spiflash",
self.mem_map["spiflash"],
self.spinor.bus,
size=SPI_FLASH_SIZE)
self.add_csr("spinor")
def __init__(self, platform, spiboot=False, **kwargs):
Sim.__init__(self,
platform,
custom_clocks=local_clocks,
spiboot=spiboot,
**kwargs) # SoC magic is in here
bios_size = 0x8000
rom_bus = wishbone.Interface(data_width=self.bus.data_width)
rom = BlockRom(bus=rom_bus, init='boot.bin')
self.bus.add_slave(
"brom", rom.bus,
SoCRegion(origin=0x80000000,
size=bios_size,
mode="r",
cached=False))
self.check_if_exists("brom")
self.logger.info("Block ROM {} {} {}.".format(
"brom", "added", self.bus.regions["brom"]))
setattr(self.submodules, "brom", rom)
def __init__(self, platform, spiboot=False, **kwargs):
Sim.__init__(self,
platform,
custom_clocks=local_clocks,
spiboot=spiboot,
**kwargs) # SoC magic is in here
# external SRAM
# rd_timing = 8 -> 80ns cycle time. 70ns Taa, but you need setup/hold time to sample the data!
# page_rd_timing = 3 -> 30ns access cycle, gives 5ns for setup/hold
self.submodules.sram_ext = sram_32_cached.SRAM32(
platform.request("sram"),
rd_timing=7,
wr_timing=7,
page_rd_timing=3,
l2_cache_size=0x1000)
self.add_csr("sram_ext")
self.register_mem("sram_ext",
self.mem_map["sram_ext"],
self.sram_ext.bus,
size=0x1000000)
def __init__(self, platform, spiboot=False, **kwargs):
Sim.__init__(self,
platform,
custom_clocks=local_clocks,
spiboot=spiboot,
**kwargs) # SoC magic is in here
SoCCore.mem_map[
"vectors"] = 0x30000000 # add test vector ROM area, cached OK
# sim=True parameter uses explicit copy of DSP48E1 primitive to aid with internal debug
self.submodules.engine = ClockDomainsRenamer({
"eng_clk": "clk50",
"rf_clk": "clk200",
"mul_clk": "sys"
})(Engine(platform, self.mem_map["engine"], sim=True))
self.add_csr("engine")
self.add_interrupt("engine")
self.bus.add_slave(
"engine", self.engine.bus,
SoCRegion(origin=self.mem_map["engine"],
size=0x2_0000,
cached=False))
def __init__(self, platform, spiboot=False, **kwargs):
if ICE40:
SoCCore.mem_map = {
} # clear the default map provided by the simulation
SoCCore.mem_map["rom"] = 0x0
SoCCore.mem_map["sram"] = 0x01000000
SoCCore.mem_map["com"] = 0xd0000000 # when simulating ICE40
SoCCore.mem_map["csr"] = 0xe0000000
else:
SoCCore.mem_map["wifi"] = 0xe0010000 # when simulating 7-series
Sim.__init__(self,
platform,
custom_clocks=local_clocks,
spiboot=spiboot,
vex_verilog_path=VEX_CPU_PATH,
**kwargs) # SoC magic is in here
# SPI interface
self.submodules.spicontroller = ClockDomainsRenamer({"sys": "spi"})(
spi_7series.SPIController(platform.request("com"),
pipeline_cipo=True))
self.add_csr("spicontroller")
self.clock_domains.cd_sclk = ClockDomain()
self.comb += self.cd_sclk.clk.eq(self.spicontroller.sclk)
self.submodules.com = spi_ice40.SpiFifoPeripheral(
platform.request("peripheral"), pipeline_cipo=True)
self.comb += self.com.oe.eq(1),
self.bus.add_slave(
"com", self.com.bus,
SoCRegion(origin=self.mem_map["com"],
size=4,
mode="rw",
cached=False))
#self.add_wb_slave(self.mem_map["com"], self.com.bus, 4)
#self.add_memory_region("com", self.mem_map["com"], 4, type='io')
self.add_csr("com")