def __init__(self,
inputInstruction, inputFlags,
outputState, outputHalted,
outputALUSelA, outputALUSelB, outputALUOp, outputLdFlags,
outputLdPC, outputLdIR, outputLdReg,
outputLdMAR, outputLdMDR,
outputMemRead, outputMemWrite,
):
assert inputInstruction.width == 8
assert outputALUSelA.width == bits_required(ALUSelA.NUM_ALU_A)
assert outputALUSelB.width == bits_required(ALUSelB.NUM_ALU_B)
assert outputALUOp.width == bits_required(ALUOp.NUM_ALU_OPS)
assert all(
elem.width == 1
for elem in (
outputLdFlags, outputLdPC, outputLdIR, outputLdReg,
outputLdMAR, outputLdMDR, outputMemRead, outputMemWrite,
)
)
super(Controller, self).__init__()
self.inputInstruction = inputInstruction
self.inputFlags = inputFlags
inputInstruction.register_callback(self.update)
inputFlags.register_callback(self.update)
self.outputState = outputState
self.outputHalted = outputHalted
self.outputALUSelA = outputALUSelA
self.outputALUSelB = outputALUSelB
self.outputALUOp = outputALUOp
self.outputLdFlags = outputLdFlags
self.outputLdPC = outputLdPC
self.outputLdIR = outputLdIR
self.outputLdReg = outputLdReg
self.outputLdMAR = outputLdMAR
self.outputLdMDR = outputLdMDR
self.outputMemRead = outputMemRead
self.outputMemWrite = outputMemWrite
def main(argv):
try:
filePath = argv[1]
except IndexError:
return error("Must provide a *.bin file!")
try:
with open(filePath, 'rb') as f:
data = f.read()
except IOError:
return error("Coud not open file '{}'!".format(filePath))
controlALUSelA = Wire(bits_required(ALUSelA.NUM_ALU_A))
controlALUSelB = Wire(bits_required(ALUSelB.NUM_ALU_B))
controlALUOp = Wire(bits_required(ALUOp.NUM_ALU_OPS))
aluA = Wire(8)
aluB = Wire(8)
aluOp = controlALUOp
aluFlags = Wire(4)
aluOut = Wire(8)
controlLdFlags = Wire(1)
flagsEn = controlLdFlags
flagsQ = Wire(4)
controlLdPC = Wire(1)
pcEn = controlLdPC
pcQ = Wire(8)
controlLdIR = Wire(1)
irEn = controlLdIR
irQ = Wire(8)
controlLdReg = Wire(1)
regWriteEn = controlLdReg
regOutA = Wire(8)
regOutB = Wire(8)
controlLdMAR = Wire(1)
marEn = controlLdMAR
marQ = Wire(8)
controlLdMDR = Wire(1)
controlMemRead = Wire(1)
mdrD = Wire(8)
mdrEn = Wire(1)
mdrQ = Wire(8)
controlMemWrite = Wire(1)
memWriteEn = controlMemWrite
memOut = Wire(8)
signalState = Wire(16)
signalHalted = Wire(1)
fsm = Controller(
irQ, flagsQ,
signalState, signalHalted,
controlALUSelA, controlALUSelB, controlALUOp, controlLdFlags,
controlLdPC, controlLdIR, controlLdReg,
controlLdMAR, controlLdMDR,
controlMemRead, controlMemWrite,
)
aluSelA = controlALUSelA
Mux(3, 8, aluSelA, regOutA, pcQ, mdrQ, aluA)
aluSelB = controlALUSelB
Mux(2, 8, aluSelB, regOutB, Wire(8, init=1), aluB)
alu = ALU(aluA, aluB, aluOp, aluFlags, aluOut)
flags = Register(4, aluFlags, flagsEn, flagsQ)
pc = Register(8, aluOut, pcEn, pcQ)
ir = Register(8, aluOut, irEn, irQ)
regFile = RegFile(irQ, aluOut, regWriteEn, regOutA, regOutB)
mar = Register(8, aluOut, marEn, marQ)
Mux(2, 8, controlMemRead, aluOut, memOut, mdrD)
OrGate(2, 1, controlLdMDR, controlMemRead, mdrEn)
mdr = Register(8, mdrD, mdrEn, mdrQ)
mem = Memory(256, marQ, memWriteEn, mdrQ, memOut)
mem.load_bytes(data)
debugger = Debugger(
regFile,
signalState, signalHalted,
pcQ, irQ, marQ, mdrQ,
aluA, aluB, aluOut, flagsQ,
)
try:
Element.simulate_datapath()
except HaltExecution as e:
print e
print ""
print "Mem Dump:"
print ['0x{:02x}'.format(b) for b in mem.state.mem]
