def _generate_regwr(conditionMet, op, funct, rd):
"""
REGWR <= '1' when an instruction writes back to the regfile
REGWR <= '0' when an instruction does not write back to the regfile
(str, branch, and cmp instructions)
"""
if not conditionMet:
return 0
if rd == 15: # PC not in register file, use PC path
return 0b0
elif op == ISA.OpCodes.DATA_PROCESS.value:
cmd = ISA.parse_function_get_cmd(funct)
if (cmd == ISA.DataCMDCodes.TST.value
or cmd == ISA.DataCMDCodes.TEQ.value
or cmd == ISA.DataCMDCodes.CMP.value
or cmd == ISA.DataCMDCodes.CMN.value):
return 0b0
else:
return 0b1
elif op == ISA.OpCodes.MEMORY_SINGLE.value and not ISA.parse_function_get_l(
funct):
return 0b0
elif op == ISA.OpCodes.BRANCH.value and ISA.parse_function_get_l(
funct, True) == 0b0:
return 0b0
else:
return 0b1
def _generate_regsrc(op, funct):
"""
REGSRC <= '1' when output of ALU is feedback (ldr instructions)
REGSRC <= '0' when output of data mem is feedback
"""
if op == ISA.OpCodes.MEMORY_SINGLE.value and ISA.parse_function_get_l(
funct):
return 0b0
else:
return 0b1
def _generate_memwr(conditionMet, op, funct):
"""
MEMWR <= '1' allows data to be written to data memory (str
instructions)
MEMWR <= '0' cannot write to data memory
"""
if not conditionMet:
return 0b0
if op == ISA.OpCodes.MEMORY_SINGLE.value and not ISA.parse_function_get_l(
funct):
return 0b1
else:
return 0b0
def _generate_regwrs(op, shift, funct):
"""
REGWRS <= B"10" to select LR (bl instruction)
REGWRS <= B"01" to select Rd (data processing instruction)
REGWRS <= B"00" to select Rd (mul instruction)
"""
if op == ISA.OpCodes.BRANCH.value and ISA.parse_function_get_l(
funct, True):
return 0b10
elif op == ISA.OpCodes.DATA_PROCESS.value and ISA.is_multiply(
funct, shift):
return 0b00
else:
return 0b01
def _generate_regdst(op, shift, funct):
"""
REGDST <= B"10" to select Rd (str instruction)
REGDST <= B"01" to select Rm (data processing intructions)
REGDST <= B"00" to select Rm (mul instruction)
"""
if op == ISA.OpCodes.MEMORY_SINGLE.value and not ISA.parse_function_get_l(
funct):
return 0b10
elif op == ISA.OpCodes.DATA_PROCESS.value and ISA.is_multiply(
funct, shift):
return 0b00
else:
return 0b01
def _generate_wd3s(op, funct):
"""
WDS3 <= '1' when a bl instruction is run else '0'
"""
return op == ISA.OpCodes.BRANCH.value and ISA.parse_function_get_l(
funct, True)