def ins_slt(self, args):
"""
Opcode: 000000
Fcode: 101010
Syntax: ArithLog
"""
return self.arith_TEMPLATE('slt', args,
lambda a, b: 1 if s32(a) < s32(b) else 0)
def ins_sub(self, args, unsigned = False):
"""
Opcode: 000000
Fcode: 100010
Syntax: ArithLog
"""
sub_name = 'subu' if unsigned else 'sub'
if unsigned:
sub_func = lambda a, b: a - b
else:
sub_func = lambda a, b: s32(a) - s32(b)
return self.arith_TEMPLATE(sub_name, args, sub_func)
def ins_add(self, args, unsigned = False):
"""
Opcode: 000000
Fcode: 100000
Syntax: ArithLog
"""
add_name = 'addu' if unsigned else 'add'
if unsigned:
add_func = lambda a, b: a + b
else:
add_func = lambda a, b: s32(a) + s32(b)
return self.arith_TEMPLATE(add_name, args, add_func)
def ins_srav(self, args):
"""
Opcode: 000000
Fcode: 000111
Syntax: ShiftV
"""
return self.shift_TEMPLATE('srav', args, False, lambda a, b: s32(a) >> b)
def ins_sra(self, args):
"""
Opcode: 000000
Fcode: 000011
Syntax: Shift
"""
return self.shift_TEMPLATE('sra', args, True, lambda a, b: s32(a) >> b)
def ins_slti(self, args):
"""
Opcode: 000000
Fcode: 001010
Syntax: ArithLog
"""
return self.imm_TEMPLATE('slti', args,
lambda a, b: 1 if s32(a) < b else 0)
def ins_addi(self, args):
"""
Opcode: 001000
Syntax: ArithLogI
"""
return self.imm_TEMPLATE('addi', args, lambda a, b: s32(a) + b)
def _asm_branch(b):
if _lambda_f(s32(b[reg_s]), s32(b[reg_t])):
if link: b[31] = b.PC + self.JAL_OFFSET
b.PC = _asm_branch.label_address
