Example #1
0
    def __init__(self):
        self._parser = Parser()
        self._registers = OrderedDict([
            ('S' + str(i), uint8(0))
            for i in [*range(10), *[j for j in 'ABCDEF']]
        ])
        self._instructions = {addr: None for addr in range(1024)}
        self._ram = {addr: uint8(0) for addr in range(64)}
        self._labels = {}
        self._carry = 0
        self._zero = 0
        self._stack = []

        self._interrupt_enabled = False
        self._pre_zero = 0
        self._pre_carry = 0
        self._interrupt_caused = False

        self._program_cnt = 0

        lex.lex(module=tokenizer_rules)
        self._parser.tokens = tokenizer_rules.tokens
        self._yacc = yacc.yacc(module=self._parser)

        self.__handlers = {
            ADD: self._handle_ADD,
            ADDC: self._handle_ADDC,
            AND: self._handle_AND,
            CALL: self._handle_CALL,
            COMP: self._handle_COMP,
            DINT: self._handle_DINT,
            EINT: self._handle_EINT,
            FETCH: self._handle_FETCH,
            IN: self._handle_IN,
            JUMP: self._handle_JUMP,
            LOAD: self._handle_LOAD,
            OR: self._handle_OR,
            OUT: self._handle_OUT,
            RET: self._handle_RET,
            RETI: self._handle_RETI,
            RL: self._handle_RL,
            SL0: self._handle_SL0,
            SL1: self._handle_SL1,
            SLA: self._handle_SLA,
            SLX: self._handle_SLX,
            RR: self._handle_RR,
            SR0: self._handle_SR0,
            SR1: self._handle_SR1,
            SRA: self._handle_SRA,
            SRX: self._handle_SRX,
            STORE: self._handle_STORE,
            SUB: self._handle_SUB,
            SUBC: self._handle_SUBC,
            TEST: self._handle_TEST,
            XOR: self._handle_XOR,
        }
Example #2
0
 def _handle_IN(self, *args):
     # there could be some port simulator in further version of VM class,
     # for now we assume that there are only zeros on input
     if args[1] < 0 or args[1] > 63:
         raise ValueError('Error in address {0}: no such port "{1}"'.format(
             str(self._program_cnt), args[1]))
     self.registers[args[0]] = uint8(0)
     self._program_cnt += 1
Example #3
0
 def _handle_LOAD(self, *args):
     self.registers[args[0]] = uint8(args[1])
     self._program_cnt += 1
def test_getitem():
    assert uint8(16)[4] == 1
    assert uint8(16)[5] == 0
    for i in range(8):
        assert uint8(255)[i] == 1
        assert uint8(0)[i] == 0
def test_lshift():
    assert (uint8(0), 1) == uint8(128) << 1
    assert (uint8(128), 1) == uint8(192) << 1
    assert (uint8(64), 0) == uint8(32) << 1
def test_constructor2():
    assert uint8(256) == uint8(0)
    assert uint8(260) == uint8(4)
    assert uint8(-1) == uint8(255)
    assert uint8(-5) == uint8(251)
    assert uint8(-5) != uint8(252)
def test_eq_int():
    assert uint8(42) == 42
    assert uint8(256) == 0
    assert uint8(-1) == 255
def test_mod():
    assert uint8(32) % 2 == 0
    assert uint8(5) % uint8(2) == 1
def test_and_other():
    assert uint8(24) == uint8(31) & uint8(24)
    assert uint8(0) == uint8(17) & uint8(12)
    val = uint8(31)
    val &= uint8(24)
    assert val == uint8(24)
def test_and_int():
    assert uint8(24) == uint8(31) & 24
    assert uint8(0) == uint8(17) & 12
    val = uint8(31)
    val &= 24
    assert val == uint8(24)
def test_sub_int():
    assert (uint8(246), 1) == uint8(20) - 30
    assert (uint8(239), 0) == uint8(250) - 11
    assert (uint8(7), 0) == uint8(1) - -6
def test_constructor1():
    assert int(uint8(20)) == 20
def test_sub_other():
    assert (uint8(246), 1) == uint8(20) - uint8(30)
    assert (uint8(239), 0) == uint8(250) - uint8(11)
def test_add_int():
    assert (uint8(50), 0) == uint8(20) + 30
    assert (uint8(5), 1) == uint8(250) + 11
    assert (uint8(251), 1) == uint8(1) + -6
def test_add_other():
    assert (uint8(50), 0) == uint8(20) + uint8(30)
    assert (uint8(5), 1) == uint8(250) + uint8(11)