print "\n###########################\nDumping global config parameters:"
for key in g_params:
print key + " " + g_params[key]
print "###########################\n"
numChannels = int(g_params["numChannels"])
maxOutstandingReqs = numChannels*64
numTxnPerCycle = numChannels
maxTxns = 100000 * numChannels
# Define SST core options
sst.setProgramOption("timebase", g_params["clockCycle"])
sst.setProgramOption("stopAtCycle", g_params["stopAtCycle"])
sst.setStatisticLoadLevel(7)
sst.setStatisticOutput("sst.statOutputConsole")
#########################################################################################################
## Configure transaction generator
comp_txnGen = sst.Component("TxnGen", "CramSim.c_TxnGen")
comp_txnGen.addParams(g_params)
comp_txnGen.addParams({
"maxTxns" : maxTxns,
"numTxnPerCycle" : numTxnPerCycle,
"maxOutstandingReqs" : maxOutstandingReqs,
"readWriteRatio" : 0.5
})
comp_txnGen.enableAllStatistics()
sst.setProgramOption("timebase", "1 ps")
sst.setProgramOption("stopAtCycle", "200ns")
########################################################################
########################################################################
# Set the Statistic Load Level; Statistics with Enable Levels (set in
# elementInfoStatistic) lower or equal to the load can be enabled (default = 0)
sst.setStatisticLoadLevel(7)
# Set the desired Statistic Output (sst.statOutputConsole is default)
#sst.setStatisticOutput("sst.statOutputConsole")
#sst.setStatisticOutput("sst.statOutputTXT", {"filepath" : "./TestOutput.txt"
# })
sst.setStatisticOutput("sst.statOutputCSV", {"filepath" : "./TestOutput.csv",
"separator" : ", "
})
#sst.setStatisticOutputOptions({"outputtopheader" : "1",
# "outputinlineheader" : "1",
# "outputsimtime": "1",
# "outputrank": "1",
# "help" : "help" })
#sst.setStatisticOutputOption("outputtopheader", "1")
#sst.setStatisticOutputOption("outputinlineheader", "1")
#sst.setStatisticOutputOption("outputsimtime", "1")
#sst.setStatisticOutputOption("outputrank", "1")
#sst.setStatisticOutputOption("help", "help")
########################################################################
########################################################################
"clock": clock,
"maxcorequeue": 256,
"maxissuepercycle": 2,
"pipetimeout": 0,
"corecount": corecount,
"arielmode": 1,
"memorylevels": 1,
"pagecount0": num_pages,
"pagesize0": pageSize * 1024,
"arielstack": 1,
"defaultlevel": 0,
}
)
sieveId = sst.Component("sieve", "memHierarchy.Sieve")
sieveId.addParams({"cache_size": "8MB", "associativity": 16, "cache_line_size": 64, "output_file": "mallocRank.txt"})
for x in range(corecount):
arielL1Link = sst.Link("cpu_cache_link_%d" % x)
arielL1Link.connect((ariel, "cache_link_%d" % x, busLat), (sieveId, "cpu_link_%d" % x, busLat))
arielALink = sst.Link("cpu_alloc_link_%d" % x)
arielALink.connect((ariel, "alloc_link_%d" % x, busLat), (sieveId, "alloc_link_%d" % x, busLat))
statoutputs = dict([(1, "sst.statOutputConsole"), (2, "sst.statOutputCSV"), (3, "sst.statOutputTXT")])
sst.setStatisticLoadLevel(7)
sst.setStatisticOutput(statoutputs[2])
sst.enableAllStatisticsForAllComponents()
print "done configuring SST"
mem.addParams(mem_params)
dc = sst.Component("dc_" + str(next_memory_ctrl_id), "memHierarchy.DirectoryController")
dc.addParams({
"network_address" : next_network_id,
"addr_range_start" : next_memory_ctrl_id * mem_interleave_size,
"addr_range_end" : (memory_capacity * 1024 * 1024) - (groups * memory_controllers_per_group * mem_interleave_size) + (next_memory_ctrl_id * mem_interleave_size)
})
dc.addParams(dc_params)
memLink = sst.Link("mem_link_" + str(next_memory_ctrl_id))
memLink.connect((mem, "direct_link", ring_latency), (dc, "memory", ring_latency))
netLink = sst.Link("dc_link_" + str(next_memory_ctrl_id))
netLink.connect((dc, "network", ring_latency), (router_map["rtr." + str(next_network_id)], "port2", ring_latency))
next_network_id = next_network_id + 1
next_memory_ctrl_id = next_memory_ctrl_id + 1
# Enable SST Statistics Outputs for this simulation
sst.setStatisticLoadLevel(4)
sst.enableAllStatisticsForAllComponents({"type":"sst.AccumulatorStatistic"})
sst.setStatisticOutput("sst.statOutputCSV")
sst.setStatisticOutputOptions( {
"filepath" : "./stats-snb-ariel.csv",
"separator" : ", "
} )
print "Completed configuring the SST Sandy Bridge model"
if ( stats != 0 ):
print "Statistic dump period (0 = end of sim only):"
rate = raw_input();
if ( rate == "" ):
rate = "0"
sst.setStatisticLoadLevel(stats)
print "Please select statistics output type:"
for (x,y) in statoutputs.iteritems():
print "[ %d ] %s" % (x, y)
output = int(raw_input())
if output not in statoutputs:
print "Bad answer. try again."
sys.exit(1)
sst.setStatisticOutput(statoutputs[output]);
if (output != 1):
print "Filename for stats output:"
filename = raw_input()
sst.setStatisticOutputOptions({
"filepath" : filename,
"separator" : ", "
})
endPoint.enableAllStatistics(rate)
topo.prepParams()
endPoint.prepParams()
topo.setEndPoint(endPoint)
topo.build()
"max_requests_per_cycle": 1,
"backing": "none",
"backend": "memHierarchy.DelayBuffer",
"backend.request_delay": "150ns",
"backend.backend": "memHierarchy.simpleDRAM",
"backend.backend.tCAS": 3, # 11@800MHz roughly coverted to 200MHz
"backend.backend.tRCD": 2,
"backend.backend.tRP": 4,
"backend.backend.cycle_time": "4ns",
"backend.backend.row_size": "4KiB",
"backend.backend.row_policy": "open"
})
# Enable statistics
sst.setStatisticLoadLevel(7)
sst.setStatisticOutput("sst.statOutputConsole")
sst.enableAllStatisticsForComponentType("memHierarchy.Cache")
sst.enableAllStatisticsForComponentType("memHierarchy.MemController")
sst.enableAllStatisticsForComponentType("memHierarchy.DirectoryController")
# Define the simulation links
link_c0_l1cache = sst.Link("link_c0_l1cache")
link_c0_l1cache.connect((comp_cpu0, "mem_link", "500ps"),
(comp_c0_l1cache, "high_network_0", "500ps"))
link_c0L1cache_bus = sst.Link("link_c0L1cache_bus")
link_c0L1cache_bus.connect((comp_c0_l1cache, "low_network_0", "1000ps"),
(comp_n0_bus, "high_network_0", "1000ps"))
link_c1_l1cache = sst.Link("link_c1_l1cache")
link_c1_l1cache.connect((comp_cpu1, "mem_link", "500ps"),
(comp_c1_l1cache, "high_network_0", "500ps"))
link_c1L1cache_bus = sst.Link("link_c1L1cache_bus")
"backend.access_time" : "100 ns",
"backend.mem_size" : "4096MiB",
"backend.system_ini" : "system.ini",
"backend.device_ini" : "DDR3_micron_32M_8B_x4_sg125.ini",
"clock" : "1 GHz",
"request_width" : "128"
})
# Define the SST Component Statistics Information
# Define SST Statistics Options:
sst.setStatisticLoadLevel(7)
sst.setStatisticOutput("sst.statoutputcsv", {
"separator" : ",",
"filepath" : "sst.stat.csv",
"outputtopheader" : 1,
"outputsimtime" : 1,
"outputrank" : 1,
})
# Define Component Statistics Information:
sst.enableAllStatisticsForComponentType("memHierarchy.Cache")
sst.enableAllStatisticsForComponentType("memHierarchy.MemController")
#comp_core0l1dcache.enableAllStatistics({"type":"sst.AccumulatorStatistic", "rate":"0ns", "startat":"0ns", "stopat":"0ns"})
# Define SST Simulation Link Information
link_c0_icache = sst.Link("link_c0_icachec0_icache")
link_c0_icache.connect( (comp_gpu0, "core0-icache", "1000ps"), (comp_core0l1icache, "high_network_0", "1000ps") )
link_c0_dcache = sst.Link("link_c0_dcachec0_dcache")
link_c0_dcache.connect( (comp_gpu0, "core0-dcache", "1000ps"), (comp_core0l1dcache, "high_network_0", "1000ps") )
"pagecount0": num_pages,
"pagesize0": pageSize * 1024,
"arielstack": 1,
"defaultlevel": 0
})
sieveId = sst.Component("sieve", "memHierarchy.Sieve")
sieveId.addParams({
"cache_size": "8MB",
"associativity": 16,
"cache_line_size": 64,
"output_file": "mallocRank.txt"
})
for x in range(corecount):
arielL1Link = sst.Link("cpu_cache_link_%d" % x)
arielL1Link.connect((ariel, "cache_link_%d" % x, busLat),
(sieveId, "cpu_link_%d" % x, busLat))
arielALink = sst.Link("cpu_alloc_link_%d" % x)
arielALink.connect((ariel, "alloc_link_%d" % x, busLat),
(sieveId, "alloc_link_%d" % x, busLat))
statoutputs = dict([(1, "sst.statOutputConsole"), (2, "sst.statOutputCSV"),
(3, "sst.statOutputTXT")])
sst.setStatisticLoadLevel(7)
sst.setStatisticOutput(statoutputs[2])
sst.enableAllStatisticsForAllComponents()
print "done configuring SST"
#########################################################################
## Connect components with the links
#########################################################################
core_cache.connect((core, "cache_link", "100ps"),
(l1_cache, "high_network_0", "100ps"))
l1_l2_cache.connect((l1_cache, "low_network_0", "100ps"),
(l2_cache, "high_network_0", "100ps"))
llc_mem.connect((l2_cache, "low_network_0", "100ps"),
(memctrl, "direct_link", "100ps"))
#########################################################################
## Statistics
#########################################################################
# Enable SST Statistics Outputs for this simulation
# Generate statistics in CSV format
sst.setStatisticOutput("sst.statoutputcsv")
# Send the statistics to a fiel called 'stats.csv'
sst.setStatisticOutputOptions({"filepath": "stats_demo-4.csv"})
# Print statistics of level 5 and below (0-5)
sst.setStatisticLoadLevel(5)
# Enable statistics for all the component
sst.enableAllStatisticsForAllComponents()
print "\nCompleted configuring the Demo_4 model\n"
################################ The End ################################
next_memory_ctrl_id * mem_interleave_size,
"addr_range_end": (memory_capacity * 1024 * 1024) -
(groups * memory_controllers_per_group * mem_interleave_size) +
(next_memory_ctrl_id * mem_interleave_size)
})
dc.addParams(dc_params)
memLink = sst.Link("mem_link_" + str(next_memory_ctrl_id))
memLink.connect((memctrl, "direct_link", ring_latency),
(dc, "memory", ring_latency))
netLink = sst.Link("dc_link_" + str(next_memory_ctrl_id))
netLink.connect(
(dc, "network", ring_latency),
(router_map["rtr." + str(next_network_id)], "port2", ring_latency))
next_network_id = next_network_id + 1
next_memory_ctrl_id = next_memory_ctrl_id + 1
# Enable SST Statistics Outputs for this simulation
sst.setStatisticLoadLevel(4)
sst.enableAllStatisticsForAllComponents({"type": "sst.AccumulatorStatistic"})
sst.setStatisticOutput("sst.statOutputCSV")
sst.setStatisticOutputOptions({
"filepath": "./stats-snb-ariel.csv",
"separator": ", "
})
print("Completed configuring the SST Sandy Bridge model")
(next_group_id, next_mem_id, next_cache))
print(" - Start Address: " + str(hex(cacheStartAddr)) +
" End Address: " + str(hex(endAddr)))
l2g = sst.Component("l2gcache_%d" % (next_cache), "memHierarchy.Cache")
l2g.addParams(config.getGPUL2Params(cacheStartAddr, endAddr))
connect("l2g_xbar_link_%d" % (next_cache), GPUrouter,
"port%d" % (config.gpu_cores + (next_cache)), l2g, "cache",
config.default_link_latency).setNoCut()
connect("l2g_mem_link_%d" % (next_cache), l2g, "low_network_0",
mem_l2_bus, "high_network_%d" % (next_mem_id),
config.default_link_latency).setNoCut()
print("++ %d-%d (%d)..." % (next_cache, sub_mems,
(next_cache + 1) % sub_mems))
if (next_cache + 1) % sub_mems == 0:
next_cache = next_cache + total_mems - (sub_mems - 1)
else:
next_cache = next_cache + 1
# ===============================================================================
# Enable SST Statistics Outputs for this simulation
sst.setStatisticLoadLevel(statLevel)
sst.enableAllStatisticsForAllComponents({"type": "sst.AccumulatorStatistic"})
sst.setStatisticOutput("sst.statOutputTXT", {"filepath": statFile})
print("Completed configuring the cuda-test model")
#
# Copyright 2009-2015 Sandia Corporation. Under the terms
# of Contract DE-AC04-94AL85000 with Sandia Corporation, the U.S.
# Government retains certain rights in this software.
#
# Copyright (c) 2009-2015, Sandia Corporation
# All rights reserved.
#
# This file is part of the SST software package. For license
# information, see the LICENSE file in the top level directory of the
# distribution.
import sst
sst.setStatisticLoadLevel(3)
sst.setStatisticOutput("sst.statOutputCSV", {
"filepath": "./TestOutput.csv",
"separator": ","
})
from sst.merlin import *
sst.merlin._params["flit_size"] = "16B"
sst.merlin._params["link_bw"] = "4.0GB/s"
sst.merlin._params["xbar_bw"] = "4.0GB/s"
sst.merlin._params["input_latency"] = "0.0ns"
sst.merlin._params["output_latency"] = "0.0ns"
sst.merlin._params["input_buf_size"] = "16.0KB"
sst.merlin._params["output_buf_size"] = "16.0KB"
sst.merlin._params["link_lat"] = "5000ns"
merlintorusparams = {}
merlintorusparams["num_dims"] = 1
if ( stats != 0 ):
print "Statistic dump period (0 = end of sim only):"
rate = raw_input();
if ( rate == "" ):
rate = "0"
sst.setStatisticLoadLevel(stats)
print "Please select statistics output type:"
for (x,y) in statoutputs.iteritems():
print "[ %d ] %s" % (x, y)
output = int(raw_input())
if output not in statoutputs:
print "Bad answer. try again."
sys.exit(1)
sst.setStatisticOutput(statoutputs[output]);
if (output != 1):
print "Filename for stats output:"
filename = raw_input()
sst.setStatisticOutputOptions({
"filepath" : filename,
"separator" : ", "
})
endPoint.enableAllStatistics(rate)
topo.prepParams()
endPoint.prepParams()
topo.setEndPoint(endPoint)
topo.build()
# Connections
# cpu <-> L1
cpu_cache_link = sst.Link("cpu_l1_cache_link")
cpu_cache_link.connect(
(cache_port, "port", cache_link_latency),
(cache_bus, "high_network_0", cache_link_latency)
)
system_cache_link = sst.Link("system_cache_link")
system_cache_link.connect(
(system_port, "port", cache_link_latency),
(cache_bus, "high_network_1", cache_link_latency)
)
cache_bus_cache_link = sst.Link("cache_bus_cache_link")
cache_bus_cache_link.connect(
(cache_bus, "low_network_0", cache_link_latency),
(l1_cache, "high_network_0", cache_link_latency)
)
# L1 <-> mem
cache_mem_link = sst.Link("l1_cache_mem_link")
cache_mem_link.connect(
(l1_cache, "low_network_0", cache_link_latency),
(memctrl, "direct_link", cache_link_latency)
)
# enable Statistics
stat_params = { "rate" : "0ns" }
sst.setStatisticLoadLevel(5)
sst.setStatisticOutput("sst.statOutputTXT", {"filepath" : "./sst-stats.txt"})
sst.enableAllStatisticsForComponentName("l1_cache", stat_params)
sst.enableAllStatisticsForComponentName("memory", stat_params)
"associativity": "96",
"cache_frequency": "1312MHz",
"cache_line_size": "64",
"cache_size": "192KiB",
"cache_type": "noninclusive",
"coherence_protocol": "MESI",
"debug": "0",
"debug_level": "10",
"memNIC.addr_range_end": "17179868928",
"memNIC.addr_range_start": "768",
"memNIC.group": "2",
"memNIC.interleave_size": "256B",
"memNIC.interleave_step": "1024B",
"memNIC.network_bw": "37.5GB/s",
"memNIC.network_link_control": "shogun.ShogunNIC",
"mshr_num_entries": "2048",
"replacement_policy": "lru",
"verbose": "2"
})
comp_l2cache_3.setCoordinates(0, 0, 0)
comp_l2cache_3.enableAllStatistics({"type": "sst.AccumulatorStatistic"})
comp_l2cache_3.addLink(link_id_00000026, "cache", "100ps")
comp_l2cache_3.addLink(link_id_00000027, "low_network_0", "100ps")
# Define SST Statistics Options:
sst.setStatisticLoadLevel(16)
sst.setStatisticOutput("sst.statOutputCSV", {
"filepath": "test-out-600k-c.csv",
"separator": ", "
})
# End of generated output.
"coherence_protocol": "MESI",
"backend": "memHierarchy.cramsim",
"backend.access_time": "100 ns",
"backend.mem_size": "4096MiB",
"clock": "1GHz",
"rangeStart": "0",
"request_width": "128"
})
# Define the SST Component Statistics Information
# Define SST Statistics Options:
sst.setStatisticLoadLevel(7)
sst.setStatisticOutput(
"sst.statoutputcsv", {
"separator": ",",
"filepath": "sst.stat.csv",
"outputtopheader": 1,
"outputsimtime": 1,
"outputrank": 1,
})
# Define Component Statistics Information:
sst.enableAllStatisticsForComponentType("memHierarchy.Cache")
sst.enableAllStatisticsForComponentType("memHierarchy.MemController")
#comp_core0l1dcache.enableAllStatistics({"type":"sst.AccumulatorStatistic", "rate":"0ns", "startat":"0ns", "stopat":"0ns"})
# Define SST Simulation Link Information
link_c0_icache = sst.Link("link_c0_icachec0_icache")
link_c0_icache.connect((comp_gpu0, "core0-icache", "1000ps"),
(comp_core0l1icache, "high_network_0", "1000ps"))
link_c0_dcache = sst.Link("link_c0_dcachec0_dcache")
link_c0_dcache.connect((comp_gpu0, "core0-dcache", "1000ps"),
