def init(statFile):
sst.setStatisticLoadLevel(16)
sst.enableAllStatisticsForAllComponents(
{"type": "sst.AccumulatorStatistic"})
sst.setStatisticOutput("sst.statOutputCSV")
sst.setStatisticOutputOptions({"filepath": statFile, "separator": ", "})
def init(outputFile):
sst.setStatisticLoadLevel(9)
sst.setStatisticOutput("sst.statOutputCSV")
sst.setStatisticOutputOptions({"filepath": outputFile, "separator": ", "})
sst.enableStatisticForComponentType("firefly.nic", 'mem_num_stores', {
"type": "sst.AccumulatorStatistic",
"rate": "0ns"
})
sst.enableStatisticForComponentType("firefly.nic", 'mem_num_loads', {
"type": "sst.AccumulatorStatistic",
"rate": "0ns"
})
sst.enableStatisticForComponentType(
"firefly.nic", 'mem_addrs', {
"type": "sst.HistogramStatistic",
"rate": "0ns",
"binwidth": "4096",
"numbins": "512"
})
"cache_line_size": "64",
"prefetcher": "cassini.StridePrefetcher",
"debug": "0",
"L1": "1",
"cache_size": "512B"
})
comp_memory = sst.Component("memory", "memHierarchy.MemController")
comp_memory.addParams({"clock": "1GHz"})
backend = comp_memory.setSubComponent("backend", "memHierarchy.simpleMem")
backend.addParams({
"access_time": "10 ns",
"mem_size": str(max_addr_gb) + "GiB",
})
sst.setStatisticOutput("sst.statOutputCSV")
sst.enableAllStatisticsForAllComponents()
sst.setStatisticOutputOptions({"filepath": "output.csv"})
# Define the simulation links
link_cpu_cache_link = sst.Link("link_cpu_cache_link")
link_cpu_cache_link.connect((comp_cpu, "cache_link", "1000ps"),
(comp_l1cache, "high_network_0", "1000ps"))
link_cpu_cache_link.setNoCut()
link_mem_bus_link = sst.Link("link_mem_bus_link")
link_mem_bus_link.connect((comp_l1cache, "low_network_0", "50ps"),
(comp_memory, "direct_link", "50ps"))
next_memory_ctrl_id * mem_interleave_size,
"memNIC.addr_range_end": (memory_capacity * 1024 * 1024) -
(groups * memory_controllers_per_group * mem_interleave_size) +
(next_memory_ctrl_id * mem_interleave_size)
})
dc.addParams(dc_params)
memLink = sst.Link("mem_link_" + str(next_memory_ctrl_id))
memLink.connect((memctrl, "direct_link", ring_latency),
(dc, "memory", ring_latency))
netLink = sst.Link("dc_link_" + str(next_memory_ctrl_id))
netLink.connect(
(dc, "network", ring_latency),
(router_map["rtr." + str(next_network_id)], "port2", ring_latency))
next_network_id = next_network_id + 1
next_memory_ctrl_id = next_memory_ctrl_id + 1
# Enable SST Statistics Outputs for this simulation
sst.setStatisticLoadLevel(4)
sst.enableAllStatisticsForAllComponents({"type": "sst.AccumulatorStatistic"})
sst.setStatisticOutput("sst.statOutputCSV")
sst.setStatisticOutputOptions({
"filepath": "./stats-snb-ariel.csv",
"separator": ", "
})
print("Completed configuring the SST Sandy Bridge model")
})
link = sst.Link("B0-%s"%name)
link.connect( (bridge, "network0", "500ps"), (net0.rtr, "port%d"%net0port, "500ps") )
link = sst.Link("B1-%s"%name)
link.connect( (bridge, "network1", "500ps"), (net1.rtr, "port%d"%net1port, "500ps") )
# Network 0
net0 = Network("CPU_Net")
for cpu in range(num_cpu):
buildCPU(cpu, net0)
# Network 1
net1 = Network("MEM_Net")
for mem in range(num_mem):
buildMem(mem, net1)
net2 = Network("Middle_Net")
bridge(net0, net2)
bridge(net1, net2)
sst.setStatisticLoadLevel(16)
sst.enableAllStatisticsForAllComponents({"type": "sst.AccumulatorStatistic"})
sst.setStatisticOutput("sst.statOutputCSV")
sst.setStatisticOutputOptions({
"filepath" : "stats.csv",
"separator" : ", ",
})
cacheDebug = 0
memDebug = 0
memDebugLevel = 0
pageAllocDebug = 0
## Application Info
os.environ['SIM_DESC'] = 'EIGHT_CORES'
os.environ['OMP_NUM_THREADS'] = str(coreCount)
sst_root = os.getenv("SST_ROOT")
# Enable SST Statistics Outputs for this simulation
sst.enableAllStatisticsForAllComponents({"type": "sst.AccumulatorStatistic"})
sst.setStatisticLoadLevel(7)
sst.setStatisticOutput("sst.statOutputCSV")
sst.setStatisticOutputOptions({
"filepath": "%s.csv" % options.StatName,
"separator": ","
})
##### Prepair benchmarr set #########################
print options.BenchmarkType
mt_mode = 0
spec_trace_dir = "spec_trace"
gap_trace_dir = "gap_trace"
if options.BenchmarkType == "spec":
for i in range(0, coreCount):
trace = "./%s/%s-%s0%s" % (spec_trace_dir, options.Benchmark,
options.TraceType, extension)
#trace="./spec_trace/astar-l2-F10B-R4B0.gz"
if os.path.exists(trace) == False:
print "trace file (%s) is not exists" % trace
bus_mem = sst.Link("cache_to_memory_" + str(cache_id))
bus_mem.connect((shogun_xbar, "port" + str(p_n), "100ps"),
(dc_linkctrl, "port", "100ps"))
link_dir_mem = sst.Link("link_dir_mem_" + str(cache_id))
link_dir_mem.connect((dc_memlink, "port", "50ps"),
(memLink, "port", "50ps"))
p_n = p_n + 1
#########################################################################
## Statistics
#########################################################################
# Enable SST Statistics Outputs for this simulation
# Generate statistics in CSV format
sst.setStatisticOutput("sst.statoutputcsv")
# Send the statistics to a fiel called 'stats.csv'
sst.setStatisticOutputOptions({"filepath": "stats_demo-6.csv"})
# Print statistics of level 5 and below (0-5)
sst.setStatisticLoadLevel(5)
# Enable statistics for all the component
sst.enableAllStatisticsForAllComponents()
print "\nCompleted configuring the Demo_6 model\n"
################################ The End ################################
sst.setStatisticLoadLevel(stats)
print "Please select statistics output type:"
for (x,y) in statoutputs.iteritems():
print "[ %d ] %s" % (x, y)
output = int(raw_input())
if output not in statoutputs:
print "Bad answer. try again."
sys.exit(1)
sst.setStatisticOutput(statoutputs[output]);
if (output != 1):
print "Filename for stats output:"
filename = raw_input()
sst.setStatisticOutputOptions({
"filepath" : filename,
"separator" : ", "
})
endPoint.enableAllStatistics(rate)
topo.prepParams()
endPoint.prepParams()
topo.setEndPoint(endPoint)
topo.build()
if ( stats != 0 ):
sst.enableAllStatisticsForComponentType("merlin.hr_router", {"type":"sst.AccumulatorStatistic",
"rate":rate});
#stats.append("port%d_send_bit_count"%l)
#stats.append("port%d_send_packet_count"%l)
mem.addParams({
"backend": "memHierarchy.simpleMem",
"backend.access_time": "30ns",
"backend.mem_size": memory_capacity,
"clock": memory_clock,
"do_not_back": 1,
})
cpu_cache_link = sst.Link("cpu_cache_link")
cpu_cache_link.connect((cpu, "cache_link", cache_link_latency),
(l1, "high_network_0", cache_link_latency))
l2_cache_link = sst.Link("l2cache_link")
l2_cache_link.connect((l1, "low_network_0", cache_link_latency),
(l2, "high_network_0", cache_link_latency))
mem_link = sst.Link("l2cache_mem_link")
mem_link.connect((l2, "low_network_0", cache_link_latency),
(mem, "direct_link", cache_link_latency))
# ===============================================================================
# Enable SST Statistics Outputs for this simulation
sst.setStatisticLoadLevel(statLevel)
sst.enableAllStatisticsForAllComponents({"type": "sst.AccumulatorStatistic"})
sst.setStatisticOutput("sst.statOutputCSV")
sst.setStatisticOutputOptions({"filepath": statFile, "separator": ", "})
print "Completed configuring the EX1 model"
mem.addParams(mem_params)
dc = sst.Component("dc_" + str(next_memory_ctrl_id), "memHierarchy.DirectoryController")
dc.addParams({
"network_address" : next_network_id,
"addr_range_start" : next_memory_ctrl_id * mem_interleave_size,
"addr_range_end" : (memory_capacity * 1024 * 1024) - (groups * memory_controllers_per_group * mem_interleave_size) + (next_memory_ctrl_id * mem_interleave_size)
})
dc.addParams(dc_params)
memLink = sst.Link("mem_link_" + str(next_memory_ctrl_id))
memLink.connect((mem, "direct_link", ring_latency), (dc, "memory", ring_latency))
netLink = sst.Link("dc_link_" + str(next_memory_ctrl_id))
netLink.connect((dc, "network", ring_latency), (router_map["rtr." + str(next_network_id)], "port2", ring_latency))
next_network_id = next_network_id + 1
next_memory_ctrl_id = next_memory_ctrl_id + 1
# Enable SST Statistics Outputs for this simulation
sst.setStatisticLoadLevel(4)
sst.enableAllStatisticsForAllComponents({"type":"sst.AccumulatorStatistic"})
sst.setStatisticOutput("sst.statOutputCSV")
sst.setStatisticOutputOptions( {
"filepath" : "./stats-snb-ariel.csv",
"separator" : ", "
} )
print "Completed configuring the SST Sandy Bridge model"
})
ep.addLink(getLink("rtr.%d.%d"%(x-1,y), "ep0.%d.%d"%(x,y)), "rtr", "800ps")
# Add endpoints
for z in xrange(num_endpoints):
rtr.addLink(getLink("rtr.%d.%d"%(x,y), "ep%d.%d.%d"%(z,x,y)), "local%d"%(z), "800ps")
if add_no_cut:
getLink("rtr.%d.%d"%(x,y), "ep%d.%d.%d"%(z,x,y)).setNoCut()
ep = sst.Component("ep%d.%d.%d"%(z,x,y), "merlin.test_nic")
ep.addParams({
"num_peers" : num_peers,
"link_bw" : "1GB/s",
"linkcontrol_type" : "kingsley.linkcontrol",
"message_size" : msg_size,
"num_messages" : "%d"%(num_messages)
})
ep.addLink(getLink("rtr.%d.%d"%(x,y), "ep%d.%d.%d"%(z,x,y)), "rtr", "800ps")
sst.setStatisticLoadLevel(9)
sst.setStatisticOutput("sst.statOutputCSV");
sst.setStatisticOutputOptions({
"filepath" : "stats.csv",
"separator" : ", "
})
sst.enableAllStatisticsForComponentType("kingsley.noc_mesh", {"type":"sst.AccumulatorStatistic","rate":"0ns"})
link = sst.Link("mem_link_" + str(next_memory_ctrl_id))
link.connect((mem, "direct_link", params.link_latency),
(dc, "memory", params.link_latency))
link = sst.Link("dc_link_" + str(next_memory_ctrl_id))
link.connect((dc, "network", params.link_latency),
(router_map["rtr." + str(next_network_id)], "port2",
params.link_latency))
next_network_id = next_network_id + 1
next_memory_ctrl_id = next_memory_ctrl_id + 1
# Enable SST Statistics Outputs for this simulation
sst.setStatisticLoadLevel(4)
sst.enableAllStatisticsForAllComponents({"type": "sst.AccumulatorStatistic"})
sst.enableAllStatisticsForComponentType("macsimComponent.macsimComponent")
sst.enableAllStatisticsForComponentType("memHierarchy.Cache")
sst.enableAllStatisticsForComponentType("memHierarchy.MemController")
sst.setStatisticOutput("sst.statOutputCSV")
sst.setStatisticOutputOptions({
"filepath": "sst-ring.stat.csv",
"separator": ",",
"outputtopheader": 1,
"outputsimtime": 1,
"outputrank": 1
})
print "Completed configuring ring topology"
BusMemContentLink = sst.Link("bus_memcontent")
BusMemContentLink.connect((memcontentbus, "low_network_0", busLat),
(comp_controller0, "contentLink", busLat))
#memMemContentLink = sst.Link("memContent_link")
#memMemContentLink.connect((comp_controller0, "contentLink", g_params["clockCycle"]), (ariel, "linkMemContent",g_params["clockCycle"]));
comp_controller0.enableAllStatistics()
comp_memhBridge.enableAllStatistics()
comp_dimm0.enableAllStatistics()
l3.enableAllStatistics()
sst.setStatisticLoadLevel(7)
sst.setStatisticOutput("sst.statOutputCSV")
sst.setStatisticOutputOptions({
"filepath": statname + ".csv",
"separator": ","
})
##### CPU ####
for core in range(corecount):
ariel = sst.Component("A%d" % core, "ariel.ariel")
## ariel.addParams(AppArgs)
# if core == 2:
# cpu_verbose=1
# else:
# cpu_verbose=0
ariel.addParams({
"clock": cpuFrequency,
"verbose": cpu_verbose,
"maxcorequeue": "512",
