def __init__(self, name="XilinxKcu1500Pgp3", description="Container for application registers", **kwargs): super().__init__(name=name, description=description, **kwargs) # Add axi-pcie-core self.add(pcie.AxiPcieCore( offset=0x00000000, expand=False, )) # Add PGP Core for i in range(8): self.add( pgp.Pgp3AxiL( name=('Lane[%i]' % i), offset=(0x00800000 + i * 0x00010000), numVc=4, # 4 VC per lane writeEn=True, expand=False, ))
def __init__(self, name="Pcie", description="Container for FPGA", dev='/dev/datadev_0', hwEmu=False, **kwargs): super().__init__(name=name, description=description, **kwargs) ###################################################################### # Check if emulating the GUI interface if (hwEmu): # Create emulated hardware interface print("Running in Hardware Emulation Mode:") srp = pyrogue.interfaces.simulation.MemEmulate() else: # Create the stream interface memMap = rogue.hardware.axi.AxiMemMap(dev) ###################################################################### self.add( pcie.AxiPcieCore( memBase=memMap, offset=0x00000000, expand=False, )) for i in range(8): self.add( pgp.Pgp3AxiL( memBase=memMap, name=('Pgp3Mon[%d]' % i), offset=(0x00800000 + i * 0x10000), numVc=16, writeEn=True, expand=False, ))
def __init__(self, name="Top", description="Container for FEB FPGA", dev='/dev/datadev_0', hwType='pcie', ip='10.0.0.1', **kwargs): super().__init__(name=name, description=description, **kwargs) # File writer dataWriter = pr.utilities.fileio.StreamWriter() self.add(dataWriter) ###################################################################### if (hwType == 'hsio-dtm') or (hwType == 'rce-dpm'): # Create the mmap interface rceMap = rogue.hardware.axi.AxiMemMap('/dev/rce_memmap') # Add RCE version device self.add(rceg3.RceVersion( memBase=rceMap, expand=False, )) # Add PGPv3 to the FEB self.add( pgp.Pgp3AxiL( name='Pgp3Mon', memBase=rceMap, offset=0xA0000000, numVc=1, writeEn=True, expand=False, )) if (hwType == 'hsio-dtm'): # Add PGPv2b to the HSIO FPGA self.add( pgp.Pgp2bAxi( name='Pgp2bMon', memBase=rceMap, offset=0xA1000000, expand=False, )) # Connect the SRPv0 to PGPv2b.VC[1] pgp2bVc1 = rogue.hardware.axi.AxiStreamDma( '/dev/axi_stream_dma_0', 1, True) srpV0 = rogue.protocols.srp.SrpV0() pr.streamConnectBiDir(srpV0, pgp2bVc1) if (hwType == 'pcie'): axiMemMap = rogue.hardware.axi.AxiMemMap(dev) self.add( pcie.AxiPcieCore( memBase=axiMemMap, offset=0x00000000, expand=False, )) # for i in range(8): # self.add(pgp.Pgp3AxiL( # memBase = axiMemMap, # name = ('Pgp3Mon[%d]' % i), # offset = (0x00800000 + i*0x10000), # numVc = 16, # writeEn = True, # expand = False, # )) ###################################################################### # Create an empty stream arrays configStream = [None] * 4 dataStream = [None] * 4 ######################################################################################################################## # https://github.com/slaclab/rogue/blob/master/include/rogue/hardware/axi/AxiStreamDma.h # static boost::shared_ptr<rogue::hardware::axi::AxiStreamDma> create (std::string path, uint32_t dest, bool ssiEnable); ######################################################################################################################## ###################################################################### # PGPv3.[VC=0] = FEB SRPv3 Register Access # PGPv3.[VC=1] = RD53[DPORT=0] Streaming ASIC Configuration Interface # PGPv3.[VC=2] = RD53[DPORT=1] Streaming ASIC Configuration Interface # PGPv3.[VC=3] = RD53[DPORT=2] Streaming ASIC Configuration Interface # PGPv3.[VC=4] = RD53[DPORT=3] Streaming ASIC Configuration Interface # PGPv3.[VC=5] = RD53[DPORT=0] Streaming Data Interface # PGPv3.[VC=6] = RD53[DPORT=1] Streaming Data Interface # PGPv3.[VC=7] = RD53[DPORT=2] Streaming Data Interface # PGPv3.[VC=8] = RD53[DPORT=3] Streaming Data Interface ###################################################################### if (hwType == 'simulation'): srpStream = pr.interfaces.simulation.StreamSim(host='localhost', dest=0, uid=12, ssi=True) for i in range(4): configStream[i] = pr.interfaces.simulation.StreamSim( host='localhost', dest=1 + i, uid=12, ssi=True) dataStream[i] = pr.interfaces.simulation.StreamSim( host='localhost', dest=5 + i, uid=12, ssi=True) elif (hwType == 'eth'): rudp = pr.protocols.UdpRssiPack(host=ip, port=8192, packVer=2) srpStream = rudp.application(0) for i in range(4): configStream[i] = rudp.application(1 + i) dataStream[i] = rudp.application(5 + i) else: srpStream = rogue.hardware.axi.AxiStreamDma(dev, 0, True) for i in range(4): configStream[i] = rogue.hardware.axi.AxiStreamDma( dev, 1 + i, True) dataStream[i] = rogue.hardware.axi.AxiStreamDma( dev, 5 + i, True) ###################################################################### # Connect the SRPv3 to PGPv3.VC[0] memMap = rogue.protocols.srp.SrpV3() pr.streamConnectBiDir(memMap, srpStream) for i in range(4): # Add data stream to file as channel [i] to dataStream[i] pr.streamConnect(dataStream[i], dataWriter.getChannel(i)) ###################################################################### # Add devices self.add( axiVer.AxiVersion( name='AxiVersion', memBase=memMap, offset=0x00000000, expand=False, )) self.add( xil.Xadc( name='Xadc', memBase=memMap, offset=0x00010000, expand=False, )) self.add( prom.AxiMicronP30( name='AxiMicronP30', memBase=memMap, offset=0x00020000, hidden=True, # Hidden in GUI because indented for scripting )) self.add( common.SysReg( name='SysReg', description= 'This device contains system level configuration and status registers', memBase=memMap, offset=0x00030000, expand=False, )) self.add( common.Ntc( name='Rd53Ntc', description= 'This device contains the four NTC MAX6682 readout modules', memBase=memMap, offset=0x00040000, expand=False, )) self.add( nxp.Sa56004x( name='BoardTemp', description= 'This device monitors the board temperature and FPGA junction temperature', memBase=memMap, offset=0x00050000, expand=False, )) self.add( linear.Ltc4151( name='BoardPwr', description= 'This device monitors the board power, input voltage and input current', memBase=memMap, offset=0x00050400, senseRes=20.E-3, # Units of Ohms expand=False, )) for i in range(4): self.add( common.RxPhyMon( name=('RxPhyMon[%d]' % i), memBase=memMap, offset=(0x01000000 * (i + 1) + 0x00100000), expand=False, )) self.add( common.Timing( name='Timing', description= 'This device monitors the TLU and timing/trigger emulator', memBase=memMap, offset=0x05000000, expand=False, ))
def __init__(self, name='PgpSemi', description='Pgp Application', numLanes=1, usePgp3=True, **kwargs): super().__init__(name=name, description=description, **kwargs) for i in range(numLanes): if usePgp3: self.add( pgp.Pgp3AxiL( name='Pgp3AxiL_%d' % i, offset=0x10000 * i, writeEn=True, )) else: self.add( pgp.Pgp2bAxi( name='Pgp2bAxi_%d' % i, offset=0x10000 * i, writeEn=True, )) self.add( axi.AxiStreamMonAxiL( name='TxMon_%d' % i, offset=0x12000 * i, )) self.add( axi.AxiStreamMonAxiL( name='RxMon_%d' % i, offset=0x14000 * i, )) for i in range(numLanes): self.add( pr.RemoteVariable( name='rxLinkId_%d' % i, offset=0x40000 + 4 * i, bitSize=32, mode='RO', )) self.add( pr.RemoteVariable( name='txLinkId_%d' % i, offset=0x40010 + 4 * i, bitSize=32, mode='RW', )) self.add( pr.RemoteVariable( name='qpllLock', offset=0x40020, bitSize=4, mode='RO', )) self.add( pr.RemoteVariable( name='qpllReset', offset=0x40024, bitSize=1, bitOffset=0, mode='RW', )) self.add( pr.RemoteVariable( name='txReset', offset=0x40024, bitSize=1, bitOffset=1, mode='RW', )) self.add( pr.RemoteVariable( name='rxReset', offset=0x40024, bitSize=1, bitOffset=2, mode='RW', ))
def __init__(self, name="Hardware", description="Container for PCIe Hardware Registers", numLane=4, version3=False, **kwargs): super().__init__(name=name, description=description, **kwargs) # Add axi-pcie-core self.add( pcie.AxiPcieCore( offset=0x00000000, numDmaLanes=numLane, expand=False, )) # Add PGP Core for i in range(numLane): if (version3): self.add( pgp.Pgp3AxiL( name=(f'PgpMon[{i}]'), offset=(0x00800000 + i * 0x00010000 + 0 * 0x2000), numVc=4, writeEn=True, expand=False, )) else: self.add( pgp.Pgp2bAxi( name=(f'PgpMon[{i}]'), offset=(0x00800000 + i * 0x00010000), writeEn=True, expand=False, )) self.add( axi.AxiStreamMonitoring( name=(f'PgpTxAxisMon[{i}]'), offset=(0x00800000 + i * 0x00010000 + 1 * 0x2000), numberLanes=4, expand=False, )) self.add( axi.AxiStreamMonitoring( name=(f'PgpRxAxisMon[{i}]'), offset=(0x00800000 + i * 0x00010000 + 2 * 0x2000), numberLanes=4, expand=False, )) # Add Timing Core self.add( XilinxKcu1500Pgp.Timing( offset=0x00900000, numLane=numLane, expand=False, ))
################################################################# # Create the mmap interface rceMap = rogue.hardware.axi.AxiMemMap('/dev/rce_memmap') # Add RCE version device base.add(rceg3.RceVersion( memBase = rceMap, expand = False, )) # Add PGPv3 to the FEB base.add(pgp.Pgp3AxiL( name = 'Pgp3Mon', memBase = rceMap, offset = 0xA0000000, numVc = 1, writeEn = True, expand = False, )) # Check for HSIO DTM if ( args.hwType == 'hsio-dtm' ): # Add PGPv2b to the HSIO FPGA base.add(pgp.Pgp2bAxi( name = 'Pgp2bMon', memBase = rceMap, offset = 0xA1000000, expand = False, )) #################################################################
def __init__( self, name="ClinkFeb", description="ClinkFeb Container", serial=[None, None], camType=[None, None], version3=False, # true = PGPv3, false = PGP2b **kwargs): super().__init__(name=name, description=description, **kwargs) # Add devices self.add( axi.AxiVersion( name='AxiVersion', offset=0x00000000, expand=False, )) self.add( prom.CypressS25Fl( name='CypressS25Fl', offset=0x00001000, hidden=True, # Hidden in GUI because indented for scripting )) self.add( nxp.Sa56004x( name='BoardTemp', description= 'This device monitors the board temperature and FPGA junction temperature', offset=0x00002000, expand=False, )) self.add( linear.Ltc4151( name='BoardPwr', description= 'This device monitors the board power, input voltage and input current', offset=0x00002400, senseRes=20.E-3, # Units of Ohms expand=False, )) self.add(xil.Xadc( name='Xadc', offset=0x00003000, expand=False, )) self.add( cl.ClinkTop( offset=0x00100000, serial=serial, camType=camType, expand=False, )) self.add( feb.ClinkTrigCtrl( name='TrigCtrl[0]', description='Channel A trigger control', offset=0x00200000, expand=False, )) self.add( feb.ClinkTrigCtrl( name='TrigCtrl[1]', description='Channel B trigger control', offset=0x00200100, expand=False, )) for i in range(2): if (version3): self.add( pgp.Pgp3AxiL( name=(f'PgpMon[{i}]'), offset=(0x00400000 + i * 0x2000), numVc=4, writeEn=False, expand=False, )) # self.add(axi.AxiStreamMonitoring( # name = (f'PgpTxAxisMon[{i}]'), # offset = (0x00400000 + i*0x4000 + 0x4000), # numberLanes = 4, # expand = False, # )) # self.add(axi.AxiStreamMonitoring( # name = (f'PgpRxAxisMon[{i}]'), # offset = (0x00400000 + i*0x4000 + 0x6000), # numberLanes = 4, # expand = False, # )) else: self.add( pgp.Pgp2bAxi( name=(f'PgpMon[{i}]'), offset=(0x00400000 + i * 0x6000 + 0 * 0x2000), writeEn=False, expand=False, ))
def __init__(self, name="pciServer", description="DMA Loopback Testing", **kwargs): super().__init__(name=name, description=description, **kwargs) # Create PCIE memory mapped interface self.memMap = rogue.hardware.axi.AxiMemMap(args.dev) # Add the PCIe core device to base self.add( pcie.AxiPcieCore( offset=0x00000000, memBase=self.memMap, numDmaLanes=args.numLane, boardType=args.boardType, expand=True, )) # Add PGP Core for lane in range(args.numLane): if (args.version == 4): self.add( pgp.Pgp4AxiL( name=f'Lane[{lane}]', offset=(0x00800000 + lane * 0x00010000), memBase=self.memMap, numVc=args.numVc, writeEn=True, expand=True, )) elif (args.version == 3): self.add( pgp.Pgp3AxiL( name=f'Lane[{lane}]', offset=(0x00800000 + lane * 0x00010000), memBase=self.memMap, numVc=args.numVc, writeEn=True, expand=False, )) else: self.add( pgp.Pgp2bAxi( name=f'Lane[{lane}]', offset=(0x00800000 + lane * 0x00010000 + 0x1000), memBase=self.memMap, expand=False, )) self.add( axi.AxiStreamMonAxiL( name=(f'PgpTxAxisMon[{lane}]'), offset=(0x00800000 + lane * 0x00010000 + 0x3000), numberLanes=args.numVc, memBase=self.memMap, expand=False, )) self.add( axi.AxiStreamMonAxiL( name=(f'PgpRxAxisMon[{lane}]'), offset=(0x00800000 + lane * 0x00010000 + 0x4000), numberLanes=args.numVc, memBase=self.memMap, expand=False, ))
def __init__(self, name="pciServer", description="DMA Loopback Testing", **kwargs): super().__init__(name=name, description=description, **kwargs) # Create PCIE memory mapped interface self.memMap = rogue.hardware.axi.AxiMemMap(args.dev) if (args.swRx or args.swTx): self.dmaStream = [[None for x in range(args.numVc)] for y in range(args.numLane)] self.prbsRx = [[None for x in range(args.numVc)] for y in range(args.numLane)] self.prbsTx = [[None for x in range(args.numVc)] for y in range(args.numLane)] # Add the PCIe core device to base self.add( pcie.AxiPcieCore( offset=0x00000000, memBase=self.memMap, numDmaLanes=args.numLane, boardType=args.boardType, expand=True, )) # Add PGP Core for lane in range(args.numLane): if (args.version == 4): self.add( pgp.Pgp4AxiL( name=f'Lane[{lane}]', offset=(0x00800000 + lane * 0x00010000), memBase=self.memMap, numVc=args.numVc, writeEn=True, expand=True, )) elif (args.version == 3): self.add( pgp.Pgp3AxiL( name=f'Lane[{lane}]', offset=(0x00800000 + lane * 0x00010000), memBase=self.memMap, numVc=args.numVc, writeEn=True, expand=False, )) else: self.add( pgp.Pgp2bAxi( name=f'Lane[{lane}]', offset=(0x00800000 + lane * 0x00010000 + 0x1000), memBase=self.memMap, expand=False, )) self.add( axi.AxiStreamMonAxiL( name=(f'PgpTxAxisMon[{lane}]'), offset=(0x00800000 + lane * 0x00010000 + 0x3000), numberLanes=args.numVc, memBase=self.memMap, expand=False, )) self.add( axi.AxiStreamMonAxiL( name=(f'PgpRxAxisMon[{lane}]'), offset=(0x00800000 + lane * 0x00010000 + 0x4000), numberLanes=args.numVc, memBase=self.memMap, expand=False, )) # Loop through the virtual channels for vc in range(args.numVc): if (args.swRx or args.swTx): self.dmaStream[lane][vc] = rogue.hardware.axi.AxiStreamDma( args.dev, (0x100 * lane) + vc, 1) if (args.swRx): # Connect the SW PRBS Receiver module self.prbsRx[lane][vc] = pr.utilities.prbs.PrbsRx( name=('SwPrbsRx[%d][%d]' % (lane, vc)), width=args.prbsWidth, checkPayload=True, expand=False, ) self.dmaStream[lane][vc] >> self.prbsRx[lane][vc] self.add(self.prbsRx[lane][vc]) if (args.swTx): # Connect the SW PRBS Transmitter module self.prbsTx[lane][vc] = pr.utilities.prbs.PrbsTx( name=('SwPrbsTx[%d][%d]' % (lane, vc)), width=args.prbsWidth, expand=False, ) self.prbsTx[lane][vc] >> self.dmaStream[lane][vc] self.add(self.prbsTx[lane][vc]) @self.command() def EnableAllSwTx(): swTxDevices = root.find(typ=pr.utilities.prbs.PrbsTx) for tx in swTxDevices: tx.txEnable.set(True) @self.command() def DisableAllSwTx(): swTxDevices = root.find(typ=pr.utilities.prbs.PrbsTx) for tx in swTxDevices: tx.txEnable.set(False)