def __init__(self, name='Fpga', description='Fpga Container', **kwargs):
super().__init__(name=name, description=description, **kwargs)
#############
# Add devices
#############
self.add(axi.AxiVersion(offset=0x00000000, ))
self.add(ssi.SsiPrbsTx(offset=0x00040000, ))
self.add(ssi.SsiPrbsRx(offset=0x00050000, ))
self.add(rssi.RssiCore(offset=0x00070000, ))
self.add(udp.UdpEngine(
offset=0x00078000,
numSrv=2,
expand=False,
))
self.add(
ethPhy.TenGigEthReg(
offset=0x80000000,
writeEn=True,
expand=True,
))
def __init__(self,
name='UdpGrp',
description='Container for UdpGrp',
**kwargs):
super().__init__(name=name, description=description, **kwargs)
for i in range(6):
self.add(
smurf.UdpConfig(
name=f'UdpConfig[{i}]',
offset=i * 0x10000 + 0x0000,
expand=False,
))
for i in range(6):
self.add(
udp.UdpEngine(
name=f'UdpEngine[{i}]',
offset=i * 0x10000 + 0x1000,
numClt=2,
expand=False,
))
for i in range(6):
self.add(
rssi.RssiCore(
name=f'RssiClient[{i}]',
offset=i * 0x10000 + 0x2000,
expand=False,
))
def __init__(self, name='Fpga', description='Fpga Container', **kwargs):
super().__init__(name=name, description=description, **kwargs)
#############
# Add devices
#############
self.add(rssi.RssiCore(offset=0xA4010000,
# expand = False,
))
self.add(ssi.SsiPrbsTx(offset=0xA4020000,
# expand = False,
))
self.add(ssi.SsiPrbsRx(offset=0xA4030000,
# expand = False,
))
def __init__(self,
name='Fpga',
fpgaType='',
commType='',
description='Fpga Container',
**kwargs):
super().__init__(name=name, description=description, **kwargs)
#############
# Add devices
#############
self.add(axi.AxiVersion(
offset=0x00000000,
expand=False,
))
if (fpgaType == '7series'):
self.add(xil.Xadc(
offset=0x00010000,
expand=False,
))
if (fpgaType == 'ultrascale'):
self.add(xil.AxiSysMonUltraScale(
offset=0x00020000,
expand=False,
))
self.add(
MbSharedMem(
name='MbSharedMem',
offset=0x00030000,
size=0x10000,
expand=False,
))
self.add(ssi.SsiPrbsTx(
offset=0x00040000,
expand=False,
))
self.add(ssi.SsiPrbsRx(
offset=0x00050000,
expand=False,
))
if (commType == 'eth'):
self.add(rssi.RssiCore(
offset=0x00070000,
expand=False,
))
self.add(
axi.AxiStreamMonitoring(
name='AxisMon',
offset=0x00080000,
numberLanes=2,
expand=False,
))
self.add(
MbSharedMem(
name='TestEmptyMem',
offset=0x80000000,
size=0x80000000,
expand=False,
))
def __init__(self,
name="SysReg",
description="AmcCarrierCore",
rssiNotInterlaved=True,
rssiInterlaved=False,
enableBsa=True,
enableMps=True,
expand=False,
**kwargs):
super().__init__(name=name,
description=description,
expand=expand,
**kwargs)
##############################
# Variables
##############################
self.add(axi.AxiVersion(
offset=0x00000000,
expand=False,
))
self.add(xilinx.AxiSysMonUltraScale(
offset=0x02000000,
expand=False,
))
self.add(IIC(
offset=0x03000000,
expand=False,
))
self.add(DevBoardTiming(
offset=0x04000000,
expand=False,
))
self.add(LocReg(
offset=0x07000000,
expand=False,
))
self.add(
AmcCarrierBsa(
offset=0x08000000,
enableBsa=enableBsa,
expand=False,
))
self.add(
udp.UdpEngineClient(
name="BpUdpCltApp",
offset=0x09000000,
description=
"Backplane UDP Client for Application ASYNC Messaging",
expand=False,
))
self.add(
udp.UdpEngineServer(
name="SwUdpSrv",
offset=0x09000800,
description="Backplane UDP Server: Xilinx XVC",
expand=False,
))
self.add(
udp.UdpEngineServer(
name="BpUdpSrvXvc",
offset=0x09000808,
description=
"Backplane UDP Server: FSBL Legacy SRPv0 register access",
expand=False,
))
self.add(
rssi.RssiCore(
name="SwRssiServer",
offset=0x09010000,
description="Interleaved RSSI server",
expand=False,
))
self.add(AxiFanController(
name="FanController",
offset=0x0A000000,
))
def __init__(self,
name="AmcCarrierCore",
description="AmcCarrierCore",
enablePwrI2C=False,
enableBsa=True,
enableMps=True,
numWaveformBuffers=4,
enableTpgMini=True,
expand=False,
**kwargs):
super().__init__(name=name,
description=description,
expand=expand,
**kwargs)
##############################
# Variables
##############################
self.add(axi.AxiVersion(offset=0x00000000, expand=False))
self.add(xilinx.AxiSysMonUltraScale(offset=0x01000000, expand=False))
self.add(
micron.AxiMicronN25Q(
name="MicronN25Q",
offset=0x2000000,
addrMode=True,
expand=False,
hidden=True,
))
self.add(
microchip.AxiSy56040(offset=0x03000000,
expand=False,
description="\n\
Timing Crossbar: https://confluence.slac.stanford.edu/x/m4H7D \n\
-----------------------------------------------------------------\n\
OutputConfig[0] = 0x0: Connects RTM_TIMING_OUT0 to RTM_TIMING_IN0\n\
OutputConfig[0] = 0x1: Connects RTM_TIMING_OUT0 to FPGA_TIMING_IN\n\
OutputConfig[0] = 0x2: Connects RTM_TIMING_OUT0 to BP_TIMING_IN\n\
OutputConfig[0] = 0x3: Connects RTM_TIMING_OUT0 to RTM_TIMING_IN1\n\
-----------------------------------------------------------------\n\
OutputConfig[1] = 0x0: Connects FPGA_TIMING_OUT to RTM_TIMING_IN0\n\
OutputConfig[1] = 0x1: Connects FPGA_TIMING_OUT to FPGA_TIMING_IN\n\
OutputConfig[1] = 0x2: Connects FPGA_TIMING_OUT to BP_TIMING_IN\n\
OutputConfig[1] = 0x3: Connects FPGA_TIMING_OUT to RTM_TIMING_IN1 \n\
-----------------------------------------------------------------\n\
OutputConfig[2] = 0x0: Connects Backplane DIST0 to RTM_TIMING_IN0\n\
OutputConfig[2] = 0x1: Connects Backplane DIST0 to FPGA_TIMING_IN\n\
OutputConfig[2] = 0x2: Connects Backplane DIST0 to BP_TIMING_IN\n\
OutputConfig[2] = 0x3: Connects Backplane DIST0 to RTM_TIMING_IN1\n\
-----------------------------------------------------------------\n\
OutputConfig[3] = 0x0: Connects Backplane DIST1 to RTM_TIMING_IN0\n\
OutputConfig[3] = 0x1: Connects Backplane DIST1 to FPGA_TIMING_IN\n\
OutputConfig[3] = 0x2: Connects Backplane DIST1 to BP_TIMING_IN\n\
OutputConfig[3] = 0x3: Connects Backplane DIST1 to RTM_TIMING_IN1\n\
-----------------------------------------------------------------\n"
))
# self.add(ti.AxiCdcm6208(
# offset = 0x05000000,
# enabled = False,
# hidden = True,
# expand = False,
# ))
self.add(amcc.AmcCarrierBsi(
offset=0x07000000,
expand=False,
))
self.add(
amcc.AmcCarrierTiming(
offset=0x08000000,
expand=False,
enableTpgMini=enableTpgMini,
))
self.add(
amcc.AmcCarrierBsa(
offset=0x09000000,
enableBsa=enableBsa,
numWaveformBuffers=numWaveformBuffers,
expand=False,
))
self.add(
udp.UdpEngineClient(
name="BpUdpCltApp",
offset=0x0A000000,
description=
"Backplane UDP Client for Application ASYNC Messaging",
expand=False,
))
self.add(
udp.UdpEngineServer(
name="BpUdpSrvXvc",
offset=0x0A000800,
description="Backplane UDP Server: Xilinx XVC",
expand=False,
))
self.add(
udp.UdpEngineServer(
name="BpUdpSrvFsbl",
offset=0x0A000808,
description=
"Backplane UDP Server: FSBL Legacy SRPv0 register access",
expand=False,
))
self.add(
udp.UdpEngineServer(
name="BpUdpSrvRssi[0]",
offset=0x0A000810,
description=
"Backplane UDP Server: Legacy Non-interleaved RSSI for Register access and ASYNC messages",
expand=False,
))
self.add(
udp.UdpEngineServer(
name="BpUdpSrvRssi[1]",
offset=0x0A000818,
description=
"Backplane UDP Server: Legacy Non-interleaved RSSI for bulk data transfer",
expand=False,
))
self.add(
udp.UdpEngineServer(
name="BpUdpSrvRssi[2]",
offset=0x0A000830,
description="Backplane UDP Server: Interleaved RSSI",
expand=False,
))
self.add(
udp.UdpEngineServer(
name="BpUdpSrvApp",
offset=0x0A000820,
description=
"Backplane UDP Server for Application ASYNC Messaging",
expand=False,
))
self.add(
udp.UdpEngineServer(
name="BpUdpSrvTiming",
offset=0x0A000828,
description="Backplane UDP Server for Timing ASYNC Messaging",
expand=False,
))
for i in range(2):
self.add(
rssi.RssiCore(
name=f'SwRssiServer[{i}]',
offset=0x0A010000 + (i * 0x1000),
description="SwRssiServer Server: %i" % (i),
expand=False,
))
self.add(
rssi.RssiCore(
name="SwRssiServer[2]",
offset=0x0A020000,
description="SwRssiServer Server",
expand=False,
))
if (enableMps):
self.add(mps.AppMps(offset=0x0C000000, expand=False))
if (enablePwrI2C):
self.add(intel.EM22xx(offset=0x0D000000, expand=False))
def __init__( self,
name = 'Fpga',
fpgaType = '',
commType = '',
description = 'Fpga Container',
**kwargs):
super().__init__(name=name,description=description, **kwargs)
self.add(axi.AxiVersion(
offset = 0x00000000,
expand = True,
))
if(fpgaType=='7series'):
self.add(xil.Xadc(
offset = 0x00010000,
expand = False,
))
if(fpgaType=='ultrascale'):
self.add(xil.AxiSysMonUltraScale(
offset = 0x00020000,
expand = False,
))
# self.add(MbSharedMem(
# name = 'MbSharedMem',
# offset = 0x00030000,
# size = 0x10000,
# expand = False,
# ))
self.add(ssi.SsiPrbsTx(
offset = 0x00040000,
expand = False,
))
self.add(ssi.SsiPrbsRx(
offset = 0x00050000,
expand = False,
))
if ( commType == 'eth' ):
self.add(rssi.RssiCore(
offset = 0x00070000,
expand = False,
))
# self.add(udp.UdpEngine(
# offset = 0x00078000,
# numSrv = 1,
# expand = False,
# ))
self.add(axi.AxiStreamMonAxiL(
name = 'AxisMon',
offset = 0x00080000,
numberLanes = 2,
expand = False,
))