def __init__(self,
name="Top",
description="Container for XPM",
ipAddr='10.0.1.101',
memBase=0,
fidPrescale=200,
**kwargs):
super().__init__(name=name, description=description, **kwargs)
################################################################################################################
# UDP_SRV_XVC_IDX_C => 2542, -- Xilinx XVC
# UDP_SRV_SRPV0_IDX_C => 8192, -- Legacy SRPv0 register access (still used for remote FPGA reprogramming)
# UDP_SRV_RSSI0_IDX_C => 8193, -- Legacy Non-interleaved RSSI for Register access and ASYNC messages
# UDP_SRV_RSSI1_IDX_C => 8194, -- Legacy Non-interleaved RSSI for bulk data transfer
# UDP_SRV_BP_MGS_IDX_C => 8195, -- Backplane Messaging
# UDP_SRV_TIMING_IDX_C => 8197, -- Timing ASYNC Messaging
# UDP_SRV_RSSI_ILEAVE_IDX_C => 8198); -- Interleaved RSSI
################################################################################################################
# Create SRP/ASYNC_MSG interface
if False:
# UDP only
self.udp = rogue.protocols.udp.Client(ipAddr, 8192, 0)
# Connect the SRPv0 to RAW UDP
self.srp = rogue.protocols.srp.SrpV0()
pyrogue.streamConnectBiDir(self.srp, self.udp)
if True:
self.rudp = pyrogue.protocols.UdpRssiPack(name='rudpReg',
host=ipAddr,
port=8193,
packVer=1,
jumbo=False)
# Connect the SRPv3 to tDest = 0x0
self.srp = rogue.protocols.srp.SrpV3()
pr.streamConnectBiDir(self.srp, self.rudp.application(dest=0x0))
# Create stream interface
self.stream = pr.protocols.UdpRssiPack(name='rudpData',
host=ipAddr,
port=8194,
packVer=1,
jumbo=False)
######################################################################
# Add devices
self.add(
axi.AxiVersion(
memBase=self.srp,
offset=0x00000000,
expand=False,
))
self.add(
xil.AxiSysMonUltraScale(memBase=self.srp,
offset=0x01000000,
expand=False))
self.add(
micron.AxiMicronN25Q(
memBase=self.srp,
name="MicronN25Q",
offset=0x2000000,
addrMode=True,
expand=False,
hidden=True,
))
self.add(microchip.AxiSy56040(
memBase = self.srp,
offset = 0x03000000,
expand = False,
description = "\n\
Timing Crossbar: https://confluence.slac.stanford.edu/x/m4H7D \n\
-----------------------------------------------------------------\n\
OutputConfig[0] = 0x0: Connects RTM_TIMING_OUT0 to RTM_TIMING_IN0\n\
OutputConfig[0] = 0x1: Connects RTM_TIMING_OUT0 to FPGA_TIMING_IN\n\
OutputConfig[0] = 0x2: Connects RTM_TIMING_OUT0 to BP_TIMING_IN\n\
OutputConfig[0] = 0x3: Connects RTM_TIMING_OUT0 to RTM_TIMING_IN1\n\
-----------------------------------------------------------------\n\
OutputConfig[1] = 0x0: Connects FPGA_TIMING_OUT to RTM_TIMING_IN0\n\
OutputConfig[1] = 0x1: Connects FPGA_TIMING_OUT to FPGA_TIMING_IN\n\
OutputConfig[1] = 0x2: Connects FPGA_TIMING_OUT to BP_TIMING_IN\n\
OutputConfig[1] = 0x3: Connects FPGA_TIMING_OUT to RTM_TIMING_IN1 \n\
-----------------------------------------------------------------\n\
OutputConfig[2] = 0x0: Connects Backplane DIST0 to RTM_TIMING_IN0\n\
OutputConfig[2] = 0x1: Connects Backplane DIST0 to FPGA_TIMING_IN\n\
OutputConfig[2] = 0x2: Connects Backplane DIST0 to BP_TIMING_IN\n\
OutputConfig[2] = 0x3: Connects Backplane DIST0 to RTM_TIMING_IN1\n\
-----------------------------------------------------------------\n\
OutputConfig[3] = 0x0: Connects Backplane DIST1 to RTM_TIMING_IN0\n\
OutputConfig[3] = 0x1: Connects Backplane DIST1 to FPGA_TIMING_IN\n\
OutputConfig[3] = 0x2: Connects Backplane DIST1 to BP_TIMING_IN\n\
OutputConfig[3] = 0x3: Connects Backplane DIST1 to RTM_TIMING_IN1\n\
-----------------------------------------------------------------\n"\
))
self.add(
ti.AxiCdcm6208(
memBase=self.srp,
offset=0x05000000,
expand=False,
))
self.add(
xpm.TimingFrameRx(
memBase=self.srp,
name='UsTiming',
offset=0x08000000,
))
self.add(
xpm.TimingFrameRx(
memBase=self.srp,
name='CuTiming',
offset=0x08400000,
))
self.add(
xpm.CuGenerator(
memBase=self.srp,
name='CuGenerator',
offset=0x08800000,
))
for i in range(len(Top.mmcmParms)):
self.add(
xpm.MmcmPhaseLock(
memBase=self.srp,
name=Top.mmcmParms[i][0],
offset=Top.mmcmParms[i][1],
))
hsrParms = [['HSRep0', 0x09000000], ['HSRep1', 0x09010000],
['HSRep2', 0x09020000], ['HSRep3', 0x09030000],
['HSRep4', 0x09040000], ['HSRep5', 0x09050000]]
for i in range(len(hsrParms)):
self.add(
xpm.Ds125br401(
memBase=self.srp,
name=hsrParms[i][0],
offset=hsrParms[i][1],
))
self.amcs = []
for i in range(2):
amc = xpm.MpsSfpAmc(
memBase=self.srp,
name='Amc%d' % i,
offset=0x09000000 + (i + 1) * 0x100000,
)
self.add(amc)
self.amcs.append(amc)
# self.add(timing.GthRxAlignCheck(
self.add(
xpm.GthRxAlignCheck(
memBase=self.srp,
name='UsGthRxAlign',
offset=0x0b000000,
))
# self.add(timing.GthRxAlignCheck(
self.add(
xpm.GthRxAlignCheck(
memBase=self.srp,
name='CuGthRxAlign',
offset=0x0c000000,
))
self.add(
xpm.XpmApp(
memBase=self.srp,
name='XpmApp',
offset=0x80000000,
fidPrescale=fidPrescale,
))
self.add(
AxiLiteRingBuffer(
memBase=self.srp,
name='AxiLiteRingBuffer',
datawidth=16,
offset=0x80010000,
))
self.add(
xpm.XpmSequenceEngine(
memBase=self.srp,
name='SeqEng_0',
offset=0x80020000,
))
# self.add(xpm.CuPhase(
# memBase = self.srp,
# name = 'CuPhase',
# offset = 0x80050000,
# ))
self.add(
xpm.XpmPhase(
memBase=self.srp,
name='CuToScPhase',
offset=0x80050000,
))
def __init__(self,
name='Fpga',
fpgaType='',
commType='',
description='Fpga Container',
**kwargs):
super().__init__(name=name, description=description, **kwargs)
#############
# Add devices
#############
self.add(axi.AxiVersion(
offset=0x00000000,
expand=False,
))
if (fpgaType == '7series'):
self.add(xil.Xadc(
offset=0x00010000,
expand=False,
))
if (fpgaType == 'ultrascale'):
self.add(xil.AxiSysMonUltraScale(
offset=0x00020000,
expand=False,
))
self.add(
MbSharedMem(
name='MbSharedMem',
offset=0x00030000,
size=0x10000,
expand=False,
))
self.add(ssi.SsiPrbsTx(
offset=0x00040000,
expand=False,
))
self.add(ssi.SsiPrbsRx(
offset=0x00050000,
expand=False,
))
if (commType == 'eth'):
self.add(rssi.RssiCore(
offset=0x00070000,
expand=False,
))
self.add(
axi.AxiStreamMonitoring(
name='AxisMon',
offset=0x00080000,
numberLanes=2,
expand=False,
))
self.add(
MbSharedMem(
name='TestEmptyMem',
offset=0x80000000,
size=0x80000000,
expand=False,
))
def __init__(self,
name="SysReg",
description="AmcCarrierCore",
rssiNotInterlaved=True,
rssiInterlaved=False,
enableBsa=True,
enableMps=True,
expand=False,
**kwargs):
super().__init__(name=name,
description=description,
expand=expand,
**kwargs)
##############################
# Variables
##############################
self.add(axi.AxiVersion(
offset=0x00000000,
expand=False,
))
self.add(xilinx.AxiSysMonUltraScale(
offset=0x02000000,
expand=False,
))
self.add(IIC(
offset=0x03000000,
expand=False,
))
self.add(DevBoardTiming(
offset=0x04000000,
expand=False,
))
self.add(LocReg(
offset=0x07000000,
expand=False,
))
self.add(
AmcCarrierBsa(
offset=0x08000000,
enableBsa=enableBsa,
expand=False,
))
self.add(
udp.UdpEngineClient(
name="BpUdpCltApp",
offset=0x09000000,
description=
"Backplane UDP Client for Application ASYNC Messaging",
expand=False,
))
self.add(
udp.UdpEngineServer(
name="SwUdpSrv",
offset=0x09000800,
description="Backplane UDP Server: Xilinx XVC",
expand=False,
))
self.add(
udp.UdpEngineServer(
name="BpUdpSrvXvc",
offset=0x09000808,
description=
"Backplane UDP Server: FSBL Legacy SRPv0 register access",
expand=False,
))
self.add(
rssi.RssiCore(
name="SwRssiServer",
offset=0x09010000,
description="Interleaved RSSI server",
expand=False,
))
self.add(AxiFanController(
name="FanController",
offset=0x0A000000,
))
def __init__(self,
name="AmcCarrierCore",
description="AmcCarrierCore",
enablePwrI2C=False,
enableBsa=True,
enableMps=True,
numWaveformBuffers=4,
enableTpgMini=True,
expand=False,
**kwargs):
super().__init__(name=name,
description=description,
expand=expand,
**kwargs)
##############################
# Variables
##############################
self.add(axi.AxiVersion(offset=0x00000000, expand=False))
self.add(xilinx.AxiSysMonUltraScale(offset=0x01000000, expand=False))
self.add(
micron.AxiMicronN25Q(
name="MicronN25Q",
offset=0x2000000,
addrMode=True,
expand=False,
hidden=True,
))
self.add(
microchip.AxiSy56040(offset=0x03000000,
expand=False,
description="\n\
Timing Crossbar: https://confluence.slac.stanford.edu/x/m4H7D \n\
-----------------------------------------------------------------\n\
OutputConfig[0] = 0x0: Connects RTM_TIMING_OUT0 to RTM_TIMING_IN0\n\
OutputConfig[0] = 0x1: Connects RTM_TIMING_OUT0 to FPGA_TIMING_IN\n\
OutputConfig[0] = 0x2: Connects RTM_TIMING_OUT0 to BP_TIMING_IN\n\
OutputConfig[0] = 0x3: Connects RTM_TIMING_OUT0 to RTM_TIMING_IN1\n\
-----------------------------------------------------------------\n\
OutputConfig[1] = 0x0: Connects FPGA_TIMING_OUT to RTM_TIMING_IN0\n\
OutputConfig[1] = 0x1: Connects FPGA_TIMING_OUT to FPGA_TIMING_IN\n\
OutputConfig[1] = 0x2: Connects FPGA_TIMING_OUT to BP_TIMING_IN\n\
OutputConfig[1] = 0x3: Connects FPGA_TIMING_OUT to RTM_TIMING_IN1 \n\
-----------------------------------------------------------------\n\
OutputConfig[2] = 0x0: Connects Backplane DIST0 to RTM_TIMING_IN0\n\
OutputConfig[2] = 0x1: Connects Backplane DIST0 to FPGA_TIMING_IN\n\
OutputConfig[2] = 0x2: Connects Backplane DIST0 to BP_TIMING_IN\n\
OutputConfig[2] = 0x3: Connects Backplane DIST0 to RTM_TIMING_IN1\n\
-----------------------------------------------------------------\n\
OutputConfig[3] = 0x0: Connects Backplane DIST1 to RTM_TIMING_IN0\n\
OutputConfig[3] = 0x1: Connects Backplane DIST1 to FPGA_TIMING_IN\n\
OutputConfig[3] = 0x2: Connects Backplane DIST1 to BP_TIMING_IN\n\
OutputConfig[3] = 0x3: Connects Backplane DIST1 to RTM_TIMING_IN1\n\
-----------------------------------------------------------------\n"
))
# self.add(ti.AxiCdcm6208(
# offset = 0x05000000,
# enabled = False,
# hidden = True,
# expand = False,
# ))
self.add(amcc.AmcCarrierBsi(
offset=0x07000000,
expand=False,
))
self.add(
amcc.AmcCarrierTiming(
offset=0x08000000,
expand=False,
enableTpgMini=enableTpgMini,
))
self.add(
amcc.AmcCarrierBsa(
offset=0x09000000,
enableBsa=enableBsa,
numWaveformBuffers=numWaveformBuffers,
expand=False,
))
self.add(
udp.UdpEngineClient(
name="BpUdpCltApp",
offset=0x0A000000,
description=
"Backplane UDP Client for Application ASYNC Messaging",
expand=False,
))
self.add(
udp.UdpEngineServer(
name="BpUdpSrvXvc",
offset=0x0A000800,
description="Backplane UDP Server: Xilinx XVC",
expand=False,
))
self.add(
udp.UdpEngineServer(
name="BpUdpSrvFsbl",
offset=0x0A000808,
description=
"Backplane UDP Server: FSBL Legacy SRPv0 register access",
expand=False,
))
self.add(
udp.UdpEngineServer(
name="BpUdpSrvRssi[0]",
offset=0x0A000810,
description=
"Backplane UDP Server: Legacy Non-interleaved RSSI for Register access and ASYNC messages",
expand=False,
))
self.add(
udp.UdpEngineServer(
name="BpUdpSrvRssi[1]",
offset=0x0A000818,
description=
"Backplane UDP Server: Legacy Non-interleaved RSSI for bulk data transfer",
expand=False,
))
self.add(
udp.UdpEngineServer(
name="BpUdpSrvRssi[2]",
offset=0x0A000830,
description="Backplane UDP Server: Interleaved RSSI",
expand=False,
))
self.add(
udp.UdpEngineServer(
name="BpUdpSrvApp",
offset=0x0A000820,
description=
"Backplane UDP Server for Application ASYNC Messaging",
expand=False,
))
self.add(
udp.UdpEngineServer(
name="BpUdpSrvTiming",
offset=0x0A000828,
description="Backplane UDP Server for Timing ASYNC Messaging",
expand=False,
))
for i in range(2):
self.add(
rssi.RssiCore(
name=f'SwRssiServer[{i}]',
offset=0x0A010000 + (i * 0x1000),
description="SwRssiServer Server: %i" % (i),
expand=False,
))
self.add(
rssi.RssiCore(
name="SwRssiServer[2]",
offset=0x0A020000,
description="SwRssiServer Server",
expand=False,
))
if (enableMps):
self.add(mps.AppMps(offset=0x0C000000, expand=False))
if (enablePwrI2C):
self.add(intel.EM22xx(offset=0x0D000000, expand=False))
def __init__( self,
name = 'Fpga',
fpgaType = '',
commType = '',
description = 'Fpga Container',
**kwargs):
super().__init__(name=name,description=description, **kwargs)
self.add(axi.AxiVersion(
offset = 0x00000000,
expand = True,
))
if(fpgaType=='7series'):
self.add(xil.Xadc(
offset = 0x00010000,
expand = False,
))
if(fpgaType=='ultrascale'):
self.add(xil.AxiSysMonUltraScale(
offset = 0x00020000,
expand = False,
))
# self.add(MbSharedMem(
# name = 'MbSharedMem',
# offset = 0x00030000,
# size = 0x10000,
# expand = False,
# ))
self.add(ssi.SsiPrbsTx(
offset = 0x00040000,
expand = False,
))
self.add(ssi.SsiPrbsRx(
offset = 0x00050000,
expand = False,
))
if ( commType == 'eth' ):
self.add(rssi.RssiCore(
offset = 0x00070000,
expand = False,
))
# self.add(udp.UdpEngine(
# offset = 0x00078000,
# numSrv = 1,
# expand = False,
# ))
self.add(axi.AxiStreamMonAxiL(
name = 'AxisMon',
offset = 0x00080000,
numberLanes = 2,
expand = False,
))
def __init__(
self,
name='Core',
description='Container for Atlas Atca Link Agg Core registers',
frontPanelI2C=False,
**kwargs):
super().__init__(name=name, description=description, **kwargs)
# self.add(MyAxiVersion(
self.add(
axi.AxiVersion(
name='AxiVersion',
offset=0x00000000,
expand=False,
))
self.add(
xil.AxiSysMonUltraScale(
name='SysMon',
offset=0x00001000,
expand=False,
))
self.add(
prom.AxiMicronN25Q(
name='AxiMicronN25Q',
offset=0x00002000,
addrMode=True, # True = 32-bit Address Mode
hidden=True, # Hidden in GUI because indented for scripting
))
self.add(
AtlasAtcaLinkAgg.Bsi(
name='Bsi',
offset=0x00003000,
expand=False,
))
if frontPanelI2C:
self.add(
nxp.Pca9506(
name='Pca9506',
offset=0x0000A000,
expand=False,
pollInterval=5,
))
for i in range(4):
self.add(
pr.LinkVariable(
name=f'SfpPresent[{i}]',
mode='RO',
linkedGet=lambda i=i:
(~int(self.Pca9506.IP[1].value()) >> (i + 0)) & 0x1,
dependencies=[self.Pca9506.IP[1]],
hidden=True,
))
self.add(
xceiver.Sff8472(
name=f'Sfp[{i}]',
offset=0x00004000 + i * 0x00001000,
expand=False,
enableDeps=[self.SfpPresent[i]],
))
for i in range(2):
self.add(
pr.LinkVariable(
name=f'QsfpPresent[{i}]',
mode='RO',
linkedGet=lambda i=i:
(~int(self.Pca9506.IP[1].value()) >> (i + 4)) & 0x1,
dependencies=[self.Pca9506.IP[1]],
hidden=True,
))
self.add(
xceiver.Sff8472(
name=f'Qsfp[{i}]',
offset=0x00008000 + i * 0x00001000,
expand=False,
enableDeps=[self.QsfpPresent[i]],
))
self.add(ti.Lmk61e2(
name='Lmk',
offset=0x0000B000,
expand=False,
))
self.add(
silabs.Si5345Lite(
name='Pll',
description='This device contains Jitter cleaner PLL',
offset=0x00010000,
expand=False,
))
def __init__(self,
name="Top",
description="Container for XPM",
memBase=0,
**kwargs):
super().__init__(name=name, description=description, **kwargs)
######################################################################
# Add devices
self.add(
axi.AxiVersion(
memBase=memBase,
offset=0x00000000,
expand=False,
))
self.add(
xil.AxiSysMonUltraScale(memBase=memBase,
offset=0x01000000,
expand=False))
self.add(
micron.AxiMicronN25Q(
memBase=memBase,
name="MicronN25Q",
offset=0x2000000,
addrMode=True,
expand=False,
hidden=True,
))
self.add(microchip.AxiSy56040(
memBase = memBase,
offset = 0x03000000,
expand = False,
description = "\n\
Timing Crossbar: https://confluence.slac.stanford.edu/x/m4H7D \n\
-----------------------------------------------------------------\n\
OutputConfig[0] = 0x0: Connects RTM_TIMING_OUT0 to RTM_TIMING_IN0\n\
OutputConfig[0] = 0x1: Connects RTM_TIMING_OUT0 to FPGA_TIMING_IN\n\
OutputConfig[0] = 0x2: Connects RTM_TIMING_OUT0 to BP_TIMING_IN\n\
OutputConfig[0] = 0x3: Connects RTM_TIMING_OUT0 to RTM_TIMING_IN1\n\
-----------------------------------------------------------------\n\
OutputConfig[1] = 0x0: Connects FPGA_TIMING_OUT to RTM_TIMING_IN0\n\
OutputConfig[1] = 0x1: Connects FPGA_TIMING_OUT to FPGA_TIMING_IN\n\
OutputConfig[1] = 0x2: Connects FPGA_TIMING_OUT to BP_TIMING_IN\n\
OutputConfig[1] = 0x3: Connects FPGA_TIMING_OUT to RTM_TIMING_IN1 \n\
-----------------------------------------------------------------\n\
OutputConfig[2] = 0x0: Connects Backplane DIST0 to RTM_TIMING_IN0\n\
OutputConfig[2] = 0x1: Connects Backplane DIST0 to FPGA_TIMING_IN\n\
OutputConfig[2] = 0x2: Connects Backplane DIST0 to BP_TIMING_IN\n\
OutputConfig[2] = 0x3: Connects Backplane DIST0 to RTM_TIMING_IN1\n\
-----------------------------------------------------------------\n\
OutputConfig[3] = 0x0: Connects Backplane DIST1 to RTM_TIMING_IN0\n\
OutputConfig[3] = 0x1: Connects Backplane DIST1 to FPGA_TIMING_IN\n\
OutputConfig[3] = 0x2: Connects Backplane DIST1 to BP_TIMING_IN\n\
OutputConfig[3] = 0x3: Connects Backplane DIST1 to RTM_TIMING_IN1\n\
-----------------------------------------------------------------\n"\
))
self.add(
ti.AxiCdcm6208(
memBase=memBase,
offset=0x05000000,
expand=False,
))
self.add(
xpm.TimingFrameRx(
memBase=memBase,
name='UsTiming',
offset=0x08000000,
))
self.add(
xpm.TimingFrameRx(
memBase=memBase,
name='CuTiming',
offset=0x08400000,
))
self.add(
xpm.CuGenerator(
memBase=memBase,
name='CuGenerator',
offset=0x08800000,
))
for i in range(len(Top.mmcmParms)):
self.add(
xpm.MmcmPhaseLock(
memBase=memBase,
name=Top.mmcmParms[i][0],
offset=Top.mmcmParms[i][1],
))
hsrParms = [['HSRep0', 0x09000000], ['HSRep1', 0x09010000],
['HSRep2', 0x09020000], ['HSRep3', 0x09030000],
['HSRep4', 0x09040000], ['HSRep5', 0x09050000]]
for i in range(len(hsrParms)):
self.add(
xpm.Ds125br401(
memBase=memBase,
name=hsrParms[i][0],
offset=hsrParms[i][1],
))
self.amcs = []
for i in range(2):
amc = xpm.MpsSfpAmc(
memBase=memBase,
name='Amc%d' % i,
offset=0x09000000 + (i + 1) * 0x100000,
)
self.add(amc)
self.amcs.append(amc)
# self.add(timing.GthRxAlignCheck(
self.add(
xpm.GthRxAlignCheck(
memBase=memBase,
name='UsGthRxAlign',
offset=0x0b000000,
))
# self.add(timing.GthRxAlignCheck(
self.add(
xpm.GthRxAlignCheck(
memBase=memBase,
name='CuGthRxAlign',
offset=0x0c000000,
))
self.add(
xpm.XpmApp(
memBase=memBase,
name='XpmApp',
offset=0x80000000,
))
self.add(
AxiLiteRingBuffer(
memBase=memBase,
name='AxiLiteRingBuffer',
datawidth=16,
offset=0x80010000,
))
self.add(
xpm.XpmSequenceEngine(
memBase=memBase,
name='SeqEng_0',
offset=0x80020000,
))
# self.add(xpm.CuPhase(
# memBase = memBase,
# name = 'CuPhase',
# offset = 0x80050000,
# ))
self.add(
xpm.XpmPhase(
memBase=memBase,
name='CuToScPhase',
offset=0x80050000,
))