def output_selector_actor(fimp_instance, max_output=glic.IO,
default_name='sylva_output_selector'):
control_ports, control_port_range \
= get_control_ports('control_input', max_output, fimp_instance)
data_ports = [sdf.port(name='_'.join([p.name, str(fimp_instance.index)]), type=p.type)
for p in fimp_instance.actors[0].output_ports]
data_port_range = xrange(len(data_ports))
input_ports = control_ports + data_ports
output_ports = []
for a in fimp_instance.actors:
for p in a.output_ports:
output_ports.append(sdf.port(name='_'.join([p.name, str(a.index), str(p.index)]), type=p.type))
output_ports[-1].actor_index = a.index
name = default_name + '_' + str(fimp_instance.index)
base_actor = sdf.actor(name=name, input_ports=input_ports, output_ports=output_ports)
result = sdf.actor(name=name, input_ports=input_ports, output_ports=output_ports, base_actor=base_actor)
result.control_port_range = control_port_range
result.data_port_range = data_port_range
return result
def fimp_control_actor(controls,
fimp_instance,
max_output=glic.IO,
default_name='sylva_fimp_control',
fimp_enable_signal_name='en',
input=glic.INPUT,
output=glic.OUTPUT,
inout=glic.IO,
computation=glic.COMPUTATION,
idle=glic.IDLE):
input_ports, __ \
= get_control_ports('control_input', max_output, fimp_instance)
output_ports = [
sdf.port(name=fimp_enable_signal_name, index=0, type=std_logic)
]
name = '_'.join([default_name, str(fimp_instance.index)])
base_actor = sdf.actor(name=name,
input_ports=input_ports,
output_ports=output_ports)
return sdf.actor(name=name,
input_ports=input_ports,
output_ports=output_ports,
base_actor=base_actor)
def actor_fsm_actor(control,
sample_interval,
max_output=glic.IO,
default_name='sylva_actor_control_fsm'):
current_cycle_port = sdf.port(name='current_cycle',
index=0,
type=integer_DataTokenType(sample_interval))
control_port = sdf.port(name='control_output',
index=0,
type=integer_DataTokenType(max_output))
input_ports = [current_cycle_port]
output_ports = [control_port]
name = default_name + '_' + str(control.name)
base_actor = sdf.actor(name=name,
input_ports=input_ports,
output_ports=output_ports)
result = sdf.actor(name=name,
input_ports=input_ports,
output_ports=output_ports,
base_actor=base_actor)
result.control = control
result.control_port = control_port
result.current_cycle_port = current_cycle_port
return result
def create_actors(lib, model):
all_actors = []
for block_item in model.system.blocks:
if 'SourceBlock' in block_item.keys():
all_actors.append(sdf.actor())
func_path = block_item['SourceBlock']
func_name = func_path.split('/')[-1]
lib_name = ''.join(func_path.split('/')[:-1])
all_actors[-1].name = func_name
# only use the first match
source_block = [value for key, value in lib.items()
if key == func_path]
if len(source_block) == 0:
raise Exception('Function %s is not in library %s.'
% (func_name, lib_name))
source_block = source_block[0]
all_actors[-1].input_ports \
= [create_port(source_block['input_ports'][i], i)
for i in source_block['input_ports'].keys()]
all_actors[-1].output_ports \
= [create_port(source_block['output_ports'][i], i)
for i in source_block['output_ports'].keys()]
return all_actors
def create_actors(lib, model):
all_actors = []
for block_item in model.system.blocks:
if 'SourceBlock' in block_item.keys():
all_actors.append(sdf.actor())
func_path = block_item['SourceBlock']
func_name = func_path.split('/')[-1]
lib_name = ''.join(func_path.split('/')[:-1])
all_actors[-1].name = func_name
# only use the first match
source_block = [
value for key, value in lib.items() if key == func_path
]
if len(source_block) == 0:
raise Exception('Function %s is not in library %s.' %
(func_name, lib_name))
source_block = source_block[0]
all_actors[-1].input_ports \
= [create_port(source_block['input_ports'][i], i)
for i in source_block['input_ports'].keys()]
all_actors[-1].output_ports \
= [create_port(source_block['output_ports'][i], i)
for i in source_block['output_ports'].keys()]
return all_actors
def fimp_actor(fimp_instance, fimp_enable_signal_name='en'):
name = fimp_instance.actors[0].base_actor.name
index = fimp_instance.index
data_input_ports = fimp_instance.actors[0].base_actor.input_ports
en_port = sdf.port(name=fimp_enable_signal_name, index=0, type=std_logic)
input_ports = data_input_ports + [en_port]
output_ports = fimp_instance.actors[0].base_actor.output_ports
base_actor = sdf.actor(name=name, input_ports=input_ports, output_ports=output_ports)
result = sdf.actor(name=name, input_ports=input_ports, output_ports=output_ports, base_actor=base_actor,
index=fimp_instance.index)
result.en_port = en_port
result.fimp_type = fimp_instance.type
return result
def counter_actor(fimp_instance, sample_interval, default_name='sylva_counter'):
current_cycle_port = sdf.port(
name='current_cycle',
type=integer_DataTokenType(sample_interval))
output_ports = [current_cycle_port]
name = '_'.join([default_name, str(sample_interval)])
base_actor = sdf.actor(name=name, output_ports=output_ports)
result = sdf.actor(name=name,
output_ports=output_ports, base_actor=base_actor)
result.current_cycle_port = current_cycle_port
result.max_output = sample_interval
return result
def fimp_control_actor(controls, fimp_instance,
max_output=glic.IO, default_name='sylva_fimp_control',
fimp_enable_signal_name='en',
input=glic.INPUT,
output=glic.OUTPUT,
inout=glic.IO,
computation=glic.COMPUTATION,
idle=glic.IDLE):
input_ports, __ \
= get_control_ports('control_input', max_output, fimp_instance)
output_ports = [sdf.port(name=fimp_enable_signal_name, index=0,
type=std_logic)]
name = '_'.join([default_name, str(fimp_instance.index)])
base_actor = sdf.actor(name=name, input_ports=input_ports, output_ports=output_ports)
return sdf.actor(name=name, input_ports=input_ports, output_ports=output_ports, base_actor=base_actor)
def actor_fsm_actor(control, sample_interval, max_output=glic.IO,
default_name='sylva_actor_control_fsm'):
current_cycle_port = sdf.port(name='current_cycle', index=0, type=integer_DataTokenType(sample_interval))
control_port = sdf.port(name='control_output', index=0, type=integer_DataTokenType(max_output))
input_ports = [current_cycle_port]
output_ports = [control_port]
name = default_name + '_' + str(control.name)
base_actor = sdf.actor(name=name, input_ports=input_ports, output_ports=output_ports)
result = sdf.actor(name=name, input_ports=input_ports, output_ports=output_ports, base_actor=base_actor)
result.control = control
result.control_port = control_port
result.current_cycle_port = current_cycle_port
return result
def counter_actor(fimp_instance,
sample_interval,
default_name='sylva_counter'):
current_cycle_port = sdf.port(name='current_cycle',
type=integer_DataTokenType(sample_interval))
output_ports = [current_cycle_port]
name = '_'.join([default_name, str(sample_interval)])
base_actor = sdf.actor(name=name, output_ports=output_ports)
result = sdf.actor(name=name,
output_ports=output_ports,
base_actor=base_actor)
result.current_cycle_port = current_cycle_port
result.max_output = sample_interval
return result
def fimp_actor(fimp_instance, fimp_enable_signal_name='en'):
name = fimp_instance.actors[0].base_actor.name
index = fimp_instance.index
data_input_ports = fimp_instance.actors[0].base_actor.input_ports
en_port = sdf.port(name=fimp_enable_signal_name, index=0, type=std_logic)
input_ports = data_input_ports + [en_port]
output_ports = fimp_instance.actors[0].base_actor.output_ports
base_actor = sdf.actor(name=name,
input_ports=input_ports,
output_ports=output_ports)
result = sdf.actor(name=name,
input_ports=input_ports,
output_ports=output_ports,
base_actor=base_actor,
index=fimp_instance.index)
result.en_port = en_port
result.fimp_type = fimp_instance.type
return result
def output_selector_actor(fimp_instance,
max_output=glic.IO,
default_name='sylva_output_selector'):
control_ports, control_port_range \
= get_control_ports('control_input', max_output, fimp_instance)
data_ports = [
sdf.port(name='_'.join([p.name, str(fimp_instance.index)]),
type=p.type) for p in fimp_instance.actors[0].output_ports
]
data_port_range = xrange(len(data_ports))
input_ports = control_ports + data_ports
output_ports = []
for a in fimp_instance.actors:
for p in a.output_ports:
output_ports.append(
sdf.port(name='_'.join([p.name,
str(a.index),
str(p.index)]),
type=p.type))
output_ports[-1].actor_index = a.index
name = default_name + '_' + str(fimp_instance.index)
base_actor = sdf.actor(name=name,
input_ports=input_ports,
output_ports=output_ports)
result = sdf.actor(name=name,
input_ports=input_ports,
output_ports=output_ports,
base_actor=base_actor)
result.control_port_range = control_port_range
result.data_port_range = data_port_range
return result
def buffer_actors(fimp_instance,
default_name='sylva_output_buffer',
read_write_signal='wr'):
fimp_index = str(fimp_instance.index)
extra_buffer = fimp_instance.extra_buffer == 1
result = []
if extra_buffer == True:
# each actor has its own output buffers
for actor in fimp_instance.actors:
result.append([])
actor_index = actor.index
# each output port has one output buffer
for port in actor.output_ports:
name = '_'.join([default_name, str(fimp_index), str(actor_index), str(port.index)])
wr_port = sdf.port(name='_'.join([read_write_signal, str(actor.index), str(port.index)]),
index=0, type=std_logic)
write_address_port = sdf.port(
name='_'.join(['write_address', str(actor_index), str(port.index)]),
type=integer_DataTokenType(port.count))
read_address_port = sdf.port(
name='_'.join(['read_address', str(fimp_instance.index), str(actor_index), str(port.index)]),
type=integer_DataTokenType(port.count))
data_input_port = sdf.port(
name='_'.join([port.name]),
type=port.type)
data_output_port = sdf.port(
name='_'.join([port.name, str(actor.index)]),
type=port.type)
input_ports = [wr_port, write_address_port, read_address_port, data_input_port]
output_ports = [data_output_port]
port.top_port = data_output_port
base_actor = sdf.actor(name=name, input_ports=input_ports, output_ports=output_ports)
one_buffer = sdf.actor(name=name, input_ports=input_ports, output_ports=output_ports,
base_actor=base_actor)
one_buffer.buffer_size = port.count
one_buffer.wr_port = wr_port
one_buffer.write_address_port = write_address_port
one_buffer.read_address_port = read_address_port
one_buffer.data_input_port = data_input_port
one_buffer.data_output_port = data_output_port
result[-1].append(one_buffer)
else: # extra_buffer = False
actor_count = len(fimp_instance.actors)
for port in fimp_instance.actors[0].output_ports:
name = '_'.join([default_name, str(fimp_index), 'shared', str(port.index)])
wr_port = sdf.port(name='_'.join([read_write_signal, 'shared', str(port.index)]),
index=0, type=std_logic)
write_address_port = sdf.port(
name='_'.join(['write_address', 'shared', str(port.index)]),
type=integer_DataTokenType(port.count * actor_count))
read_address_port = sdf.port(
name='_'.join(['read_address', str(fimp_instance.index), 'shared', str(port.index)]),
type=integer_DataTokenType(port.count * actor_count))
data_input_port = sdf.port(
name='_'.join([port.name]),
type=port.type)
data_output_port = sdf.port(
name='_'.join([port.name, 'shared']),
type=port.type)
input_ports = [wr_port, write_address_port, read_address_port, data_input_port]
output_ports = [data_output_port]
for a in fimp_instance.actors:
for p in a.output_ports:
if p.name == port.name:
p.top_port = data_output_port
base_actor = sdf.actor(name=name, input_ports=input_ports, output_ports=output_ports)
one_buffer = sdf.actor(name=name, input_ports=input_ports, output_ports=output_ports,
base_actor=base_actor)
one_buffer.buffer_size = port.count * len(fimp_instance.actors)
one_buffer.wr_port = wr_port
one_buffer.write_address_port = write_address_port
one_buffer.read_address_port = read_address_port
one_buffer.data_input_port = data_input_port
one_buffer.data_output_port = data_output_port
result.append(one_buffer)
return result
def buffer_control_actor(controls, fimp_instance, max_cycle,
max_output=glic.IO,
default_name='sylva_buffer_control',
read_write_signal='wr', extra_buffer=True):
control_ports, control_port_range = \
get_control_ports('control_input', max_output, fimp_instance)
current_cycle_port = sdf.port(name='current_cycle', index=0, type=integer_DataTokenType(max_cycle))
wr_ports = [sdf.port(name='_'.join([read_write_signal, str(actor.index)]), index=i, type=std_logic)
for i, actor in enumerate(fimp_instance.actors)]
address_ports = []
__, cycles_per_data_token = output_data_structure(fimp_instance.actors[0])
if extra_buffer == True:
# each actor has its own output buffers
for actor in fimp_instance.actors:
address_ports.append([])
# each output port has one output buffer
for port_index, port in enumerate(actor.output_ports):
address_ports[-1].append(
sdf.port(name='_'.join(['write_address', str(actor.index), str(port.index)]),
type=integer_DataTokenType(port.count)))
address_ports[-1][-1].actions = [
(actor.output_start + token_index * cycles_per_data_token[port_index], token_index)
for token_index in xrange(port.count)]
else:
actor_count = len(fimp_instance.actors)
# all output ports of all actors share one output buffer
for port_index, port in enumerate(fimp_instance.actors[0].output_ports):
address_ports.append(
sdf.port(name='_'.join(['write_address', 'shared', str(port.index)]),
type=integer_DataTokenType(port.count * actor_count)))
address_ports[-1].actions = []
token_index = 0
for actor_index, actor in enumerate(fimp_instance.actors):
for __ in xrange(port.count):
action = (actor.output_start + token_index * cycles_per_data_token[port_index],
token_index)
token_index += 1
address_ports[-1].actions.append(action)
input_ports = control_ports + [current_cycle_port]
output_ports = wr_ports + address_ports
name = '_'.join([default_name, str(fimp_instance.index)])
base_actor = sdf.actor(
name=name,
input_ports=input_ports,
output_ports=output_ports)
result = sdf.actor(
name=name,
input_ports=input_ports,
output_ports=output_ports,
base_actor=base_actor)
result.control_ports = control_ports
result.current_cycle_port = current_cycle_port
result.wr_ports = wr_ports
result.address_ports = address_ports
return result
def input_selector_actor(fimp_instance,
sample_interval,
max_output=glic.IO,
default_name='sylva_input_selector'):
input_ports = []
output_ports = []
name = default_name + '_' + str(fimp_instance.index)
control_ports, control_port_range \
= get_control_ports('control_input', max_output, fimp_instance)
data_input_ports = []
for a in fimp_instance.actors:
for p in a.input_ports:
data_input_port_name = '_'.join(
[p.name, str(a.index), str(p.index)])
data_input_port = sdf.port(name=data_input_port_name, type=p.type)
data_input_port.actor = a
p.top_port = data_input_port
data_input_ports.append(data_input_port)
current_cycle_port = sdf.port(name='current_cycle',
index=0,
type=integer_DataTokenType(sample_interval))
data_output_ports = [
sdf.port(name='_'.join([p.name, str(fimp_instance.index)]),
type=p.type) for p in fimp_instance.actors[0].input_ports
]
read_address_ports = {}
# assume actors are sorted based on their start time
# increasing
for a in fimp_instance.actors:
input_start_time = a.start
input_end_time = a.input_end
for p in a.previous:
cycles_step = output_data_structure(
p.src_actor)[1][p.src_port.index]
source_fimp = p.src_actor.fimp
source_actor = p.src_actor
source_port = p.src_port
extra_buffer = p.src_actor.fimp.extra_buffer == 1
source_actor_count = len(p.src_actor.fimp.actors)
if extra_buffer == True:
addres_port_type = integer_DataTokenType(source_port.count)
address_port_name = '_'.join([
'read_address',
str(source_fimp.index),
str(source_actor.index),
str(source_port.index)
])
else:
addres_port_type = \
integer_DataTokenType(source_port.count * source_actor_count)
address_port_name = '_'.join([
'read_address',
str(source_fimp.index), 'shared',
str(source_port.index)
])
if address_port_name not in read_address_ports.keys():
address_port = sdf.port(name=address_port_name,
type=addres_port_type)
address_port.extra_buffer = extra_buffer
address_port.actions = []
address_port.source_fimp = source_fimp
address_port.source_port = source_port
if extra_buffer == True:
address_port.source_actor = source_actor
read_address_ports[address_port_name] = address_port
actions = read_address_ports[address_port_name].actions
previous_actions = len(actions)
if extra_buffer == True:
address_offset = previous_actions * p.dest_port.count
actions += [
AddressPortAction(cycle=input_start_time +
token_index * cycles_step,
address=address_offset + token_index)
for token_index in xrange(p.dest_port.count)
]
else:
actor_index = p.src_actor.abb.fimp.actors.index(p.src_actor)
address_offset = actor_index * p.src_port.count + previous_actions * p.dest_port.count
actions += [
AddressPortAction(cycle=input_start_time +
token_index * cycles_step,
address=address_offset + token_index)
for token_index in xrange(p.dest_port.count)
]
read_address_ports = read_address_ports.values()
input_ports = control_ports + data_input_ports + [current_cycle_port]
output_ports = data_output_ports + read_address_ports
base_actor = sdf.actor(name=name,
input_ports=input_ports,
output_ports=output_ports)
result = sdf.actor(name=name,
input_ports=input_ports,
output_ports=output_ports,
base_actor=base_actor)
result.control_ports = control_ports
result.data_input_ports = data_input_ports
result.data_output_ports = data_output_ports
result.read_address_ports = read_address_ports
result.current_cycle_port = current_cycle_port
result.control_map = [
ControlMap(
output_port=data_output_port,
conditions=[
PortMapCondition(
control_port=c,
valid_values=[glic.INPUT, glic.IO],
input_port=data_input_ports[j +
i * len(data_output_ports)])
for i, c in enumerate(control_ports)
for j, __ in enumerate(data_output_ports)
]) for data_output_port in data_output_ports
]
return result
def input_selector_actor(fimp_instance, sample_interval, max_output=glic.IO, default_name='sylva_input_selector'):
input_ports = []
output_ports = []
name = default_name + '_' + str(fimp_instance.index)
control_ports, control_port_range \
= get_control_ports('control_input', max_output, fimp_instance)
data_input_ports = []
for a in fimp_instance.actors:
for p in a.input_ports:
data_input_port_name = '_'.join([p.name, str(a.index), str(p.index)])
data_input_port = sdf.port(name=data_input_port_name, type=p.type)
data_input_port.actor = a
p.top_port = data_input_port
data_input_ports.append(data_input_port)
current_cycle_port = sdf.port(
name='current_cycle', index=0, type=integer_DataTokenType(sample_interval))
data_output_ports = [sdf.port(name='_'.join([p.name, str(fimp_instance.index)]), type=p.type)
for p in fimp_instance.actors[0].input_ports]
read_address_ports = {}
# assume actors are sorted based on their start time
# increasing
for a in fimp_instance.actors:
input_start_time = a.start
input_end_time = a.input_end
for p in a.previous:
cycles_step = output_data_structure(p.src_actor)[1][p.src_port.index]
source_fimp = p.src_actor.fimp
source_actor = p.src_actor
source_port = p.src_port
extra_buffer = p.src_actor.fimp.extra_buffer == 1
source_actor_count = len(p.src_actor.fimp.actors)
if extra_buffer == True:
addres_port_type = integer_DataTokenType(source_port.count)
address_port_name = '_'.join(['read_address',
str(source_fimp.index),
str(source_actor.index),
str(source_port.index)])
else:
addres_port_type = \
integer_DataTokenType(source_port.count * source_actor_count)
address_port_name = '_'.join(['read_address',
str(source_fimp.index),
'shared',
str(source_port.index)])
if address_port_name not in read_address_ports.keys():
address_port = sdf.port(name=address_port_name, type=addres_port_type)
address_port.extra_buffer = extra_buffer
address_port.actions = []
address_port.source_fimp = source_fimp
address_port.source_port = source_port
if extra_buffer == True:
address_port.source_actor = source_actor
read_address_ports[address_port_name] = address_port
actions = read_address_ports[address_port_name].actions
previous_actions = len(actions)
if extra_buffer == True:
address_offset = previous_actions * p.dest_port.count
actions += [AddressPortAction(
cycle=input_start_time + token_index * cycles_step,
address=address_offset + token_index)
for token_index in xrange(p.dest_port.count)]
else:
actor_index = p.src_actor.abb.fimp.actors.index(p.src_actor)
address_offset = actor_index * p.src_port.count + previous_actions * p.dest_port.count
actions += [AddressPortAction(
cycle=input_start_time + token_index * cycles_step,
address=address_offset + token_index)
for token_index in xrange(p.dest_port.count)]
read_address_ports = read_address_ports.values()
input_ports = control_ports + data_input_ports + [current_cycle_port]
output_ports = data_output_ports + read_address_ports
base_actor = sdf.actor(name=name, input_ports=input_ports, output_ports=output_ports)
result = sdf.actor(name=name, input_ports=input_ports, output_ports=output_ports, base_actor=base_actor)
result.control_ports = control_ports
result.data_input_ports = data_input_ports
result.data_output_ports = data_output_ports
result.read_address_ports = read_address_ports
result.current_cycle_port = current_cycle_port
result.control_map = [
ControlMap(output_port=data_output_port,
conditions=[
PortMapCondition(control_port=c,
valid_values=[glic.INPUT, glic.IO],
input_port=data_input_ports[j + i*len(data_output_ports)])
for i, c in enumerate(control_ports)
for j, __ in enumerate(data_output_ports)])
for data_output_port in data_output_ports]
return result
if __name__ == '__main__':
if 'prepare system':
width = 10
height = 10
c = CGRA(width, height, hop_x=3, hop_y=3, TC=2, TW=1)
# json.dumps(c)
w, h, num_fimps = [2, 1, 4, 4, 1, 4, 1, 1], [2, 1, 1, 3, 1, 4, 4, 1], 8
num_actors = 10
fimps = range(num_fimps)
# FIMP size values
functions = [0, 1, 1, 2, 2, 3, 3, 3, 3, 4]
fimp_names = [0, 1, 2, 3, 3, 3, 3, 4]
actors = [sdf.actor(name='n_%i' % f, index=i)
for i, f in enumerate(functions)]
fimp_instances = [FIMP('n_%i' % f, index=i,
width=w[i], height=h[i], computation_phase=i)
for i, f in enumerate(fimp_names)]
c.fimps = fimp_instances
# create sdf graph
e_0_1 = sdf.connect(actors[0], 0, 1, actors[1], 0, 1)
e_0_2 = sdf.connect(actors[0], 1, 1, actors[2], 0, 1)
e_0_3 = sdf.connect(actors[0], 2, 1, actors[3], 0, 1)
e_0_4 = sdf.connect(actors[0], 3, 1, actors[4], 0, 1)
e_1_5 = sdf.connect(actors[1], 0, 2, actors[5], 0, 2)
e_2_6 = sdf.connect(actors[2], 0, 2, actors[6], 0, 2)
e_3_7 = sdf.connect(actors[3], 0, 2, actors[7], 0, 2)
def abb_to_vhdl(one_abb, sample_interval, sylva_lib):
entity_name = '_'.join([one_abb.fimp.name, str(one_abb.fimp.index)])
input_ports, output_ports = [], []
input_actor_and_ports, output_actor_and_ports = [], []
if hasattr(one_abb, 'abb_input_selector_actor'):
# input data ports
data_input_ports = one_abb.abb_input_selector_actor.data_input_ports
input_actor_and_ports += [
ActorAndPort(actor=one_abb.abb_input_selector_actor,
port=p)
for p in data_input_ports]
one_abb.data_input_ports = data_input_ports
# read address ports output
read_address_output_ports = one_abb.abb_input_selector_actor.read_address_ports
output_actor_and_ports += [
ActorAndPort(actor=one_abb.abb_input_selector_actor,
port=p)
for p in read_address_output_ports]
one_abb.read_address_output_ports = read_address_output_ports
input_ports += data_input_ports
output_ports += read_address_output_ports
if hasattr(one_abb, 'abb_output_buffer_actors'):
# output data ports
data_output_ports = [a.data_output_port for a in one_abb.abb_output_buffer_actors]
output_actor_and_ports += [ActorAndPort(actor=a, port=a.data_output_port)
for a in one_abb.abb_output_buffer_actors]
one_abb.data_output_ports = data_output_ports
# read address ports input
read_address_input_ports = [a.read_address_port for a in one_abb.abb_output_buffer_actors]
input_actor_and_ports += [ActorAndPort(actor=a, port=a.read_address_port)
for a in one_abb.abb_output_buffer_actors]
one_abb.read_address_input_ports = read_address_input_ports
input_ports += read_address_input_ports
output_ports += data_output_ports
status = hsdf_to_vhdl(one_abb.hsdf_actors, one_abb.hsdf_edges, sylva_lib,
entity_name=entity_name,
used_libraries={'IEEE': ['std_logic_1164.all'], 'WORK': ['all']},
output_file=entity_name + '.vhdl',
input_actor_and_ports=input_actor_and_ports,
output_actor_and_ports=output_actor_and_ports)
top_input_ports = [p.port for p in input_actor_and_ports]
top_output_ports = [p.port for p in output_actor_and_ports]
base_actor = sdf.actor(name=entity_name, index=one_abb.fimp.index,
input_ports=top_input_ports, output_ports=top_output_ports)
one_abb.top_actor = sdf.actor(name=entity_name, index=one_abb.fimp.index,
input_ports=top_input_ports, output_ports=top_output_ports,
base_actor=base_actor)
one_abb.top_actor.assign_to(fimp.fimp(name=entity_name, index=one_abb.fimp.index))
one_abb.top_actor.fimp.base_actor = base_actor
one_abb.top_actor.fimp.global_index = one_abb.fimp.index
return status
def buffer_actors(fimp_instance,
default_name='sylva_output_buffer',
read_write_signal='wr'):
fimp_index = str(fimp_instance.index)
extra_buffer = fimp_instance.extra_buffer == 1
result = []
if extra_buffer == True:
# each actor has its own output buffers
for actor in fimp_instance.actors:
result.append([])
actor_index = actor.index
# each output port has one output buffer
for port in actor.output_ports:
name = '_'.join([
default_name,
str(fimp_index),
str(actor_index),
str(port.index)
])
wr_port = sdf.port(name='_'.join(
[read_write_signal,
str(actor.index),
str(port.index)]),
index=0,
type=std_logic)
write_address_port = sdf.port(name='_'.join(
['write_address',
str(actor_index),
str(port.index)]),
type=integer_DataTokenType(
port.count))
read_address_port = sdf.port(name='_'.join([
'read_address',
str(fimp_instance.index),
str(actor_index),
str(port.index)
]),
type=integer_DataTokenType(
port.count))
data_input_port = sdf.port(name='_'.join([port.name]),
type=port.type)
data_output_port = sdf.port(name='_'.join(
[port.name, str(actor.index)]),
type=port.type)
input_ports = [
wr_port, write_address_port, read_address_port,
data_input_port
]
output_ports = [data_output_port]
port.top_port = data_output_port
base_actor = sdf.actor(name=name,
input_ports=input_ports,
output_ports=output_ports)
one_buffer = sdf.actor(name=name,
input_ports=input_ports,
output_ports=output_ports,
base_actor=base_actor)
one_buffer.buffer_size = port.count
one_buffer.wr_port = wr_port
one_buffer.write_address_port = write_address_port
one_buffer.read_address_port = read_address_port
one_buffer.data_input_port = data_input_port
one_buffer.data_output_port = data_output_port
result[-1].append(one_buffer)
else: # extra_buffer = False
actor_count = len(fimp_instance.actors)
for port in fimp_instance.actors[0].output_ports:
name = '_'.join(
[default_name,
str(fimp_index), 'shared',
str(port.index)])
wr_port = sdf.port(name='_'.join(
[read_write_signal, 'shared',
str(port.index)]),
index=0,
type=std_logic)
write_address_port = sdf.port(
name='_'.join(['write_address', 'shared',
str(port.index)]),
type=integer_DataTokenType(port.count * actor_count))
read_address_port = sdf.port(name='_'.join([
'read_address',
str(fimp_instance.index), 'shared',
str(port.index)
]),
type=integer_DataTokenType(
port.count * actor_count))
data_input_port = sdf.port(name='_'.join([port.name]),
type=port.type)
data_output_port = sdf.port(name='_'.join([port.name, 'shared']),
type=port.type)
input_ports = [
wr_port, write_address_port, read_address_port, data_input_port
]
output_ports = [data_output_port]
for a in fimp_instance.actors:
for p in a.output_ports:
if p.name == port.name:
p.top_port = data_output_port
base_actor = sdf.actor(name=name,
input_ports=input_ports,
output_ports=output_ports)
one_buffer = sdf.actor(name=name,
input_ports=input_ports,
output_ports=output_ports,
base_actor=base_actor)
one_buffer.buffer_size = port.count * len(fimp_instance.actors)
one_buffer.wr_port = wr_port
one_buffer.write_address_port = write_address_port
one_buffer.read_address_port = read_address_port
one_buffer.data_input_port = data_input_port
one_buffer.data_output_port = data_output_port
result.append(one_buffer)
return result
def buffer_control_actor(controls,
fimp_instance,
max_cycle,
max_output=glic.IO,
default_name='sylva_buffer_control',
read_write_signal='wr',
extra_buffer=True):
control_ports, control_port_range = \
get_control_ports('control_input', max_output, fimp_instance)
current_cycle_port = sdf.port(name='current_cycle',
index=0,
type=integer_DataTokenType(max_cycle))
wr_ports = [
sdf.port(name='_'.join([read_write_signal,
str(actor.index)]),
index=i,
type=std_logic)
for i, actor in enumerate(fimp_instance.actors)
]
address_ports = []
__, cycles_per_data_token = output_data_structure(fimp_instance.actors[0])
if extra_buffer == True:
# each actor has its own output buffers
for actor in fimp_instance.actors:
address_ports.append([])
# each output port has one output buffer
for port_index, port in enumerate(actor.output_ports):
address_ports[-1].append(
sdf.port(name='_'.join(
['write_address',
str(actor.index),
str(port.index)]),
type=integer_DataTokenType(port.count)))
address_ports[-1][-1].actions = [
(actor.output_start +
token_index * cycles_per_data_token[port_index],
token_index) for token_index in xrange(port.count)
]
else:
actor_count = len(fimp_instance.actors)
# all output ports of all actors share one output buffer
for port_index, port in enumerate(
fimp_instance.actors[0].output_ports):
address_ports.append(
sdf.port(name='_'.join(
['write_address', 'shared',
str(port.index)]),
type=integer_DataTokenType(port.count * actor_count)))
address_ports[-1].actions = []
token_index = 0
for actor_index, actor in enumerate(fimp_instance.actors):
for __ in xrange(port.count):
action = (actor.output_start +
token_index * cycles_per_data_token[port_index],
token_index)
token_index += 1
address_ports[-1].actions.append(action)
input_ports = control_ports + [current_cycle_port]
output_ports = wr_ports + address_ports
name = '_'.join([default_name, str(fimp_instance.index)])
base_actor = sdf.actor(name=name,
input_ports=input_ports,
output_ports=output_ports)
result = sdf.actor(name=name,
input_ports=input_ports,
output_ports=output_ports,
base_actor=base_actor)
result.control_ports = control_ports
result.current_cycle_port = current_cycle_port
result.wr_ports = wr_ports
result.address_ports = address_ports
return result
if 'prepare system':
width = 10
height = 10
c = CGRA(width, height, hop_x=3, hop_y=3, TC=2, TW=1)
# json.dumps(c)
w, h, num_fimps = [2, 1, 4, 4, 1, 4, 1, 1], [2, 1, 1, 3, 1, 4, 4, 1], 8
num_actors = 10
fimps = range(num_fimps)
# FIMP size values
functions = [0, 1, 1, 2, 2, 3, 3, 3, 3, 4]
fimp_names = [0, 1, 2, 3, 3, 3, 3, 4]
actors = [
sdf.actor(name='n_%i' % f, index=i)
for i, f in enumerate(functions)
]
fimp_instances = [
FIMP('n_%i' % f,
index=i,
width=w[i],
height=h[i],
computation_phase=i) for i, f in enumerate(fimp_names)
]
c.fimps = fimp_instances
# create sdf graph
e_0_1 = sdf.connect(actors[0], 0, 1, actors[1], 0, 1)
e_0_2 = sdf.connect(actors[0], 1, 1, actors[2], 0, 1)
e_0_3 = sdf.connect(actors[0], 2, 1, actors[3], 0, 1)
def abb_to_vhdl(one_abb, sample_interval, sylva_lib):
entity_name = '_'.join([one_abb.fimp.name, str(one_abb.fimp.index)])
input_ports, output_ports = [], []
input_actor_and_ports, output_actor_and_ports = [], []
if hasattr(one_abb, 'abb_input_selector_actor'):
# input data ports
data_input_ports = one_abb.abb_input_selector_actor.data_input_ports
input_actor_and_ports += [
ActorAndPort(actor=one_abb.abb_input_selector_actor, port=p)
for p in data_input_ports
]
one_abb.data_input_ports = data_input_ports
# read address ports output
read_address_output_ports = one_abb.abb_input_selector_actor.read_address_ports
output_actor_and_ports += [
ActorAndPort(actor=one_abb.abb_input_selector_actor, port=p)
for p in read_address_output_ports
]
one_abb.read_address_output_ports = read_address_output_ports
input_ports += data_input_ports
output_ports += read_address_output_ports
if hasattr(one_abb, 'abb_output_buffer_actors'):
# output data ports
data_output_ports = [
a.data_output_port for a in one_abb.abb_output_buffer_actors
]
output_actor_and_ports += [
ActorAndPort(actor=a, port=a.data_output_port)
for a in one_abb.abb_output_buffer_actors
]
one_abb.data_output_ports = data_output_ports
# read address ports input
read_address_input_ports = [
a.read_address_port for a in one_abb.abb_output_buffer_actors
]
input_actor_and_ports += [
ActorAndPort(actor=a, port=a.read_address_port)
for a in one_abb.abb_output_buffer_actors
]
one_abb.read_address_input_ports = read_address_input_ports
input_ports += read_address_input_ports
output_ports += data_output_ports
status = hsdf_to_vhdl(one_abb.hsdf_actors,
one_abb.hsdf_edges,
sylva_lib,
entity_name=entity_name,
used_libraries={
'IEEE': ['std_logic_1164.all'],
'WORK': ['all']
},
output_file=entity_name + '.vhdl',
input_actor_and_ports=input_actor_and_ports,
output_actor_and_ports=output_actor_and_ports)
top_input_ports = [p.port for p in input_actor_and_ports]
top_output_ports = [p.port for p in output_actor_and_ports]
base_actor = sdf.actor(name=entity_name,
index=one_abb.fimp.index,
input_ports=top_input_ports,
output_ports=top_output_ports)
one_abb.top_actor = sdf.actor(name=entity_name,
index=one_abb.fimp.index,
input_ports=top_input_ports,
output_ports=top_output_ports,
base_actor=base_actor)
one_abb.top_actor.assign_to(
fimp.fimp(name=entity_name, index=one_abb.fimp.index))
one_abb.top_actor.fimp.base_actor = base_actor
one_abb.top_actor.fimp.global_index = one_abb.fimp.index
return status