def testAdd05(self):
arch = Arch()
lines_of_mcode = [
b"\x05\x01\x02\x03\x04",
b"\x66\x05\x01\x02"
]
lines_of_code = [decode.decode(arch, data)[0] for data in lines_of_mcode]
self.chk_disassembler2(arch, lines_of_code, lines_of_mcode)
def testAdd00_32bit_fixed_sib(self):
arch = Arch()
lines_of_code = []
lines_of_mcode = []
for i in range(256):
mcode = bytes([0, i, 1, 2, 3, 4, 5, 6, 7, 8])
instruction, idx = decode.decode(arch, mcode)
lines_of_code.append(instruction)
lines_of_mcode.append(mcode[:idx])
self.chk_disassembler(arch, lines_of_code, lines_of_mcode)
def testAdd01_16bit_addr_and_op(self):
arch = Arch()
lines_of_code = []
lines_of_mcode = []
for i in range(256):
mcode = bytes([0x67, 0x66, 1, i, 1, 2, 3, 4, 5, 6, 7])
instruction, idx = decode.decode(arch, mcode)
lines_of_code.append(instruction)
lines_of_mcode.append(mcode[:idx])
self.chk_disassembler(arch, lines_of_code, lines_of_mcode)
def test06toFF(self):
arch = Arch()
lines_of_mcode = [
b"\x08\xf1",
b"\x09\xf1",
b"\x0A\xf1",
b"\x0B\xf1",
b"\x0C\xf1",
b"\x0D\x01\x02\x03\x04",
b"\x10\xf1",
b"\x11\xf1",
b"\x12\xf1",
b"\x13\xf1",
b"\x14\xf1",
b"\x15\x01\x02\x03\x04",
b"\x18\xf1",
b"\x19\xf1",
b"\x1A\xf1",
b"\x1B\xf1",
b"\x1C\xf1",
b"\x1D\x01\x02\x03\x04",
b"\x20\xf1",
b"\x21\xf1",
b"\x22\xf1",
b"\x23\xf1",
b"\x24\xf1",
b"\x25\x01\x02\x03\x04",
b"\x28\xf1",
b"\x29\xf1",
b"\x2A\xf1",
b"\x2B\xf1",
b"\x2C\xf1",
b"\x2D\x01\x02\x03\x04",
b"\x30\xf1",
b"\x31\xf1",
b"\x32\xf1",
b"\x33\xf1",
b"\x34\xf1",
b"\x35\x01\x02\x03\x04",
b"\x38\xf1",
b"\x39\xf1",
b"\x3A\xf1",
b"\x3B\xf1",
b"\x3C\xf1",
b"\x3D\x01\x02\x03\x04",
b"\x66\x40",
b"\x60",
b"\x66\x60",
b"\x61",
b"\x66\x61",
b"\x62\x01",
b"\x63\x01",
]
lines_of_code = [decode.decode(arch, data)[0] for data in lines_of_mcode]
self.chk_disassembler(arch, lines_of_code, lines_of_mcode)
def testAdd01_32bit_var_sib(self):
arch = Arch()
lines_of_code = []
lines_of_mcode = []
for j in (0x0C, 0x4c, 0x8c):
for i in range(256):
mcode = bytes([1, j, i, 1, 2, 3, 4, 5, 6, 7])
instruction, idx = decode.decode(arch, mcode)
lines_of_code.append(instruction)
lines_of_mcode.append(mcode[:idx])
self.chk_disassembler(arch, lines_of_code, lines_of_mcode)
def test_fuzzy(self):
arch = Arch()
for i in range(1000):
data = bytes([random.randint(0, 255) for i in range(16)])
try:
instruction, idx = decode.decode(Arch(), data)
except ValueError:
continue
except TypeError:
continue
except AttributeError:
continue
except IndexError:
continue
print(instruction)
data2 = assemble(arch, [instruction], [data])[0]
if data[:idx] != data2:
instruction2, idx = decode.decode(Arch(), data2)
self.assertEqual(instruction2, instruction)
else:
self.assertEqual(data[:idx], data2)
def chk_disassembler(self, arch, lines_of_code, lines_of_mcode):
if not isinstance(lines_of_code, list):
lines_of_code = [lines_of_code]
lines_of_mcode = [lines_of_mcode]
lines_of_mcode2 = assemble(arch, lines_of_code, lines_of_mcode)
for idx in range(len(lines_of_mcode)):
instruction = lines_of_code[idx]
mcode = lines_of_mcode[idx]
mcode2 = lines_of_mcode2[idx]
if mcode != mcode2: # Some assembly lead to different mcode
instruction2, idx = decode.decode(arch, mcode2)
self.assertEqual(instruction2, instruction)
else:
self.assertEqual(mcode, mcode2)
def testOneByteCode(self):
arch = Arch()
lines_of_mcode = []
lines_of_code = []
for i in (
0x06, 0x07, 0x0E, 0x16, 0x17, 0x1e, 0x1f, 0x27, 0x2f,
0x37, 0x3F, 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46,
0x47, 0x48, 0x49, 0x50, 0x51, 0x52, 0x53, 0x54, 0x55,
0x56, 0x57, 0x58, 0x59, 0x90
):
mcode = bytes([i,])
lines_of_mcode.append(mcode)
lines_of_code.append(decode.decode(arch, mcode)[0])
self.chk_disassembler2(arch, lines_of_code, lines_of_mcode)
def testAdd04(self):
arch = Arch()
data = b"\x04\x05"
instruction, idx = decode.decode(arch, data)
self.chk_disassembler2(arch, instruction, data)
def testAdd03(self):
"""01 and 03 are same except ops are swapped"""
arch = Arch()
data = b"\x66\x03\x05\x0a\x00\x00\x00"
instruction, idx = decode.decode(arch, data)
self.chk_disassembler(arch, instruction, data)
