def get_enum_values(line):
line = util.clip_in_blacket(line, '{')
line = line.replace(' ','')
line = line.replace('\t','')
enum_dict = OrderedDict()
i = 0
for val in line.split(','):
if '=' in val:
i = int(val[val.find('=') + 1:])
enum_dict[val[0:val.find('=')]] = i
else:
enum_dict[val] = i
i += 1
return enum_dict
def get_enum_values(line):
line = util.clip_in_blacket(line, '{')
line = line.replace(' ', '')
line = line.replace('\t', '')
enum_dict = OrderedDict()
i = 0
for val in line.split(','):
if '=' in val:
i = int(val[val.find('=') + 1:])
enum_dict[val[0:val.find('=')]] = i
else:
enum_dict[val] = i
i += 1
return enum_dict
def readfirstline(self):
"""[FUNCTIONS]
ex.
module COMPARE(output GT, output LE, output EQ,
input [1:0] A, input [1:0] B, input C);
"""
first_line = " ".join(self.dec_lines)
first_line = first_line.replace('\n', ' ')
self.name = get_module_name_from_decline(first_line)
if ('input' not in first_line and 'inout' not in first_line
and 'output' not in first_line):
return
first_line = re.sub("#\(.+?\)", " ", first_line)
first_line = re.sub("\[.+?\]", " ", first_line)
in_bracket = util.clip_in_blacket(first_line)
decs = in_bracket.split(',')
#words[-1] :exclude type definition
for dec in decs:
words = dec.split()
self._add_port(words[-1], words[0])
def readfirstline(self):
"""[FUNCTIONS]
ex.
module COMPARE(output GT, output LE, output EQ,
input [1:0] A, input [1:0] B, input C);
"""
first_line = " ".join(self.dec_lines)
first_line = first_line.replace('\n', ' ')
self.name = get_module_name_from_decline(first_line)
if ('input' not in first_line and 'inout' not in first_line
and 'output' not in first_line):
return
first_line = re.sub("#\(.+?\)", " ", first_line)
first_line = re.sub("\[.+?\]", " ", first_line)
in_bracket = util.clip_in_blacket(first_line)
decs = in_bracket.split(',')
#words[-1] :exclude type definition
for dec in decs:
words = dec.split()
self._add_port(words[-1], words[0])
def convert_for_logic(line, module_lines, module_name):
logic_convert_dict = {'logic': 'reg', 'bit': 'reg', 'byte': 'reg [7:0]'}
wire_convert_dict = {'logic': 'wire', 'bit': 'wire', 'byte': 'wire [7:0]'}
wire_flag = False
words = line.replace(';', '').split()
if not words: return line
if words[0] == 'input' or words[0] == 'output' or words[0] == 'inout':
words = words[1:]
if words[0] in logic_convert_dict.keys():
if words[1][0] == '[':
var_name = words[2]
else:
var_name = words[1]
for i, templine in enumerate(module_lines):
if 'assign' in templine and var_name in templine[0:templine.
find('=')]:
wire_flag = True
break
#elif var_name in module_data_base().module_dict[module_name].input:
# wire_flag = True
# break
#elif var_name in module_data_base().module_dict[module_name].inout:
# wire_flag = True
# break
elif get_mod_instance(templine):
assigned_module = get_mod_instance(templine)
dec_lines = []
j = 0
while ';' not in module_lines[i + j]:
dec_lines.append(module_lines[i + j])
j += 1
dec_lines.append(module_lines[i + j]) #add last line
dec_line = ' '.join(dec_lines).replace('\n', ' ')
if '*' in dec_line: #assigned by wild card or not
if var_name in module_data_base(
).module_dict[assigned_module].output:
wire_flag = True
elif '.' in dec_line:
if var_name in get_in_bracket_signals(dec_line):
#assigned by port name
# SUB sub(.CLK(CLK),.RST(RST),.IN(in1),.OUT1(OUT));
# .Port_name(Signal_name)
dec_line = util.clip_in_blacket(dec_line)
dec_line = dec_line.replace('.', '')
assigned_ports = dec_line.split(',')
for comb in assigned_ports:
signal = util.clip_in_blacket(comb)
port = comb[0:comb.find('(')]
#print(port + ': ' +signal)
if signal == var_name:
if port in module_data_base(
).module_dict[assigned_module].output:
wire_flag = True
break
else:
raise Exception("Unexpected exception.")
else: #assigned by order name
assigned_vars = util.clip_in_blacket(dec_line).split(',')
for i, assigned_var in enumerate(assigned_vars):
if assigned_var.strip() == var_name:
if module_data_base().module_dict[
assigned_module].all_ports[i] == 'output':
wire_flag = True
break
## else:
## raise Exception("Unexpected exception.")
if wire_flag:
line = line.replace(words[0], wire_convert_dict[words[0]])
else:
line = line.replace(words[0], logic_convert_dict[words[0]])
return line
def convert_for_logic(line, module_lines, module_name):
logic_convert_dict = {'logic': 'reg', 'bit': 'reg', 'byte': 'reg [7:0]'}
wire_convert_dict = {'logic': 'wire', 'bit': 'wire', 'byte': 'wire [7:0]'}
wire_flag = False
words = line.replace(';', '').split()
if not words: return line
if words[0] == 'input' or words[0] == 'output' or words[0] == 'inout':
words = words[1:]
if words[0] in logic_convert_dict.keys():
if words[1][0] == '[':
var_name = words[2]
else:
var_name = words[1]
for i, templine in enumerate(module_lines):
if 'assign' in templine and var_name in templine[0:templine.find('=')]:
wire_flag = True
break
elif var_name in module_data_base().module_dict[module_name].input:
wire_flag = True
break
elif var_name in module_data_base().module_dict[module_name].inout:
wire_flag = True
break
elif get_mod_instance(templine):
assigned_module = get_mod_instance(templine)
dec_lines = []
j = 0
while ';' not in module_lines[i+j]:
dec_lines.append(module_lines[i+j])
j += 1
dec_lines.append(module_lines[i+j])#add last line
dec_line = ' '.join(dec_lines).replace('\n', ' ')
if '*' in dec_line: #assigned by wild card or not
if var_name in module_data_base().module_dict[assigned_module].output:
wire_flag = True
elif '.' in dec_line:
if var_name in get_in_bracket_signals(dec_line):
#assigned by port name
# SUB sub(.CLK(CLK),.RST(RST),.IN(in1),.OUT1(OUT));
# .Port_name(Signal_name)
dec_line = util.clip_in_blacket(dec_line)
dec_line = dec_line.replace('.','')
assigned_ports = dec_line.split(',')
for comb in assigned_ports:
signal = util.clip_in_blacket(comb)
port = comb[0:comb.find('(')]
#print(port + ': ' +signal)
if signal == var_name:
if port in module_data_base().module_dict[assigned_module].output:
wire_flag = True
break
else:
raise Exception("Unexpected exception.")
else: #assigned by order name
assigned_vars = util.clip_in_blacket(dec_line).split(',')
for i, assigned_var in enumerate(assigned_vars):
if assigned_var.strip() == var_name:
if module_data_base().module_dict[assigned_module].all_ports[i] == 'output':
wire_flag = True
break
## else:
## raise Exception("Unexpected exception.")
if wire_flag:
line = line.replace(words[0], wire_convert_dict[words[0]])
else:
line = line.replace(words[0], logic_convert_dict[words[0]])
return line
