def test_simple_no_buffer(self):
root = Gate(Coordinate([0, 0]), ElectroProperty([10, 0]))
root[1] = Gate(Coordinate([10, 0]), ElectroProperty([0, 5]))
unit_rc = ElectroProperty([1 / Coordinate.scale] * 2)
self.assertEqual(DFS(root, unit_rc, RCAdjustment()).delay()[0], 250)
def setUp(self):
self._root_gate = Gate(Coordinate([1, 0]), ElectroProperty([4, 0]))
self._root_gate[1] = Node(Coordinate([1, 5]))
self._root_gate[1][3] = Gate(Coordinate([1, 13]), ElectroProperty([0, 8]))
self._root_gate[2] = Gate(Coordinate([1, 6]), ElectroProperty([0, 7]))
self._unit_rc = ElectroProperty([1 / Coordinate.scale] * 2)
def test_two_branch_one_buffer(self):
root = Gate(Coordinate([0, 0]), ElectroProperty([10, 0]))
root[1] = Node(Coordinate([5, 0]))
root[1][1] = Gate(Coordinate([5, 0]), ElectroProperty([10, 10]))
root[1][1][1] = Gate(Coordinate([10, 0]), ElectroProperty([0, 5]))
root[1][2] = Gate(Coordinate([10, 5]), ElectroProperty([0, 10]))
unit_rc = ElectroProperty([1 / Coordinate.scale] * 2)
self.assertEqual(DFS(root, unit_rc, RCAdjustment()).delay()[0], 662.5)
def test_binary_tree(self):
driver_0 = Gate(Coordinate([0, 0]), ElectroProperty([1, 0]))
buffer_1 = Gate(Coordinate([6, 0]), ElectroProperty([2, 2]))
node_2 = Node(Coordinate([6, 0]))
buffer_3 = Gate(Coordinate([6, 0]), ElectroProperty([5, 5]))
sink_4 = Gate(Coordinate([26, 0]), ElectroProperty([0, 10]))
sink_5 = Gate(Coordinate([16, 0]), ElectroProperty([0, 10]))
node_6 = Node(Coordinate([0, 10]))
sink_7 = Gate(Coordinate([0, 20]), ElectroProperty([0, 5]))
buffer_8 = Gate(Coordinate([0, 10]), ElectroProperty([4, 4]))
sink_9 = Gate(Coordinate([0, 16]), ElectroProperty([0, 10]))
driver_0[1] = buffer_1
buffer_1[2] = node_2
node_2[3] = buffer_3
buffer_3[4] = sink_4
node_2[5] = sink_5
driver_0[6] = node_6
node_6[7] = sink_7
node_6[8] = buffer_8
buffer_8[9] = sink_9
unit_rc = ElectroProperty([1 / Coordinate.scale] * 2)
self.assertEqual(DFS(driver_0, unit_rc, RCAdjustment()).delay()[0], 667)
def test_complex_case(self):
root = Gate(Coordinate([0, 0]), ElectroProperty([5, 0]))
root[1] = Node(Coordinate([0, 10]))
root[1][1] = Gate(Coordinate([0, 10]), ElectroProperty([10, 10]))
root[1][2] = Gate(Coordinate([0, 50]), ElectroProperty([0, 10]))
root[1][1][1] = Node(Coordinate([0, 40]))
root[1][1][1][1] = Gate(Coordinate([0, 40]), ElectroProperty([5, 5]))
root[1][1][1][2] = Gate(Coordinate([0, 60]), ElectroProperty([0, 5]))
root[1][1][1][1][1] = Gate(Coordinate([0, 50]), ElectroProperty([0, 5]))
unit_rc = ElectroProperty([1 / Coordinate.scale] * 2)
self.assertEqual(DFS(root, unit_rc, RCAdjustment()).delay()[0], 3250)
def __init__(self, electro_property=(0, 0), intrinsic_delay=0):
ElectroProperty.__init__(self, electro_property)
self._intrinsic_delay = intrinsic_delay
def test_electro_property(self):
self.parser.parse()
self.assertEqual(self.parser.nodes[0].electro_property,
ElectroProperty([0.328886, 0]))
self.assertEqual(self.parser.nodes[6].electro_property,
ElectroProperty([0, 0.004111]))
def parse(self):
map(self.create_node, [line.split() for line in self.lines()])
self._unit_electro_property = ElectroProperty(
[self._parse_unit_rc(is_valid_wire_unit_res), self._parse_unit_rc(is_valid_wire_unit_cap)])
map(self.create_edge, filter(is_edge, self.lines()))
return self.nodes
def __init__(self, electro_property=(0, 0), intrinsic_delay=0):
ElectroProperty.__init__(self, electro_property)
self._intrinsic_delay = intrinsic_delay
def parse(self):
return ElectroProperty(
map(lambda _: float(_) * UnitRCParser._scaling, self.line))
def __init__(self, coord):
self._coord = Coord(coord)
self._electro_property = ElectroProperty()
def test_content(self):
self.assertIn(
ElectroProperty(
map(lambda _: _ * UnitRCParser._scaling,
[0.006499, 0.142514])),
WireRCParser('cnt_res_cap_5000.txt').parse())
def create_sink(self):
return self.get_index(), Gate(
self.get_coord(), ElectroProperty([0.0, float(self.line[4])]))
def create_driver(self):
return self.get_index(), Gate(
self.get_coord(), ElectroProperty([float(self.line[4]), 0.0]))