def setUp(self):
self.a = AutoStoreStack(arch['bytesize'], 3, 1)
self.var = Var(
"testVar",
Loc.RegisterX64('rsi'),
Type.Bit64
)
def setUp(self):
self.ul = Var.UpdateLocationBuilder(arch)
tpe = Bit64
loc = Loc.RegisterX64('rax')
self.var = Var.Var('testVar', loc, tpe)
self.b = Builder()
self.ul.toStack(self.b, self.var, 3)
def setUp(self):
self.a = AutoStoreReg(arch['generalPurposeRegisters'])
self.var = Var(
"testVar",
Loc.RegisterX64('r14'),
Type.Bit64
)
self.a._set('r14', self.var)
def setUp(self):
# arch, sizeSlots, offset
self.a = AutoStoreX64(arch, 3, 1)
self.var = Var(
"testVar",
Loc.RegisterX64('r14'),
Type.Bit64
)
def varRegCreate(self, b, name, regName, tpe, priority):
'''
Create a var on a named register.
If the register has an existing var it is moved to another
register or stack. The destination depends on the
priority of the displaced var, and may cascade.
Tracked
'''
self._varRegExistingMove(b, regName)
var = Var(
name,
Loc.RegisterX64(regName),
tpe
)
var.priority = priority
self.autoReg._set(regName, var)
return var
def test_init(self):
tpe = Bit64
loc = Loc.RegisterX64('rsi')
var = Var.Var('testVar', loc, tpe)
self.assertEqual(var.tpe, Bit64)
def test_init_fail2(self):
tpe = 'rsi'
loc = Loc.RegisterX64('rsi')
with self.assertRaises(Exception):
Var.Var('testVar', loc, tpe)
def test_register_fail2(self):
with self.assertRaises(Exception):
Loc.RegisterX64('str1')
def test_register(self):
Loc.RegisterX64('rbx')
def test_reg(self):
loc = Loc.RegisterX64('r12')
b = AccessAddress(loc)
with self.assertRaises(AssertionError):
self.assertEqual(b.result(), 'r12')
def test_reg_no_register(self):
loc = Loc.RegisterX64('r12')
b = AccessValue(loc)
b.addRegister('r12')
with self.assertRaises(AssertionError):
self.assertEqual(b.result(), '[r12]')
def test_reg(self):
loc = Loc.RegisterX64('r12')
b = AccessValue(loc)
self.assertEqual(b.result(), 'r12')