def qep(self):
if not self._qep:
self.regs.clkreq.qep = 1
if self.regs.clkack.qep != 1:
raise RuntimeError("submodule clock failure?")
uio = Uio(self.path.parent / 'qep', parent=self)
self._qep = uio.map(EQep)
self._qep.irq.uio = uio
return self._qep
def cap(self):
if not self._cap:
self.regs.clkreq.cap = 1
if self.regs.clkack.cap != 1:
raise RuntimeError("submodule clock failure?")
uio = Uio(self.path.parent / 'cap', parent=self)
self._cap = uio.map(ECap)
self._cap.irq.uio = uio
return self._cap
def _add_submodule(self, name, Module, offset):
module = None
path = self.path / name
if path.exists():
uio = Uio(path, parent=self)
assert uio.region().address == self.region().address + offset
module = uio.map(Module)
module._uio = uio
module.irq.uio = uio
setattr(self, name, module)
if module is None:
# fallback, mainly for debugging:
module = self.map(Module, offset)
setattr(self, '_' + name, module)
#!/usr/bin/python3
from uio.device import Uio
from uio.ti.subarctic.lcdc import Lcdc, lcdc_fck
from time import sleep
uio = Uio( "/dev/uio/lcdc" )
lcdc = uio.map( Lcdc )
# lcdc functional clock rate
fck = lcdc_fck()
print( "lcdc_fck = %f MHz" % (fck/1e6) )
# global config
lcdc.clock_div = 6 # FIXME pick suitable value
lcdc.pinmux = 0 # rfb
# memory clock rate
mck = fck / lcdc.clock_div
print( "lcdc_mck = %f MHz (1 cycle = %f ns)" % (mck/1e6, 1e9/mck) )
# sanity checks
if fck > 252000000:
raise RuntimeError('lcdc functional clock exceeds max spec')
if mck > 126000000:
raise RuntimeError('lcdc memory clock exceeds max spec')
elif mck > 42000000 and lcdc.pinmux == 0:
raise RuntimeError('lcdc memory clock exceeds max spec for rfb mode')
rfb = lcdc.rfb
rfb.protocol = 4 # hd44780