def start_of_simulation(*k, **kw):
for param in get_args().loadelf:
result = memoryre.match(param)
if not result:
print("-e takes always a key/value pair. '%s' is not a key/value pair. The value must be contain a file name and a base address: '-e sdram=hello.sparc(0x40000000)'" % (param))
continue
groups = result.groupdict()
if not 'object' in groups or not 'filename' in groups:
print("-e takes always a key/value pair. '%s' is not a key/value pair. The value must be contain a file name and a base address: '-e sdram=hello.sparc(0x40000000)'" % (param))
continue
obj = groups['object']
filename = groups['filename']
if "baseaddr" in groups and groups['baseaddr']:
base = int(groups['baseaddr'], 0) # not 100% right, won't work in the case when there is no 0x in front of Hex string!
elif filename.endswith('.sparc') or filename.endswith('.dsu'):
base = 0x40000000
else:
base = 0x00000000
stores = usi.find(obj)
if len(stores) == 0:
print("scireg %s not found in simulation for parameter -e %s" % (obj, param))
continue
load_elf_into_scireg(filename, stores, base)
for param in get_args().intrinsics:
result = intrinsicre.match(param)
if not result:
print("-i takes always a key/value pair. '%s' is not a key/value pair. The value must be contain a file name and a list of intrinsics: '-i leon3_0=hello.sparc(open,close)'" % (param))
continue
groups = result.groupdict()
if not 'object' in groups or not 'filename' in groups or not 'intrinsics':
print("-i takes always a key/value pair. '%s' is not a key/value pair. The value must be contain a file name and a base address: '-i leon3_0=hello.sparc(open,close)'" % (param))
continue
obj = groups['object']
filename = groups['filename']
intrinsiclist = groups['intrinsics'].split(',')
intrinsics = {}
for intrinsic in intrinsiclist:
splitted = intrinsic.split('=')
if len(splitted) == 1:
if splitted[0] in intrinsic_groups:
intrinsics.update(intrinsic_groups[splitted[0]])
else:
intrinsics[splitted[0]] = splitted[0]
elif len(splitted) > 1:
if splitted[1] == 'None':
del(intrinsics[splitted[0]])
else:
intrinsics[splitted[0]] = splitted[1]
else:
pass
cpus = usi.find(obj)
if len(cpus) == 0:
print("cpu %s not found in simulation for parameter -i %s" % (obj, param))
continue
load_elf_intrinsics_to_processor(filename, cpus, intrinsics)
def __init__(self, name):
print " * Creating Supervisor Subsystem:"
super(SupervisorSystem, self).__init__()
self.voter = module.Voter("voter",
irq=4, # Interuptline Used
wdog=0x21FF # CLK Cycles to hit
)
for idx, name in enumerate(["leon", "microblaze", "arm"]):
commitreg = usi.find(name + "_system.commitregister")[0]
irqmp = usi.find(name + "_system.irqmp")[0]
self.voter.commit.signal_bind(commitreg.commit, idx)
self.voter.irq.signal_bind(irqmp.irq_in, 4)
def onstart(*k, **kw):
banks = []
search_result = usi.find('leon3_0.dvectorcache.line_63.*')
for component in search_result:
if implements_scireg(component) and\
component.scireg_get_region_type() == scireg.SCIREG_BANK:
banks.append(component)
total_bytes_banks = 0
for bank in banks:
print(bank.name())
def onstart(*k, **kw):
banks = []
search_result = usi.find('leon3_0.dvectorcache.line_63.*')
for component in search_result:
if implements_scireg(component) and\
component.scireg_get_region_type() == scireg.SCIREG_BANK:
banks.append(component)
total_bytes_banks = 0
for bank in banks:
print(bank.name())
def onstart(*k, **kw):
registers = []
search_result = usi.find('*')
for component in search_result:
if implements_scireg(component) and\
component.scireg_get_region_type() == scireg.SCIREG_REGISTER:
registers.append(component)
total_bytes_register = 0
for register in registers:
print(register.name())
total_bytes_register += register.scireg_get_byte_width()
print('Total bytes in registers: {}'.format(total_bytes_register))
def onstart(*k, **kw):
memories = []
search_result = usi.find('*')
for component in search_result:
if implements_scireg(component) and\
component.scireg_get_region_type() == scireg.SCIREG_MEMORY:
memories.append(component)
total_bytes_memories = 0
for memory in memories:
print(memory.name())
total_bytes_memories += memory.scireg_get_byte_width()
print(memory.scireg_get_byte_width())
print('Total bytes in memories: {}; {} MB'.format(total_bytes_memories, total_bytes_memories / (1024 * 1024)))
def onstart(*k, **kw):
memories = []
search_result = usi.find('*')
for component in search_result:
if implements_scireg(component) and\
component.scireg_get_region_type() == scireg.SCIREG_MEMORY:
memories.append(component)
total_bytes_memories = 0
for memory in memories:
print(memory.name())
total_bytes_memories += memory.scireg_get_byte_width()
print(memory.scireg_get_byte_width())
print('Total bytes in memories: {}; {} MB'.format(
total_bytes_memories, total_bytes_memories / (1024 * 1024)))
def simulation_begin(*k, **kw):
def read_access(*k, **kw):
width = k[2].scireg_get_byte_width()
tag_name = k[2].scireg_get_string_attribute(
scireg.SCIREG_NAME)[:-5] + 'tag.atag'
tag = usi.USIDelegate(tag_name)
print("Callback: Read access at address {:02} with length of {:02} bytes on {}: current value {:#0{length}x}, with tag {:#08x}"\
.format(
k[0],
k[1],
k[2].scireg_get_string_attribute(scireg.SCIREG_NAME),
convert2int(k[2].scireg_read(long(width))),
convert2int(tag.scireg_read(long(4))),
length=width*2,
)
)
def write_access(*k, **kw):
width = k[2].scireg_get_byte_width()
tag_name = k[2].scireg_get_string_attribute(
scireg.SCIREG_NAME)[:-5] + 'tag.atag'
tag = usi.USIDelegate(tag_name)
print("Callback: Write access at address {:02} with length of {:02} bytes on {}: current value {:#0{length}x}, with tag {:#08x}"\
.format(
k[0],
k[1],
k[2].scireg_get_string_attribute(scireg.SCIREG_NAME),
convert2int(k[2].scireg_read(long(width))),
convert2int(tag.scireg_read(long(4))),
length=width*2,
)
)
everything = usi.find('*')
cache_lines = []
for scobject in everything:
if re.search(r"leon3_0\.dvectorcache\.line_\d+\.entry",
scobject.name()):
cache_lines.append(scobject)
for cache_line in cache_lines:
cache_line.scireg_add_callback(
(read_access, scireg.SCIREG_READ_ACCESS, long(0), long(4)))
cache_line.scireg_add_callback(
(write_access, scireg.SCIREG_WRITE_ACCESS, long(0), long(4)))
def simulation_begin(*k, **kw):
def read_access(*k, **kw):
width = k[2].scireg_get_byte_width()
tag_name = k[2].scireg_get_string_attribute(scireg.SCIREG_NAME)[:-5] + 'tag.atag'
tag = usi.USIDelegate(tag_name)
print("Callback: Read access at address {:02} with length of {:02} bytes on {}: current value {:#0{length}x}, with tag {:#08x}"\
.format(
k[0],
k[1],
k[2].scireg_get_string_attribute(scireg.SCIREG_NAME),
convert2int(k[2].scireg_read(long(width))),
convert2int(tag.scireg_read(long(4))),
length=width*2,
)
)
def write_access(*k, **kw):
width = k[2].scireg_get_byte_width()
tag_name = k[2].scireg_get_string_attribute(scireg.SCIREG_NAME)[:-5] + 'tag.atag'
tag = usi.USIDelegate(tag_name)
print("Callback: Write access at address {:02} with length of {:02} bytes on {}: current value {:#0{length}x}, with tag {:#08x}"\
.format(
k[0],
k[1],
k[2].scireg_get_string_attribute(scireg.SCIREG_NAME),
convert2int(k[2].scireg_read(long(width))),
convert2int(tag.scireg_read(long(4))),
length=width*2,
)
)
everything = usi.find('*')
cache_lines = []
for scobject in everything:
if re.search(r"leon3_0\.dvectorcache\.line_\d+\.entry", scobject.name()):
cache_lines.append(scobject)
for cache_line in cache_lines:
cache_line.scireg_add_callback((read_access, scireg.SCIREG_READ_ACCESS, long(0), long(4)))
cache_line.scireg_add_callback((write_access, scireg.SCIREG_WRITE_ACCESS, long(0), long(4)))
def simulation_begin(*k, **kw):
def read_access(*k, **kw):
print("Callback: Read access at address {} with length of {} bytes on {}: current value {}"\
.format(k[0], k[1], k[2].scireg_get_string_attribute(scireg.SCIREG_NAME), convert2int(k[2].scireg_read(long(4)))))
def write_access(*k, **kw):
print("Callback: Write access at address {} with length of {} bytes on {}: current value {}"\
.format(k[0], k[1], k[2].scireg_get_string_attribute(scireg.SCIREG_NAME), convert2int(k[2].scireg_read(long(4)))))
everything = usi.find('*')
cache_lines = []
for scobject in everything:
if re.search(r"leon3_0\.ivectorcache\.line_\d+\.tag\.valid", scobject.name()):
cache_lines.append(scobject)
for cache_line in cache_lines:
cache_line.scireg_add_callback((read_access, scireg.SCIREG_READ_ACCESS, long(0), long(4)))
cache_line.scireg_add_callback((write_access, scireg.SCIREG_WRITE_ACCESS, long(0), long(4)))
def simulation_begin(*k, **kw):
def read_access(*k, **kw):
print("Callback: Read access at address {} with length of {} bytes on {}: current value {}"\
.format(k[0], k[1], k[2].scireg_get_string_attribute(scireg.SCIREG_NAME), convert2int(k[2].scireg_read(long(4)))))
def write_access(*k, **kw):
print("Callback: Write access at address {} with length of {} bytes on {}: current value {}"\
.format(k[0], k[1], k[2].scireg_get_string_attribute(scireg.SCIREG_NAME), convert2int(k[2].scireg_read(long(4)))))
everything = usi.find('*')
cache_lines = []
for scobject in everything:
if re.search(r"leon3_0\.ivectorcache\.line_\d+\.tag\.valid",
scobject.name()):
cache_lines.append(scobject)
for cache_line in cache_lines:
cache_line.scireg_add_callback(
(read_access, scireg.SCIREG_READ_ACCESS, long(0), long(4)))
cache_line.scireg_add_callback(
(write_access, scireg.SCIREG_WRITE_ACCESS, long(0), long(4)))
def class_systems(*k, **kw):
# gs_params for options
_mctrl_prom_elf_arg = "conf.mctrl.prom.elf"
_mctrl_ram_sdram_elf_arg = "conf.mctrl.ram.sdram.elf"
for param in get_args().option:
param = param.split("=")
# save in variables
if param[0] == _mctrl_prom_elf_arg:
mctrl_prom_elf = param[1]
if param[0] == _mctrl_ram_sdram_elf_arg:
mctrl_ram_sdram_elf = param[1]
leonsystem = LeonSystem("leon_system", 0)
leonsystem.store_elf(mctrl_prom_elf, mctrl_ram_sdram_elf, True)
#leonsystem.store_elf("build/core/software/prom/sdram/sdram.prom", "build/quadcopter/test/test.sparc", True)
# Fehlermeldung wenn store noch nciht existiert AHBMem/Memory!
#microblazesystem = LeonSystem("microblaze_system", 1)
#microblazesystem.store_elf("build/core/software/prom/sdram/sdram.prom", "build/core/software/trapgen/hanoi.sparc", True)
#microblazesystem = MicroBlazeSystem("microblaze_system")
#microblazesystem.store_elf("build/core/software/prom/sdram/sdram.prom", "build/core/software/grlib_tests/hello.sparc", True)
#"hello.microblaze",
#microblazesystem.store_elf("build/core/software/prom/sdram/sdram.prom", "build/core/software/grlib_tests/hello.sparc", True)
#armsystem = LeonSystem("a_system", 1)
#armsystem.store_elf("build/core/software/prom/sdram/sdram.prom", "build/core/software/trapgen/hanoi.sparc", True)
#armsystem = LeonSystem("arm_system", 2)
#armsystem.store_elf("build/core/software/prom/sdram/sdram.prom", "build/core/software/grlib_tests/hello.sparc", True)
#armsystem = ARMSystem("arm_system")
#armsystem.store_elf("build/arm/prom/arm.prom", "build/core/software/grlib_tests/hello.sparc", True)
#supervisorsystem = SupervisorSystem("supervisor_system")
usi.add_to_reporting_list("leon_system.ahbctrl", usi.report.SC_WARNING, 0)
for vec in ['ivectorcache', 'dvectorcache']:
caches = usi.find("leon_system.cpu.{}.*".format(vec))
usi.add_to_reporting_list(caches, usi.report.SC_WARNING, 0)
def start_of_simulation(*k, **kw):
for param in get_args().loadelf:
result = memoryre.match(param)
if not result:
print(
"-e takes always a key/value pair. '%s' is not a key/value pair. The value must be contain a file name and a base address: '-e sdram=hello.sparc(0x40000000)'"
% (param))
continue
groups = result.groupdict()
if not 'object' in groups or not 'filename' in groups:
print(
"-e takes always a key/value pair. '%s' is not a key/value pair. The value must be contain a file name and a base address: '-e sdram=hello.sparc(0x40000000)'"
% (param))
continue
obj = groups['object']
filename = groups['filename']
if "baseaddr" in groups and groups['baseaddr']:
base = int(
groups['baseaddr'], 0
) # not 100% right, won't work in the case when there is no 0x in front of Hex string!
elif filename.endswith('.sparc') or filename.endswith('.dsu'):
base = 0x40000000
else:
base = 0x00000000
stores = usi.find(obj)
if len(stores) == 0:
print("scireg %s not found in simulation for parameter -e %s" %
(obj, param))
continue
load_elf_into_scireg(filename, stores, base)
for param in get_args().intrinsics:
result = intrinsicre.match(param)
if not result:
print(
"-i takes always a key/value pair. '%s' is not a key/value pair. The value must be contain a file name and a list of intrinsics: '-i leon3_0=hello.sparc(open,close)'"
% (param))
continue
groups = result.groupdict()
if not 'object' in groups or not 'filename' in groups or not 'intrinsics':
print(
"-i takes always a key/value pair. '%s' is not a key/value pair. The value must be contain a file name and a base address: '-i leon3_0=hello.sparc(open,close)'"
% (param))
continue
obj = groups['object']
filename = groups['filename']
intrinsiclist = groups['intrinsics'].split(',')
intrinsics = {}
for intrinsic in intrinsiclist:
splitted = intrinsic.split('=')
if len(splitted) == 1:
if splitted[0] in intrinsic_groups:
intrinsics.update(intrinsic_groups[splitted[0]])
else:
intrinsics[splitted[0]] = splitted[0]
elif len(splitted) > 1:
if splitted[1] == 'None':
del (intrinsics[splitted[0]])
else:
intrinsics[splitted[0]] = splitted[1]
else:
pass
cpus = usi.find(obj)
if len(cpus) == 0:
print("cpu %s not found in simulation for parameter -i %s" %
(obj, param))
continue
load_elf_intrinsics_to_processor(filename, cpus, intrinsics)
