def update_fpga(self, filepath, metadata):
"""
Update the FPGA image in the filesystem and reload the overlay
:param filepath: path to new FPGA image
:param metadata: Dictionary of strings containing metadata
"""
self.log.trace("Updating FPGA with image at {} (metadata: `{}')"
.format(filepath, str(metadata)))
_, file_extension = os.path.splitext(filepath)
# Cut off the period from the file extension
file_extension = file_extension[1:].lower()
binfile_path = self.updateable_components['fpga']['path'].format(
self.device_info.get('product'))
if file_extension == "bit":
self.log.trace("Converting bit to bin file and writing to {}"
.format(binfile_path))
from usrp_mpm.fpga_bit_to_bin import fpga_bit_to_bin
fpga_bit_to_bin(filepath, binfile_path, flip=True)
elif file_extension == "bin":
self.log.trace("Copying bin file to %s", binfile_path)
shutil.copy(filepath, binfile_path)
else:
self.log.error("Invalid FPGA bitfile: %s", filepath)
raise RuntimeError("Invalid N3xx FPGA bitfile")
# RPC server will reload the periph manager after this.
return True
def update_fpga(self, filepath, metadata):
"""
Update the FPGA image in the filesystem and reload the overlay
:param filepath: path to new FPGA image
:param metadata: Dictionary of strings containing metadata
"""
self.log.trace(
"Updating FPGA with image at {} (metadata: `{}')".format(
filepath, str(metadata)))
_, file_extension = os.path.splitext(filepath)
# Cut off the period from the file extension
file_extension = file_extension[1:].lower()
binfile_path = self.updateable_components['fpga']['path']
if file_extension == "bit":
self.log.trace(
"Converting bit to bin file and writing to {}".format(
binfile_path))
from usrp_mpm.fpga_bit_to_bin import fpga_bit_to_bin
fpga_bit_to_bin(filepath, binfile_path, flip=True)
elif file_extension == "bin":
self.log.trace("Copying bin file to {}".format(binfile_path))
shutil.copy(filepath, binfile_path)
else:
self.log.error("Invalid FPGA bitfile: {}".format(filepath))
raise RuntimeError("Invalid N310 FPGA bitfile")
# RPC server will reload the periph manager after this.
return True
def update_fpga(self, filepath, metadata):
"""
Update the FPGA image in the filesystem and reload the overlay
:param filepath: path to new FPGA image
:param metadata: Dictionary of strings containing metadata
"""
self.log.trace(f"Updating FPGA with image at {filepath}"\
" (metadata: `{str(metadata)}')")
file_name, file_extension = os.path.splitext(filepath)
self.log.trace("file_name: {}".format(file_name))
# Cut off the period from the file extension
file_extension = file_extension[1:].lower()
if file_extension not in ['bit', 'bin']:
self._log_and_raise(f"Invalid FPGA bitfile: {filepath}")
binfile_path = self.updateable_components['fpga']['path']\
.format(self.device_info.get('product'))
self._verify_compatibility(file_name,
self.updateable_components['fpga'])
if file_extension == "bit":
self.log.trace(
"Converting bit to bin file and writing to {}".format(
binfile_path))
from usrp_mpm.fpga_bit_to_bin import fpga_bit_to_bin
fpga_bit_to_bin(filepath, binfile_path, flip=True)
elif file_extension == "bin":
self.log.trace("Copying bin file to %s", binfile_path)
shutil.copy(filepath, binfile_path)
# RPC server will reload the periph manager after this.
return True
