def __init__(self,p,platform):
self.p = p
self.platform = platform
self.IPCores = util.findTag(self.platform,"IPCores")
self.nodes = util.findTag(self.platform,"nodes")
self.memory = util.findTag(self.platform,"memory")
self.spys = dict({})
def __init__(self, p, aegean):
self.p = p
self.platform = util.findTag(aegean, 'platform')
topology = util.findTag(self.platform, 'topology')
self.routerDepth = topology.get('routerDepth')
self.IPCores = util.findTag(self.platform, 'IPCores')
et = etree.ElementTree(self.platform)
et.write(self.p.GEN_PLAT)
def __init__(self,p,aegean):
self.p = p
self.platform = util.findTag(aegean,'platform')
topology = util.findTag(self.platform,'topology')
self.routerDepth = topology.get('routerDepth')
self.IPCores = util.findTag(self.platform,'IPCores')
et = etree.ElementTree(self.platform)
et.write(self.p.GEN_PLAT)
def parseIPCores(self):
IPCores = list(util.findTag(self.platform, 'IPCores'))
for IPCore in IPCores:
name = IPCore.get('IPType').replace('-', '_')
r = util.findTag(IPCore, 'patmos')
if str(r) == 'None': # The IPCore is not a patmos processor
self.IPCores[name] = IPCore
else: # The IPCore is a patmos processor
self.IPCores[name] = r
def parseIPCores(self):
IPCores = list(util.findTag(self.platform,'IPCores'))
for IPCore in IPCores:
name = IPCore.get('IPType').replace('-','_')
r = util.findTag(IPCore,'patmos')
if str(r) == 'None': # The IPCore is not a patmos processor
self.IPCores[name] = IPCore
else: # The IPCore is a patmos processor
self.IPCores[name] = r
def parseIPCores(self):
IPCores = list(util.findTag(self.platform,'IPCores'))
for i in range(0,len(IPCores)):
IPCore = IPCores[i]
name = IPCore.get('IPType')
r = util.findTag(IPCore,'patmos')
if str(r) == 'None': # The IPCore is not a patmos processor
self.IPCores[name] = IPCore
else: # The IPCore is a patmos processor
self.IPCores[name] = r
def __init__(self,p,platform):
self.p = p
self.platform = platform
self.nodes = util.findTag(self.platform,'nodes')
self.memory = util.findTag(self.platform,'memory')
self.board = util.findTag(self.platform,'board')
self.IOSignals = []
self.IPCores = dict({})
self.Devs = dict({})
self.genIPCores = dict({})
self.genComps = dict({})
self.genFiles = []
self.SPMSizes = []
def __init__(self, p, platform):
self.p = p
self.platform = platform
self.nodes = util.findTag(self.platform, 'nodes')
self.memory = util.findTag(self.platform, 'memory')
self.board = util.findTag(self.platform, 'board')
self.IOSignals = []
self.IPCores = dict({})
self.Devs = dict({})
self.genIPCores = dict({})
self.genComps = dict({})
self.genFiles = []
self.SPMSizes = []
def generateNodes(self):
nodes = list(self.nodes)
for i in range(0, len(nodes)):
node = nodes[i]
IPTypeRef = node.get('IPTypeRef').replace('-', '_')
SPMSize = node.get('SPMSize')
self.SPMSizes.append(self.parseSize(SPMSize))
BootApp = node.get('BootApp')
IPTypeID = IPTypeRef.replace('-', '_')
if str(BootApp) != 'None':
IPTypeID = (IPTypeRef + '-' + BootApp).replace('-', '_')
if IPTypeID not in self.genIPCores: # IPTypeRef -> IPTypeID
IPCore = self.IPCores[IPTypeRef]
b = util.findTag(IPCore, 'bootrom')
if str(b) == 'None' and str(BootApp) == 'None':
if IPCore.tag == 'patmos':
raise SystemExit(
__file__ +
': Error: Patmos specified with no bootapp: ' +
IPTypeRef)
else:
continue
if str(BootApp) == 'None':
BootApp = b.get('app')
# Remove the bootapp tag from the patmos config
IPCore.remove(b)
# Add the Devs to the patmos configuration file
IOsT = util.findTag(IPCore, 'IOs')
if str(IOsT) != 'None':
IOs = list(IOsT)
Devs = etree.Element('Devs')
for j in range(0, len(IOs)):
DevTypeRef = IOs[j].get('DevTypeRef')
Devs.append(self.Devs[DevTypeRef])
IPCore.append(Devs)
# Write the patmos configration file
et = etree.ElementTree(IPCore)
et.write(self.p.TMP_BUILD_PATH + '/' +
IPTypeID.replace('-', '_') +
'.xml') # IPTypeRef ->IPTypeRef + IPTypeID
# Generate the patmos file
self.patmosGen(IPTypeID.replace('-', '_'), BootApp,
self.p.TMP_BUILD_PATH + '/' +
IPTypeID.replace('-', '_') +
'.xml') # IPTypeRef -> IPTypeID
self.genIPCores[IPTypeID.replace(
'-', '_')] = IPCore # IPTypeRef -> IPTypeID
def config(self):
configurations = list(util.findTag(self.application,"configurations"))
for i in range(0,len(configurations)):
#communication = util.findTag(configurations,"communication")
et = etree.ElementTree(configurations[i])
et.write(self.p.GEN_COM+str(i)+'.xml')
self.createSched(len(configurations))
self.createScript()
def config(self):
configurations = list(util.findTag(self.application, "configurations"))
for i in range(0, len(configurations)):
#communication = util.findTag(configurations,"communication")
et = etree.ElementTree(configurations[i])
et.write(self.p.GEN_COM + str(i) + '.xml')
self.createSched(len(configurations))
self.createScript()
def generateNodes(self):
nodes = list(self.nodes)
for i in range(0,len(nodes)):
node = nodes[i]
IPTypeRef = node.get('IPTypeRef')
SPMSize = node.get('SPMSize')
self.SPMSizes.append(self.parseSize(SPMSize))
BootApp = node.get('BootApp')
IPTypeID = IPTypeRef
if str(BootApp) != 'None':
IPTypeID = (IPTypeRef + '-' + BootApp).replace('-','_')
if IPTypeID not in self.genIPCores: # IPTypeRef -> IPTypeID
IPCore = self.IPCores[IPTypeRef]
b = util.findTag(IPCore,'bootrom')
if str(b) == 'None' and str(BootApp) == 'None':
if IPCore.tag == 'patmos':
raise SystemExit(__file__ +': Error: Patmos specified with no bootapp: ' + IPTypeRef)
else:
continue
if str(BootApp) == 'None':
BootApp = b.get('app')
# Remove the bootapp tag from the patmos config
IPCore.remove(b)
# Add the Devs to the patmos configuration file
IOsT = util.findTag(IPCore,'IOs')
if str(IOsT) != 'None':
IOs = list(IOsT)
Devs = etree.Element('Devs')
for j in range(0,len(IOs)):
DevTypeRef = IOs[j].get('DevTypeRef')
Devs.append(self.Devs[DevTypeRef])
IPCore.append(Devs)
# Write the patmos configration file
et = etree.ElementTree(IPCore)
et.write(self.p.TMP_BUILD_PATH + '/' + IPTypeID.replace('-','_') + '.xml') # IPTypeRef ->IPTypeRef + IPTypeID
# Generate the patmos file
self.patmosGen(IPTypeID.replace('-','_'),BootApp,self.p.TMP_BUILD_PATH + '/' + IPTypeID.replace('-','_') + '.xml') # IPTypeRef -> IPTypeID
self.genIPCores[IPTypeID.replace('-','_')] = IPCore # IPTypeRef -> IPTypeID
def parseIOPorts(self):
clock = util.findTag(self.board,'clock')
self.IOSignals.append(['clock',clock.get('name'),'in',1,[clock.get('pin')]])
for port in util.findTag(self.board,'IOPorts'): # For each port
portName = port.get('name')
for signal in port: # For each signal
# Find direction of signal
if signal.tag == 'out':
prefix='o'
elif signal.tag == 'in':
prefix='i'
elif signal.tag == 'inout':
prefix=''
sigName = signal.get('name')
pins = signal.get('pin').split(',')
pins.reverse()
signalName = prefix+portName+'_'+sigName
IOSignal = [portName,signalName,signal.tag,len(pins),pins]
self.IOSignals.append(IOSignal)
def config(self,routerDepth):
# tags = list(self.application)
# for i in range(0,len(tags)):
# if tags[i].tag == 'communication':
# communication = tags[i]
# break
communication = util.findTag(self.application,"communication")
et = etree.ElementTree(communication)
et.write(self.p.GEN_COM)
self.createSched(routerDepth)
self.createScript()
def parseIOPorts(self):
clock = util.findTag(self.board, 'clock')
self.IOSignals.append(
['clock', clock.get('name'), 'in', 1, [clock.get('pin')]])
for port in util.findTag(self.board, 'IOPorts'): # For each port
portName = port.get('name')
for signal in port: # For each signal
# Find direction of signal
if signal.tag == 'out':
prefix = 'o'
elif signal.tag == 'in':
prefix = 'i'
elif signal.tag == 'inout':
prefix = ''
sigName = signal.get('name')
pins = signal.get('pin').split(',')
pins.reverse()
signalName = prefix + portName + '_' + sigName
IOSignal = [portName, signalName, signal.tag, len(pins), pins]
self.IOSignals.append(IOSignal)
def config(self,routerDepth):
# tags = list(self.application)
# for i in range(0,len(tags)):
# if tags[i].tag == 'communication':
# communication = tags[i]
# break
configurations = list(util.findTag(self.application,"configurations"))
for i in range(0,len(configurations)):
#communication = util.findTag(configurations,"communication")
et = etree.ElementTree(configurations[i])
et.write(self.p.GEN_COM+str(i)+'.xml')
self.createSched(routerDepth,len(configurations))
self.createScript()
def generateMemory(self):
if str(self.memory) == 'None':
return
DevTypeRef = self.memory.get('DevTypeRef')
ID = self.memory.get('id')
memory = self.Devs[DevTypeRef]
entity = memory.get('entity')
params = util.findTag(memory,'params')
for i in range(0,len(list(params))):
if params[i].get('name') == 'addr_width':
self.ocpBurstAddrWidth = params[i].get('value')
break
self.ssramGen(entity,self.ocpBurstAddrWidth)
self.arbiterGen(len(self.nodes),self.ocpBurstAddrWidth,32,4)
aegeanCode.writeConfig(self.p.OcpConfFile,self.ocpBurstAddrWidth)
def generateMemory(self):
if str(self.memory) == 'None':
return
DevTypeRef = self.memory.get('DevTypeRef')
ID = self.memory.get('id')
memory = self.Devs[DevTypeRef]
entity = memory.get('entity')
params = util.findTag(memory, 'params')
for i in range(0, len(list(params))):
if params[i].get('name') == 'addr_width':
self.ocpBurstAddrWidth = params[i].get('value')
break
self.ssramGen(entity, self.ocpBurstAddrWidth)
self.arbiterGen(len(self.nodes), self.ocpBurstAddrWidth, 32, 4)
# Add sspm here for generation, since it is a type of memory
aegeanCode.writeConfig(self.p.OcpConfFile, self.ocpBurstAddrWidth)
def getRouterType(self):
return util.findTag(self.platform, "topology").get('routerType')
def generate(self,top):
test = testCode.getTest()
for p in range(0,len(self.nodes)):
node = self.nodes[p]
label = node.get('id')
IPTypeRef = node.get('IPTypeRef')
for IPCore in list(self.IPCores):
if IPCore.get('IPType') == IPTypeRef:
pat = util.findTag(IPCore,'patmos')
IOs = util.findTag(pat,'IOs')
for IO in list(IOs):
DevTypeRef = IO.get('DevTypeRef')
if DevTypeRef == 'Uart':
self.spys[label] = True
testCode.writeSignalSpySignals(test,label)
break
self.spys[label] = False
break
sramName = self.memory.get('DevTypeRef')
testCode.declareSignals(test,self.memory.get('DevTypeRef'))
testCode.bindTop(top,sramName)
test.arch.instComp(top,'top',True)
for p in range(0,len(self.nodes)):
node = self.nodes[p]
IPTypeRef = node.get('IPTypeRef')
BootApp = node.get('BootApp')
if str(BootApp) != 'None':
IPTypeRef = (IPTypeRef +'_'+BootApp).replace('-','_')
label = node.get('id')
if self.spys[label]:
testCode.writeUartSpy(test,label,IPTypeRef)
s = testCode.writeBaudIncBegin()
s+= testCode.writeWait()
for p in range(0,len(self.nodes)):
node = self.nodes[p]
IPTypeRef = node.get('IPTypeRef')
BootApp = node.get('BootApp')
if str(BootApp) != 'None':
IPTypeRef = (IPTypeRef +'_'+BootApp).replace('-','_')
label = node.get('id')
if self.spys[label]:
s+= testCode.writeUartForce(label,1,IPTypeRef)
s+= testCode.writeWait()
for p in range(0,len(self.nodes)):
node = self.nodes[p]
IPTypeRef = node.get('IPTypeRef')
BootApp = node.get('BootApp')
if str(BootApp) != 'None':
IPTypeRef = (IPTypeRef +'_'+BootApp).replace('-','_')
label = node.get('id')
if self.spys[label]:
s+= testCode.writeUartForce(label,0,IPTypeRef)
s+= testCode.writeBaudIncEnd()
test.arch.addToBody(s)
testCode.writeSimMem(test,sramName,self.p.MAIN_MEM)
test.writeComp(self.p.TestFile)
def __init__(self,p,aegean):
self.application = util.findTag(aegean,"application")
self.p = p
def parseDevs(self):
Devs = list(util.findTag(self.platform,'Devs'))
for i in range(0,len(Devs)):
Dev = Devs[i]
name = Dev.get('DevType')
self.Devs[name] = Dev
def parseDevs(self):
Devs = list(util.findTag(self.platform, 'Devs'))
for Dev in Devs:
name = Dev.get('DevType')
self.Devs[name] = Dev
def getTopType(self):
return util.findTag(self.platform,"topology").get('topoType')
def getLinks(self):
return list(util.findTag(self.platform,"topology"))
def __init__(self,p,nocsched):
self.application = util.findTag(nocsched,"application")
self.p = p
def parseDevs(self):
Devs = list(util.findTag(self.platform,'Devs'))
for Dev in Devs:
name = Dev.get('DevType')
self.Devs[name] = Dev
def getNodes(self):
return list(util.findTag(self.platform, "nodes"))
def __init__(self, p, nocsched):
self.application = util.findTag(nocsched, "application")
self.p = p
def generate(self, noc):
self.parseDevs()
self.parseIPCores()
self.parseIOPorts()
self.generateNodes()
self.generateMemory()
self.sspmGen(len(self.nodes))
vlog_src = open(self.p.BUILD_PATH + '/.vlog_src', 'w')
for f in self.genFiles:
if f.endswith('.v'):
vlog_src.write(self.p.BUILD_PATH + f[2:] + ' ')
aegean = aegeanCode.getAegean()
# Adding our own sspm
sspm = aegeanCode.getSSPM(len(self.nodes))
aegean.arch.declComp(sspm)
arbiter = aegeanCode.getArbiter(len(self.nodes),
self.ocpBurstAddrWidth)
aegean.arch.declComp(arbiter)
# Declare Patmos processors
for IPType in self.genIPCores.keys():
IPCore = self.genIPCores[IPType]
IOs = util.findTag(IPCore, 'IOs')
patmos = aegeanCode.getPatmos(IPType, self.ocpBurstAddrWidth)
for IO in list(IOs):
DevTypeRef = IO.get('DevTypeRef')
Dev = self.Devs[DevTypeRef]
ports = util.findTag(Dev, 'ports')
if ports == None:
continue
for port in list(ports):
direction = port.tag
name = port.get('name')
width = port.get('width')
if width != None:
width = int(width)
if direction == "outport":
direction = "out"
elif direction == "inport":
direction = "in"
if ((width == None) or (width == 1)):
patmos.entity.addPort(name, direction, 'std_logic')
else:
patmos.entity.addPort(name, direction,
'std_logic_vector', width)
aegean.arch.declComp(patmos)
self.genComps[IPType] = patmos
aegeanCode.declareSignals(aegean, len(self.nodes))
aegeanCode.setSPMSize(aegean, self.SPMSizes)
for p in range(0, len(self.nodes)):
node = self.nodes[p]
label = node.get('id')
IPType = node.get('IPTypeRef').replace('-', '_')
BootApp = node.get('BootApp')
if str(BootApp) != 'None':
IPType = (IPType + '-' + BootApp).replace('-', '_')
patmos = self.genComps[IPType]
aegeanCode.bindPatmos(patmos, len(self.nodes), p)
IOs = util.findTag(self.genIPCores[IPType], 'IOs')
for IO in list(IOs):
DevTypeRef = IO.get('DevTypeRef')
Dev = self.Devs[DevTypeRef]
ports = util.findTag(Dev, 'ports')
if ports == None:
continue
for port in list(ports):
direction = port.tag
name = port.get('name')
width = port.get('width')
if width != None:
width = int(width)
if direction == "outport":
direction = "out"
elif direction == "inport":
direction = "in"
if ((width == None) or (width == 1)):
aegean.entity.addPort(name + str(p), direction,
'std_logic')
patmos.entity.bindPort(name, name + str(p))
else:
aegean.entity.addPort(name + str(p), direction,
'std_logic_vector', width)
patmos.entity.bindPort(name, name + str(p))
aegean.arch.instComp(patmos, label)
aegean.arch.addToBody(aegeanCode.addSPM())
aegeanCode.bindNoc(noc)
aegean.arch.instComp(noc, 'noc', True)
aegeanCode.bindArbiter(arbiter, len(self.nodes))
aegean.arch.instComp(arbiter, 'arbit')
# Adding our own sspm
aegeanCode.bindSSPM(sspm, len(self.nodes))
aegean.arch.instComp(sspm, 'sspm')
aegean.writeComp(self.p.AegeanFile)
return aegean
def __init__(self,p,aegean):
self.application = util.findTag(aegean,"application")
self.p = p
def getTopType(self):
return util.findTag(self.platform, "topology").get('topoType')
def generateTopLevel(self,aegean):
vendor = self.board.get('vendor')
if vendor == 'Altera':
self.addPinsToQSF()
self.addDeviceToQSF()
self.addDeviceToCDF()
self.addGeneratedFilesToQSF()
elif vendor == 'Xilinx':
#raise SystemExit(__file__ +': Error: Unsupported vendor: ' + vendor)
print("Project files not generated!!")
else:
raise SystemExit(__file__ +': Error: Unsupported vendor: ' + vendor)
top = topCode.getTop()
# One Port for each signal in for loop
for IOSignal in self.IOSignals:
portType = 'std_logic'
if IOSignal[3] > 1:
portType = 'std_logic_vector'
top.entity.addPort(IOSignal[1],IOSignal[2],portType,IOSignal[3]) # (name,direction,portType,len(pins))
top.arch.declConstant('pll_mult','natural',1,'8')
top.arch.declConstant('pll_div','natural',1,'5')
top.arch.declSignal('clk_int','std_logic')
top.arch.declSignal('int_res','std_logic')
top.arch.declSignal('res_reg1,res_reg2','std_logic')
top.arch.declSignal('res_cnt','unsigned',3,'"000"')
top.arch.declSignal('sram_burst_m','ocp_burst_m')
top.arch.declSignal('sram_burst_s','ocp_burst_s')
# Declaration of the Tri state signals
# One tri state for the sram possibly in a for loop for more tri states
for IOSignal in self.IOSignals:
if IOSignal[2] == 'inout':
topCode.writeTriStateSig(top,IOSignal[0],IOSignal[3])
topCode.attr(top)
topCode.reset(top)
sramType = self.memory.get('DevTypeRef')
sramDev = self.Devs[sramType]
sramPorts = util.findTag(sramDev,'ports')
if sramPorts != None:
sramPorts = list(sramPorts)
sramParams = list(util.findTag(sramDev,'params'))
if sramParams != None:
sramParams = list(sramParams)
sramEntity = sramDev.get('entity')
sramIFace = sramDev.get('iface')
# The tristate logic and registers
for IOSignal in self.IOSignals:
if IOSignal[2] == 'inout':
topCode.writeTriState(top,IOSignal[0],sramEntity,IOSignal[1])
sram = Component(sramEntity)
sram.entity.addPort('clk')
sram.entity.addPort('reset')
for param in sramParams:
if param.get('addr_width') != 'None':
addrWidth = param.get('value')
ocp.addSlavePort(sram,sramIFace,addrWidth)
if sramPorts != None:
for port in sramPorts:
width = port.get('width')
if port.tag == 'outport':
if width != None:
sram.entity.addPort(port.get('name'),'out','std_logic_vector',int(width))
else:
sram.entity.addPort(port.get('name'),'out')
elif port.tag == 'inport':
if width != None:
sram.entity.addPort(port.get('name'),'in','std_logic_vector',int(width))
else:
sram.entity.addPort(port.get('name'),'in')
clkPin = 'open'
if sramEntity == 'SSRam32Ctrl':
clkPin = 'oSRAM_CLK'
topCode.pll(top,vendor,clkPin)
top.arch.declComp(sram)
topCode.bindAegean(aegean,len(self.nodes))
top.arch.instComp(aegean,'cmp',True)
topCode.bindSram(sram,sramEntity,'sram_burst_m','sram_burst_s')
top.arch.instComp(sram,'ssram')
top.writeComp(self.p.TopFile)
return top
def getNodes(self):
return list(util.findTag(self.platform,"nodes"))
def generate(self,noc):
self.parseDevs()
self.parseIPCores()
self.parseIOPorts()
self.generateNodes()
self.generateMemory()
vlog_src = open(self.p.BUILD_PATH+'/.vlog_src','w')
for f in self.genFiles:
if f.endswith('.v'):
vlog_src.write(self.p.BUILD_PATH + f[2:] + ' ')
aegean = aegeanCode.getAegean()
# add IO pins
aegean.entity.addPort('led','out','std_logic_vector',9)
#aegean.entity.addPort('txd','out')
#aegean.entity.addPort('rxd','in')
arbiter = aegeanCode.getArbiter(len(self.nodes),self.ocpBurstAddrWidth)
aegean.arch.declComp(arbiter)
for IPType in self.genIPCores.keys():
ledPort = None
uartPort = None
IPCore = self.genIPCores[IPType]
IOs = util.findTag(IPCore,'IOs')
for IO in list(IOs):
DevTypeRef = IO.get('DevTypeRef')
if DevTypeRef == 'Leds':
ledPort = True
ledWidth = 9 # TODO: extract from XML
if DevTypeRef == 'Led':
ledPort = True
ledWidth = 1
elif DevTypeRef == 'Uart':
uartPort = True
patmos = aegeanCode.getPatmos(IPType,ledPort,ledWidth,uartPort,self.ocpBurstAddrWidth)
aegean.arch.declComp(patmos)
self.genComps[IPType] = patmos
aegeanCode.declareSignals(aegean)
aegeanCode.setSPMSize(aegean,self.SPMSizes)
for p in range(0,len(self.nodes)):
patmos = self.nodes[p]
label = patmos.get('id')
IPType = patmos.get('IPTypeRef')
BootApp = patmos.get('BootApp')
if str(BootApp) != 'None':
IPType = (IPType + '-' + BootApp).replace('-','_')
ledPort = None
txdPort = None
rxdPort = None
# TODO: this assumes that core 0 handles all I/O
IOs = util.findTag(self.genIPCores[IPType],'IOs')
for IO in list(IOs):
DevTypeRef = IO.get('DevTypeRef')
if DevTypeRef == 'Leds':
ledPort = 'leds' + str(p)
ledWidth = 9
aegean.entity.addPort('leds' + str(p),'out','std_logic_vector',9)
elif DevTypeRef == 'Led':
ledPort = 'led' + str(p)
aegean.entity.addPort('led' + str(p),'out','std_logic')
ledWidth = 1
elif DevTypeRef == 'Uart':
txdPort = 'txd' + str(p)
rxdPort = 'rxd' + str(p)
aegean.entity.addPort('txd' + str(p),'out')
aegean.entity.addPort('rxd' + str(p),'in')
comp = self.genComps[IPType]
aegeanCode.bindPatmos(comp,len(self.nodes),p,ledPort,txdPort,rxdPort)
aegean.arch.instComp(comp,label)
aegean.arch.addToBody(aegeanCode.addSPM())
aegeanCode.bindNoc(noc)
aegean.arch.instComp(noc,'noc',True)
aegeanCode.bindArbiter(arbiter,len(self.nodes))
aegean.arch.instComp(arbiter,'arbit')
aegean.writeComp(self.p.AegeanFile)
return aegean
def getRouterType(self):
return util.findTag(self.platform,"topology").get('routerType')
def generateTopLevel(self, aegean, audioEnabled):
vendor = self.board.get('vendor')
if vendor == 'Altera':
self.addPinsToQSF()
self.addDeviceToQSF()
self.addDeviceToCDF()
self.addGeneratedFilesToQSF()
elif vendor == 'Xilinx':
#raise SystemExit(__file__ +': Error: Unsupported vendor: ' + vendor)
print("Project files not generated!!")
else:
raise SystemExit(__file__ + ': Error: Unsupported vendor: ' +
vendor)
top = topCode.getTop()
# One Port for each signal in for loop
for IOSignal in self.IOSignals:
portType = 'std_logic'
if IOSignal[3] > 1:
portType = 'std_logic_vector'
top.entity.addPort(
IOSignal[1], IOSignal[2], portType,
IOSignal[3]) # (name,direction,portType,len(pins))
top.arch.declConstant('pll_mult', 'natural', 1, '8')
top.arch.declConstant('pll_div', 'natural', 1, '5')
top.arch.declSignal('clk_int', 'std_logic')
top.arch.declSignal('int_res', 'std_logic')
top.arch.declSignal('res_reg1,res_reg2', 'std_logic')
top.arch.declSignal('res_cnt', 'unsigned', 3, '"000"')
top.arch.declSignal('sram_burst_m', 'ocp_burst_m')
top.arch.declSignal('sram_burst_s', 'ocp_burst_s')
# Declaration of the Tri state signals
# One tri state for the sram possibly in a for loop for more tri states
for IOSignal in self.IOSignals:
if IOSignal[2] == 'inout':
topCode.writeTriStateSig(top, IOSignal[0], IOSignal[3])
#if (IOSignal[0] == 'AudioPins'):
# topCode.writeAudioTriStateSigs(top)
#else:
# topCode.writeTriStateSig(top,IOSignal[0],IOSignal[3])
topCode.attr(top)
topCode.reset(top)
#topCode.audioI2tristate(top)
sramType = self.memory.get('DevTypeRef')
sramDev = self.Devs[sramType]
sramPorts = util.findTag(sramDev, 'ports')
if sramPorts != None:
sramPorts = list(sramPorts)
sramParams = list(util.findTag(sramDev, 'params'))
if sramParams != None:
sramParams = list(sramParams)
sramEntity = sramDev.get('entity')
sramIFace = sramDev.get('iface')
# The tristate logic and registers
for IOSignal in self.IOSignals:
if IOSignal[2] == 'inout': # and (IOSignal[0] != 'AudioPins') ):
topCode.writeTriState(top, IOSignal[0], sramEntity,
IOSignal[1])
sram = Component(sramEntity)
sram.entity.addPort('clk')
sram.entity.addPort('reset')
for param in sramParams:
if param.get('addr_width') != 'None':
addrWidth = param.get('value')
ocp.addSlavePort(sram, sramIFace, addrWidth)
if sramPorts != None:
for port in sramPorts:
width = port.get('width')
if port.tag == 'outport':
if width != None:
sram.entity.addPort(port.get('name'), 'out',
'std_logic_vector', int(width))
else:
sram.entity.addPort(port.get('name'), 'out')
elif port.tag == 'inport':
if width != None:
sram.entity.addPort(port.get('name'), 'in',
'std_logic_vector', int(width))
else:
sram.entity.addPort(port.get('name'), 'in')
clkPin = 'open'
if sramEntity == 'SSRam32Ctrl':
clkPin = 'oSRAM_CLK'
topCode.pll(top, vendor, clkPin)
top.arch.declComp(sram)
topCode.bindAegean(aegean, len(self.nodes), audioEnabled)
top.arch.instComp(aegean, 'cmp', True)
topCode.bindSram(sram, sramEntity, 'sram_burst_m', 'sram_burst_s')
top.arch.instComp(sram, 'ssram')
top.writeComp(self.p.TopFile)
return top
def generate(self,noc):
self.parseDevs()
self.parseIPCores()
self.parseIOPorts()
self.generateNodes()
self.generateMemory()
self.sspmGen(len(self.nodes))
vlog_src = open(self.p.BUILD_PATH+'/.vlog_src','w')
for f in self.genFiles:
if f.endswith('.v'):
vlog_src.write(self.p.BUILD_PATH + f[2:] + ' ')
aegean = aegeanCode.getAegean()
# Adding our own sspm
sspm = aegeanCode.getSSPM(len(self.nodes))
aegean.arch.declComp(sspm)
arbiter = aegeanCode.getArbiter(len(self.nodes),self.ocpBurstAddrWidth)
aegean.arch.declComp(arbiter)
# Declare Patmos processors
for IPType in self.genIPCores.keys():
IPCore = self.genIPCores[IPType]
IOs = util.findTag(IPCore,'IOs')
patmos = aegeanCode.getPatmos(IPType,self.ocpBurstAddrWidth)
for IO in list(IOs):
DevTypeRef = IO.get('DevTypeRef')
Dev = self.Devs[DevTypeRef]
ports = util.findTag(Dev,'ports')
if ports == None:
continue
for port in list(ports):
direction = port.tag
name = port.get('name')
width = port.get('width')
if width != None:
width = int(width)
if direction == "outport":
direction = "out"
elif direction == "inport":
direction = "in"
if ((width == None) or (width == 1)) :
patmos.entity.addPort(name,direction,'std_logic')
else:
patmos.entity.addPort(name,direction,'std_logic_vector',width)
aegean.arch.declComp(patmos)
self.genComps[IPType] = patmos
aegeanCode.declareSignals(aegean,len(self.nodes))
aegeanCode.setSPMSize(aegean,self.SPMSizes)
for p in range(0,len(self.nodes)):
node = self.nodes[p]
label = node.get('id')
IPType = node.get('IPTypeRef').replace('-','_')
BootApp = node.get('BootApp')
if str(BootApp) != 'None':
IPType = (IPType + '-' + BootApp).replace('-','_')
patmos = self.genComps[IPType]
aegeanCode.bindPatmos(patmos,len(self.nodes),p)
IOs = util.findTag(self.genIPCores[IPType],'IOs')
for IO in list(IOs):
DevTypeRef = IO.get('DevTypeRef')
Dev = self.Devs[DevTypeRef]
ports = util.findTag(Dev,'ports')
if ports == None:
continue
for port in list(ports):
direction = port.tag
name = port.get('name')
width = port.get('width')
if width != None:
width = int(width)
if direction == "outport":
direction = "out"
elif direction == "inport":
direction = "in"
if ((width == None) or (width == 1)) :
aegean.entity.addPort(name + str(p),direction,'std_logic')
patmos.entity.bindPort(name,name + str(p))
else:
aegean.entity.addPort(name + str(p),direction,'std_logic_vector',width)
patmos.entity.bindPort(name,name + str(p))
aegean.arch.instComp(patmos,label)
aegean.arch.addToBody(aegeanCode.addSPM())
aegeanCode.bindNoc(noc)
aegean.arch.instComp(noc,'noc',True)
aegeanCode.bindArbiter(arbiter,len(self.nodes))
aegean.arch.instComp(arbiter,'arbit')
# Adding our own sspm
aegeanCode.bindSSPM(sspm,len(self.nodes))
aegean.arch.instComp(sspm,'sspm')
aegean.writeComp(self.p.AegeanFile)
return aegean
def getLinks(self):
return list(util.findTag(self.platform, "topology"))
