'mdefines': '\n'.join(['%s="%s"' % (var,val) for (var,val) in map(util.splitBinding, bsvdefines)]), 'dump_map': ('export PORTAL_DUMP_MAP=' + options.dump_map + '\n') if options.dump_map else '', 'bscflags': ' '.join(options.bscflags), 'xelabflags': ' '.join(options.xelabflags), 'xsimflags': ' '.join(options.xsimflags), 'bsvdefines_list': ' '.join(bsvdefines), 'shared': 'CONNECTAL_SHARED=1' if options.shared else '', 'nohardware': 'CONNECTAL_NOHARDWARE=1' if options.nohardware else '', 'protobuf': ('export PROTODEBUG=%s' % ' '.join(protolist)) if options.protobuf else '', 'bitsmake': bitsmake }) if not options.prtop: for name in options.prvariant: make.write(variantTemplate % {'varname': name}) make.close() util.replaceIfChanged(makename, makename + '.new') configbsvname = os.path.join(project_dir, 'generatedbsv', 'ConnectalProjectConfig.bsv') configbsv = util.createDirAndOpen(configbsvname + '.new', 'w') for (var, val) in map(util.splitBinding, bsvdefines): configbsv.write('`define %(var)s %(val)s\n' % { 'var': var, 'val': val }) configbsv.close() util.replaceIfChanged(configbsvname, configbsvname + '.new') confighname = os.path.join(project_dir, 'jni', 'ConnectalProjectConfig.h') configh = util.createDirAndOpen(confighname + '.new', 'w') configh.write('#ifndef _ConnectalProjectConfig_h\n') configh.write('#define _ConnectalProjectConfig_h\n') configh.write('\n') for (var, val) in map(util.splitBinding, bsvdefines): if re.match("^[0-9]+(.[0-9]*)?$", val):
argparser = argparse.ArgumentParser("Extract BVI schedule lines from bsc-generated verilog.") argparser.add_argument('vfile', help='Verilog files to process', nargs='+') argparser.add_argument('-d', '--dir', help='Output directory', default='.') if __name__=='__main__': options = argparser.parse_args() for vfilename in options.vfile: vf = open(vfilename, 'r') basename = os.path.basename(vfilename) (name, ext) = os.path.splitext(basename) bvifname = os.path.join(options.dir, '%s.bvi' % name) bvif = open(bvifname + '.new', 'w') bvif.write('// BVI Schedule from %s\n' % vfilename) inschedule = False for line in vf: if re.match('^// BVI format method schedule info:', line): inschedule = True elif re.match('^// Ports:', line): inschedule = False elif inschedule: # skip the comment characters bvif.write(line[2:]) else: pass pass bvif.close() ## only update the file if it changed, to help out make util.replaceIfChanged(bvifname, bvifname + '.new') vf.close()
'nohardware': 'CONNECTAL_NOHARDWARE=1' if options.nohardware else '', 'protobuf': ('export PROTODEBUG=%s' % ' '.join(protolist)) if options.protobuf else '', 'bitsmake': bitsmake, 'run_args': ' '.join(options.run_args), 'toolchain': option_info['toolchain'] if 'toolchain' in option_info else '' }) if not options.prtop: for name in options.prvariant: make.write(variantTemplate % {'varname': name}) make.close() util.replaceIfChanged(makename, makename + '.new') configbsvname = os.path.join(project_dir, 'generatedbsv', 'ConnectalProjectConfig.bsv') configbsv = util.createDirAndOpen(configbsvname + '.new', 'w') for (var, val) in map(util.splitBinding, bsvdefines): configbsv.write('`define %(var)s %(val)s\n' % {'var': var, 'val': val}) configbsv.close() util.replaceIfChanged(configbsvname, configbsvname + '.new') confighname = os.path.join(project_dir, 'jni', 'ConnectalProjectConfig.h') configh = util.createDirAndOpen(confighname + '.new', 'w') configh.write('#ifndef _ConnectalProjectConfig_h\n') configh.write('#define _ConnectalProjectConfig_h\n') configh.write('\n') for (var, val) in map(util.splitBinding, bsvdefines):