def convert_to_text(self) -> str: prepare_command = self.get_prepare_command(self.oozie_node, self.params) return render_template(template_name=self.template, prepare_command=prepare_command, task_id=self.name, **self.__dict__)
def convert_to_text(self) -> str: return render_template( template_name="decision.tpl", task_id=self.name, trigger_rule=self.trigger_rule, case_dict=self.case_dict.items(), )
def convert_to_text(self): """Converts subworkflow to text""" op_text = render_template(template_name=self.template, task_id=self.name, **self.__dict__) # If we have found a prepare node, we must reorder nodes. if self.delete_paths or self.mkdir_paths: prep_text = render_template( template_name="prepare.tpl", task_id=self.name + "_reorder", trigger_rule=self.trigger_rule, delete_paths=self.delete_paths, mkdir_paths=self.mkdir_paths, ) return op_text + prep_text return op_text
def convert_to_text(self) -> str: prepare_command = self.get_prepare_command(self.oozie_node, self.params) relations = [Relation(from_task_id=self.name + "_prepare", to_task_id=self.name)] return render_template( template_name=self.template, prepare_command=prepare_command, task_id=self.name, relations=relations, **self.__dict__, )
def write_relations(file, relations, indent=INDENT): """ Write the relations to the given opened file object. These are each written on a new line. """ logging.info("Writing control flow dependencies to file.") relations_str = render_template(template_name="relations.tpl", relations=relations) file.write(textwrap.indent(relations_str, indent * " "))
def process_template_dir(d, suffix, out_path, cfg, target, **kargs): f_list = [] for r, d, fl in os.walk(d): for f in fl: if f.endswith(suffix): tp = os.path.join(r, f) op = os.path.join(out_path, f) if VERBOSE: print('-- Processing %s'%tp) ostr = render_template(tp, cfg=cfg, target=target, kargs=kargs) if len(ostr.strip()) > 0: with open(op, 'w') as of: of.write(ostr) f_list.append(f) return f_list
def write_dag_header(file, dag_name, schedule_interval, start_days_ago, template="dag.tpl"): """ Write the DAG header to the open file specified in the file pointer :param file: Opened file to write to. :param dag_name: Desired name of DAG :param schedule_interval: Desired DAG schedule interval, expressed as number of days :param start_days_ago: Desired DAG start date, expressed as number of days ago from the present day :param template: Desired template to use when creating the DAG header. """ file.write( render_template( template_name=template, dag_name=dag_name, schedule_interval=schedule_interval, start_days_ago=start_days_ago, )) logging.info("Wrote DAG header.")
#import some helper functions which are usefull to have available in the template from math import ceil, floor from utils.datasection_utils import genDataSection, genRandomDataSection #import any user defined vars, functions etc. here user_params = {} if opts.importable: if os.path.isfile(os.path.abspath(opts.importable)): user_import = imp.load_source('', os.path.abspath(opts.importable)) for item in inspect.getmembers(user_import): if item[0][0:2] != '__': user_params[item[0]] = item[1] else: print >> sys.stderr, 'WARNING: %s: unable to locate %s, ignoring!' % ( sys.argv[0], opts.importable) with open(opts.out_file, 'wt') as fp: fp.write( render_template(opts.in_file, cfg=cfg, dataSection=genDataSection, randomDataSection=genRandomDataSection, pow=pow, ceil=ceil, floor=floor, int=int, float=float, imm1=imm1, imm2=imm2, **user_params))
def convert_to_text(self) -> str: return render_template(template_name="kill.tpl", task_id=self.name, trigger_rule=self.trigger_rule)
def convert_to_text(self) -> str: return render_template(template_name=self.template, task_id=self.name, **self.__dict__)
#import some helper functions which are usefull to have available in the template from math import ceil, floor from utils.datasection_utils import genDataSection, genRandomDataSection #import any user defined vars, functions etc. here user_params={} if opts.importable: if os.path.isfile(os.path.abspath(opts.importable)): user_import=imp.load_source('', os.path.abspath(opts.importable)) for item in inspect.getmembers(user_import): if item[0][0:2] != '__': user_params[item[0]]=item[1] else: print >>sys.stderr, 'WARNING: %s: unable to locate %s, ignoring!'%(sys.argv[0],opts.importable) with open(opts.out_file, 'wt') as fp: fp.write(render_template(opts.in_file, cfg=cfg, dataSection=genDataSection, randomDataSection=genRandomDataSection, pow=pow, ceil=ceil, floor=floor, int=int, float=float, imm1=imm1, imm2=imm2, **user_params))
def convert_to_text(self): return render_template(template_name=self.template, **self.__dict__)
def convert_to_text(self): return render_template(template_name="dummy.tpl", task_id=self.name, trigger_rule=self.trigger_rule)
def generate_xil_pcore(cfg, out_dir, rtl_path, def_path, sys_path, target='xilinx', addr_size='1M', sys_type='axilite', ver='v1_00_a'): """ Use configuration cfg to generate a complete Solver RTL package in out_dir. The output package contains: def/ Folder containing the definition files for RTL and testbench. verilog/ Folder containing the Verilog source files. testbench/ Folder containing the testbench files. Keyword arguments: cfg -- A valid Solver configuration object out_dir -- Path to the output directory rtl_path -- A list of paths to the RTL source files. Every .v file under the specified paths is treated as a RTL source template file. def_path -- A list of paths to the definition files. Every .v file under the specified paths is treated as a definition template file. sys_path -- Path to the system wrapper files. Every .v or .vhd file under the specified path is treated as a system HDL file. target -- enable optimization in HDL code for specific target addr_size -- size of target address space sys_type -- type of the system interface """ global VERBOSE ip_name = 'solver_%dpe_'%cfg.pe.size \ + cfg.get_tgt_attr().lower().replace('-', '_') if VERBOSE: print('IP name: %s'%ip_name) utils.sys_utils.mkdir_p(out_dir) ip_out_dir = os.path.join(out_dir, 'pcores', ip_name+'_'+ver) if os.path.exists(ip_out_dir) and os.path.isdir(ip_out_dir): shutil.rmtree(ip_out_dir) vlog_p = os.path.join (ip_out_dir, 'hdl', 'verilog') vhdl_p = os.path.join(ip_out_dir, 'hdl', 'vhdl') data_p = os.path.join (ip_out_dir, 'data') utils.sys_utils.mkdir_p(vlog_p) utils.sys_utils.mkdir_p(vhdl_p) utils.sys_utils.mkdir_p(data_p) addr_size = utils.sys_utils.parse_size_str(addr_size) if addr_size < 1024*1024: print('Address space size should be at least 1M') addr_size = 1024*1024 eff_addr_width = len(bin(addr_size-1)) - 2 if VERBOSE: print('Generating Xilinx pcore for for %s'%cfg.name) if VERBOSE: print('IP output is written to %s'%ip_out_dir) sys_path = os.path.join(sys_path, 'xil_pcore', sys_type) rtl_path.append(sys_path) if VERBOSE: print('System wrapper is in %s'%sys_path) top_vhdl = os.path.join(sys_path, 'solver.vhd') with open(os.path.join(vhdl_p, '%s.vhd'%ip_name), 'w') as of: ostr = render_template(top_vhdl, cfg=cfg, target=target, eff_addr_width=eff_addr_width) if ostr: of.write(ostr) else: raise RuntimeError('No VHDL wrapper found for %s'%ip_name) with open(os.path.join(data_p, '%s_v2_1_0.mpd'%ip_name), 'w') as of: ostr = render_template(os.path.join(sys_path, 'solver.mpd'), cfg=cfg, eff_addr_width=eff_addr_width) if ostr: of.write(ostr) else: raise RuntimeError('No MPD found for %s'%ip_name) vlog_list = [] for d in rtl_path: vlog_list += process_template_dir( d, '.v', vlog_p, cfg, target, eff_addr_width=eff_addr_width) def_list = [] for d in def_path: def_list += process_template_dir( d, '.v', vlog_p, cfg, target) with open(os.path.join(data_p, '%s_v2_1_0.pao'%ip_name), 'w') as of: with open(os.path.join(sys_path, 'solver.pao')) as pao_base: ostr = pao_base.read() for v in vlog_list: ostr+='lib %s_%s %s verilog\n'%(ip_name, ver, v) ostr += 'lib %s_%s %s.vhd vhdl\n'%(ip_name, ver, ip_name) if ostr: of.write(ostr) else: raise RuntimeError('No PAO found for %s'%ip_name) drv_path = os.path.join(sys_path, 'driver') if not os.path.isdir(drv_path): return drv_out_dir = os.path.join(out_dir, 'drivers', ip_name+'_'+ver) if VERBOSE: print('Generating driver for %s to %s'%(ip_name, drv_out_dir)) if os.path.exists(drv_out_dir) and os.path.isdir(drv_out_dir): shutil.rmtree(drv_out_dir) drv_data_p = os.path.join(drv_out_dir, 'data') utils.sys_utils.mkdir_p(drv_data_p) with open(os.path.join(drv_data_p, '%s_v2_1_0.mdd'%ip_name), 'w') as of: ostr = render_template(os.path.join(drv_path, 'solver_device.mdd'), cfg=cfg, eff_addr_width=eff_addr_width) if ostr: of.write(ostr) else: raise RuntimeError('No MDD found for %s'%ip_name) with open(os.path.join(drv_data_p, '%s_v2_1_0.tcl'%ip_name), 'w') as of: ostr = render_template(os.path.join(drv_path, 'solver_device.tcl'), cfg=cfg, eff_addr_width=eff_addr_width) if ostr: of.write(ostr) drv_src_p = os.path.join(drv_out_dir, 'src') drv_src_path = os.path.join(drv_path, 'src') utils.sys_utils.mkdir_p(drv_src_p) if os.path.isdir(drv_src_path): process_template_dir(drv_src_path, '.h', drv_src_p, cfg, target) process_template_dir(drv_src_path, '.c', drv_src_p, cfg, target) with open(os.path.join(drv_src_p, 'Makefile'), 'w') as of: ostr=render_template(os.path.join(drv_src_path, 'Makefile'),cfg=cfg) if ostr: if VERBOSE: print('-- Processing %s'%os.path.join(drv_src_p,'Makefile')) of.write(ostr) else: raise RuntimeError('No Makefile found for %s'%ip_name) else: raise RuntimeError('No driver source file found for %s'%ip_name)