def body(self):
#reg_block_slave model
#sv.cast(model, self.model)
model = self.model
for i in range(1):
default_map = model.INDEX.get_default_map()
status = []
idx = sv.urandom_range(0, 255)
yield model.INDEX.write(status, idx, _map=default_map, parent=self)
status = []
yield model.INDEX.mirror(status, UVM_CHECK, UVM_FRONTDOOR,
default_map, self)
got = model.INDEX.get()
if idx != got:
uvm_error("IDX_ERR", "exp: " + str(idx) + ' got: ' + str(got))
for i in range(5):
status = []
idx = sv.urandom_range(0, (1 << 64) - 1)
yield model.SESSION[i].SRC.write(status,
idx,
_map=default_map,
parent=self)
status = []
yield model.SESSION[i].SRC.mirror(status, UVM_CHECK,
UVM_FRONTDOOR, default_map,
self)
# Randomize the content of 10 random indexed registers
#for i in range(10):
for i in range(1):
idx = sv.urandom_range(0, 255)
data = sv.urandom()
status = []
default_map = model.TABLES[idx].get_default_map()
print("Writing to TABLES idx " + str(idx))
yield model.TABLES[idx].write(status,
data,
_map=default_map,
parent=self)
print("AFTER Writing to TABLES idx " + str(idx))
# Find which indexed registers are non-zero
#for i in range(len(model.TABLES)):
for i in range(1):
data = []
status = []
print("Reading from TABLES idx " + str(i))
yield model.TABLES[i].read(status, data)
if data[0] != 0:
print(sv.sformatf("TABLES[%0d] is 0x%h...", i, data[0]))
def pre_do(self, is_item):
# Update the properties that are relevant to both read and write
_print("calling PRE_DO now: " + self.util_transfer.convert2string())
self.req.size = self.util_transfer.size
self.req.addr = self.util_transfer.addr
self.req.read_write = self.util_transfer.read_write
self.req.error_pos = 1000
self.req.transmit_delay = 0
self.req.data = [0] * self.util_transfer.size
self.req.wait_state = [0] * self.util_transfer.size
for i in range(self.util_transfer.size):
self.req.wait_state[i] = 2
# For reads, populate req with the random "readback" data of the size
# requested in util_transfer
if (self.req.read_write == READ):
new_addr = self.util_transfer.addr + i
if new_addr not in self.m_mem:
self.m_mem[new_addr] = sv.urandom()
self.req.data[i] = self.m_mem[new_addr]