def build_phase(self, phase): _str = [] super().build_phase(phase) arr = [] if UVMConfigDb.get(self, "", "v", arr): self.v = arr[0] arr = [] if UVMConfigDb.get(self, "", "s", arr): self.s = arr[0] if UVMConfigDb.get(self, "", "myaa[foo]", _str): self.myaa["foo"] = _str[0] _str = [] else: uvm_error("NO_CONF_MATCH", "Did not get myaa[foo]") if UVMConfigDb.get(self, "", "myaa[bar]", _str): self.myaa["bar"] = _str[0] _str = [] else: uvm_error("NO_CONF_MATCH", "Did not get myaa[bar]") if UVMConfigDb.get(self, "", "myaa[foobar]", _str): self.myaa["foobar"] = _str[0] _str = [] else: uvm_error("NO_CONF_MATCH", "Did not get myaa[foobar]")
def build_phase(self, phase): super().build_phase(phase) arr = [] if UVMConfigDb.get(self, "", "debug", arr) is True: self.debug = arr[0] UVMConfigDb.set(self, "inst1.u2", "v", 5) UVMConfigDb.set(self, "inst2.u1", "v", 3) UVMConfigDb.set(self, "inst1.*", "s", 0x10) sv.display("%s: In Build: debug = %0d", self.get_full_name(), self.debug) self.inst1 = ClassA("inst1", self) self.inst2 = ClassB("inst2", self) if UVMConfigDb.get(uvm_top, "topenv", "should_match", arr): uvm_info("MATCH_OK", "should_match found from DB", UVM_MEDIUM) else: uvm_error("MATCH_ERROR", "should_match NOT found from DB")
def build_phase(self, phase): super().build_phase(phase) _str = [] if UVMConfigDb.get(self, "", "debug", _str): self.debug = _str[0] else: uvm_error("NO_CONF_MATCH", "Did not get debug") UVMConfigDb.set(self, "u1", "v", 0) sv.display("%s: In Build: debug = %0d", self.get_full_name(), self.debug) self.u1 = ClassC("u1", self)
def build_phase(self, phase): super().build_phase(phase) arr = [] if UVMConfigDb.get(self, "", "debug", arr): self.debug = arr[0] else: uvm_error("NO_CONF_MATCH", "Failed to get 'debug' from config DB") UVMConfigDb.set(self, "*", "v", 0) sv.display("%s: In Build: debug = %0d", self.get_full_name(), self.debug) self.u1 = ClassC("u1", self) self.u2 = ClassC("u2", self)
def run_phase(self, phase): cs_ = UVMCoreService.get() env = None # tb_env phase.raise_objection(self) arr = [] if sv.cast(arr, uvm_top.find("env$"), tb_env): env = arr[0] arr = [] vif = None if UVMConfigDb.get(env, "apb", "vif", arr): vif = arr[0] else: uvm_fatal("NO_VIF", "Could not find apb_vif from config_db") # dut_reset_seq rst_seq rst_seq = dut_reset_seq.type_id.create("rst_seq", self) rst_seq.vif = vif yield rst_seq.start(None) env.model.reset() # uvm_cmdline_processor opts = UVMCmdlineProcessor.get_inst() seq = None # uvm_reg_sequence factory = cs_.get_factory() seq_name = [] opts.get_arg_value("+UVM_REG_SEQ=", seq_name) seq_name = seq_name[0] seq = factory.create_object_by_name(seq_name, self.get_full_name(), "seq") #print("Created obj is " + str(created_obj)) #if not sv.cast(seq, created_obj, uvm_reg_sequence) or seq is None: # uvm_fatal("TEST/CMD/BADSEQ", "Sequence " + seq_name + " is not a known sequence " + str(seq)) seq.model = env.model UVMResourceDb.set("REG::" + env.model.DMA_RAM.get_full_name() + ".*", "NO_REG_TESTS", 1, self) for i in range(len(env.model.SESSION)): UVMResourceDb.set( "REG::" + env.model.SESSION[i].get_full_name() + ".*", "NO_REG_TESTS", 1, self) for i in range(len(env.model.TABLES)): UVMResourceDb.set( "REG::" + env.model.TABLES[i].get_full_name() + ".*", "NO_REG_TESTS", 1, self) yield seq.start(None) phase.drop_objection(self)
async def run_phase(self, phase): status = 0x0 data = 0x0 expected = [] max_val = 0 FIFO = None # fifo_reg regmodel = self.regmodel dut = [] UVMConfigDb.get(None, "DUT_REF", "dut", dut) dut = dut[0] #regmodel.default_map.set_auto_predict(on=True) regmodel.default_map.set_check_on_read(on=False) phase.raise_objection(self) uvm_info("Test", "Resetting DUT and Register Model...", UVM_LOW) rst_seq = dut_reset_seq.type_id.create("rst_seq", self) rst_seq.dut_top = dut await rst_seq.start(None) regmodel.reset() FIFO = regmodel.FIFO max_val = FIFO.capacity() FIFO.set_compare(UVM_CHECK) uvm_info( "FIFO Example", sv.sformatf( "Initializing FIFO reg of max_val size %0d with set()...", max_val), UVM_LOW) expected = [0] * max_val # SET - preload regmodel; remodel now has full FIFO; DUT still empty for i in range(len(expected)): data = sv.urandom() expected[i] = data FIFO.set(data) uvm_info( "FIFO Example", sv.sformatf("Updating DUT FIFO reg with mirror using update()..."), UVM_LOW) # UPDATE - write regmodel contents to DUT; DUT now has full FIFO status = [] await FIFO.update(status) if status[0] == UVM_NOT_OK: uvm_fatal("FIFO Update Error", "Received status UVM_NOT_OK updating DUT") uvm_info( "FIFO Example", sv.sformatf(" Read back DUT FIFO reg into mirror using read()..."), UVM_LOW) print("Before starting to read, FIFO contents: " + str([hex(no) for no in FIFO.fifo])) # READ - read contents of DUT back to regmodel; DUT is empty now, regmodel FULL for i in range(len(expected)): status = [] data = [] await FIFO.read(status, data) if status[0] == UVM_NOT_OK: uvm_fatal( "FIFO Read Error", "Read status UVM_NOT_OK, read {}, data: {}".format( i, data)) else: uvm_info("FIFO Read OK", "Read {}, got data: {}".format(i, data), UVM_LOW) phase.drop_objection(self)