def remove_dangling_wires(benchmarks):
import verilog_parser
for bench_name, url in benchmarks:
verilog = "{0}/{0}_remapped.v".format(bench_name)
print("Removing dangling wires of %s ..." % (bench_name), flush=True)
module = verilog_parser.Module()
module.read_verilog(verilog)
module.construct_circuit_graph()
module.remove_dangling_nets()
verilog = "{0}/{0}.v".format(bench_name)
module.write_verilog(verilog)
def write_def(dest_def, src_lef, src_def, src_v, src_pl):
print ("Parsing LEF: %s" % (src_lef))
the_lef = lef_parser.Lef()
the_lef.read_lef(src_lef)
the_lef.print_stats()
the_lef.m1_layer_name = 'metal1'
the_lef.m2_layer_name = 'metal2'
width_multiplier = the_lef.metal_layer_dict[the_lef.m2_layer_name]
height_multiplier = the_lef.metal_layer_dict[the_lef.m1_layer_name]
dbu_per_micron = the_lef.units_distance_microns
print ("Parsing DEF: %s" % (src_def))
the_def = def_parser.Def()
the_def.read_def(src_def)
the_def.print_stats()
print ("Parsing verilog: %s" % (src_v))
the_verilog = verilog_parser.Module()
the_verilog.read_verilog(src_v)
the_verilog.clock_port = 'iccad_clk' # clock_port will not be used in this code
the_verilog.print_stats()
# Get placement info
print ("Parsing bookshelf pl: %s" %(src_pl))
pl_dict = parse_pl(src_pl) # name : (x, y, orient)
# Create new def file
print ("Write def file")
new_def = deepcopy(the_def)
new_def.file_name = dest_def
new_def.components = list()
for g in the_verilog.instances:
if g.gate_type in ('PI', 'PO'):
continue
name = g.name
gate_type = g.gate_type
is_fixed = False
x, y, orient = pl_dict[name]
x = x * dbu_per_micron * width_multiplier
y = y * dbu_per_micron * height_multiplier
new_def.components.append(
def_parser.DefComponent(name, gate_type, is_fixed, x, y, orient))
new_def.print_stats()
new_def.write_def(dest_def)
def check_tie_cells(src):
""" Check whether the source Verilog contains tie cells. """
module = verilog_parser.Module()
module.read_verilog(src)
module.construct_circuit_graph()
# Remove tie cells
ties = list()
for i in module.instances:
if i.gate_type in TIE_CELLS:
return True
return False
def create_bs_nodes_after_sizing(src_nodes, src_v, src_lef, dest):
# read files
print("Read verilog.")
module = verilog_parser.Module()
module.read_verilog(src_v)
module.clock_port = 'iccad_clk'
module.print_stats()
print("Read lef.")
the_lef = lef_parser.Lef()
the_lef.read_lef(src_lef)
the_lef.print_stats()
with open(src_nodes, 'r') as f:
lines = [l.strip() for l in f]
lines_iter = iter(lines)
#
instance_dict = {i.name: i.gate_type for i in module.instances}
lef_macro_dict = {m.name: m.width for m in the_lef.macros}
site_width = the_lef.sites[0].width
with open(dest, 'w') as f:
for line in lines_iter:
if line == "":
f.write('\n')
continue
tokens = line.split()
instance_name = tokens[0]
try:
gate_type = instance_dict[instance_name]
except KeyError:
f.write(line + '\n')
continue
if gate_type in ('PI', 'PO'):
f.write(line + '\n')
continue
width = lef_macro_dict[gate_type] / site_width
# width = round(width) # FIXME
width = ceil(width) # FIXME
f.write("%-40s %15d %15d\n" % (instance_name, int(width), 9))
def initialize(self):
""" Initialize data structure. """
print("Parsing verilog: %s" % (self.src_v))
self.verilog = verilog_parser.Module()
self.verilog.read_verilog(self.src_v)
self.verilog.construct_circuit_graph()
self.verilog.print_stats()
print("Parsing LEF: %s" % (self.src_lef))
self.lef = lef_parser.Lef()
self.lef.set_m1_layer_name(M1_LAYER_NAME)
self.lef.set_m2_layer_name(M2_LAYER_NAME)
self.lef.read_lef(self.src_lef)
self.lef.print_stats()
self.site_width = self.lef.site_width
self.site_height = self.lef.site_height
self.width_divider = self.lef.metal_layer_dict[M2_LAYER_NAME]
self.height_divider = self.lef.metal_layer_dict[M1_LAYER_NAME]
def initialize(self):
""" Initialize internal data structure of Verilog and LEF. """
def generate_node_dict(verilog, node_dict):
""" Build up a name-to-type dictionary. """
for i in verilog.input_dict.values():
node_dict[i.name] = NodePin(i.name, 'INPUT')
for o in verilog.output_dict.values():
node_dict[o.name] = NodePin(o.name, 'OUTPUT')
for i in verilog.instances:
node_dict[i.name] = NodeComponent(i.name, i.gate_type)
def generate_nets(verilog, nets):
for w in verilog.wire_dict.values():
try:
pins = [(w.source.owner.name, w.source.name)]
except AttributeError:
pins = [("PIN", w.source.name)]
for s in w.sinks:
try:
pins.append((s.owner.name, s.name))
except AttributeError:
pins.append(("PIN", s.name))
nets.append(def_parser.DefNet(w.name, pins))
print ("Parsing verilog: %s" % (self.src_v))
self.verilog = verilog_parser.Module()
self.verilog.read_verilog(self.src_v)
self.verilog.construct_circuit_graph()
self.verilog.print_stats()
self.verilog.check_dangling_nets()
generate_node_dict(self.verilog, self.node_dict)
generate_nets(self.verilog, self.nets)
print ("Parsing LEF: %s" % (self.src_lef))
self.lef = lef_parser.Lef()
self.lef.read_lef(self.src_lef)
self.lef.print_stats()
self.lef.m1_layer_name = 'metal1'
self.lef.m2_layer_name = 'metal2'
def generate_sizer_input(src, dest, dest_sdc, clock='iccad_clk', period='0.0'):
module = verilog_parser.Module()
module.read_verilog(src)
module.clock_port = clock
module.print_stats()
#
inputs = set(module.inputs[:])
outputs = set(module.outputs[:])
wires = set(module.wires[:])
# Remove big blocks and tie cells
blocks, ties, std_cells = list(), list(), list()
for i in module.instances:
if i.gate_type.startswith('block'):
blocks.append(i)
[inputs.add(net) for pin, net in i.output_pin_dict.items()]
[outputs.add(net) for pin, net in i.input_pin_dict.items()]
elif i.gate_type in ('vcc', 'vss'):
ties.append(i)
[inputs.add(net) for pin, net in i.output_pin_dict.items()]
elif i.gate_type in ('PI', 'PO'):
continue
else:
std_cells.append(i)
# Remove floating logic
for net_name, net in module.net_dict.items():
# If the number of connected nodes to the net is 1
if len(net.nodes) == 1:
# Get the node
node = net.nodes[0]
if node.gate_type.startswith('block'):
continue # blocks are already removed
if node.gate_type in ('PI', 'PO'):
continue # don't touch PI/POs
# Find the pin connected to the net
pin_dict = dict(node.input_pin_dict)
pin_dict.update(node.output_pin_dict)
pin = [p for p, n in pin_dict.items() if n == net_name][0]
# Create a dummy port
if pin.startswith('o'):
outputs.add(net_name)
else:
inputs.add(net_name)
# block to block connection?
outputs = outputs - inputs
wires = wires - set(list(inputs) + list(outputs))
# Write verilog
sizer = verilog_parser.Module()
sizer.name, sizer.clock_port = (module.name, clock)
(sizer.inputs, sizer.outputs, sizer.wires) = \
(list(inputs), list(outputs), list(wires))
sizer.instances = std_cells[:]
# Generate circuit graph
sizer.create_pio_nodes()
sizer.construct_circuit_graph()
sizer.print_stats()
sizer.write_verilog(dest)
sizer.write_sdc(dest_sdc, period)
def gen_bookshelf(src_v, src_lef, src_def, fix_big_blocks, clock_port,
remove_clock_port, utilization, dest):
# Parse verilog and lef
print("Parsing verilog: %s" % (src_v))
the_verilog = verilog_parser.Module()
the_verilog.read_verilog(src_v)
the_verilog.clock_port = clock_port
the_verilog.print_stats()
if remove_clock_port:
try:
the_verilog.inputs.remove(clock_port)
the_verilog.clock_port = None
except ValueError:
sys.stderr.write("Specified clock port doesn't exist.\n")
raise SystemExit(-1)
print("Parsing LEF: %s" % (src_lef))
the_lef = lef_parser.Lef()
the_lef.set_m1_layer_name(M1_LAYER_NAME)
the_lef.set_m2_layer_name(M2_LAYER_NAME)
the_lef.read_lef(src_lef)
the_lef.print_stats()
the_def = def_parser.Def()
if src_def is not None:
print("Parsing DEF.")
the_def.read_def(src_def)
the_def.print_stats()
#---------------------------------------
# Hyper graph
#---------------------------------------
# Generate bookshelf nodes
print("Writing nodes.")
total_area_in_bs = write_bookshelf_nodes(dest, the_verilog, the_lef,
the_def, fix_big_blocks)
# Bookshelf nets file - doesn't include the clock net
print("Writing nets.")
write_bookshelf_nets(dest, the_verilog, the_lef, the_def)
# Generate bookshelf wts
print("Writing wts.")
write_bookshelf_wts(dest, the_verilog, the_lef, the_def)
# Placement informatoin
if src_def is not None:
print("Writing scl.")
write_bookshelf_scl(dest, the_lef, the_def)
print("Writing pl.")
write_bookshelf_pl(dest, the_lef, the_def, fix_big_blocks)
else:
# Bookshelf scl file
print("Writing scl.")
pl_width, pl_height = create_bookshelf_scl(dest, the_lef,
total_area_in_bs,
utilization)
# Bookshelf pl file
print("Writing pl.")
create_bookshelf_pl(dest, the_lef, pl_width, pl_height, fix_big_blocks)
if src_def is not None:
print("Writing shapes.")
write_bookshelf_shapes(dest, the_verilog, the_lef, the_def)
print("Writing aux.")
# bookshelf aux
f_aux = open(dest + '.aux', 'w')
f_aux.write("RowBasedPlacement : " \
"%s.nodes %s.nets %s.wts %s.pl %s.scl %s.shapes" \
% (dest, dest, dest, dest, dest, dest))
f_aux.close()
print("Done.\n")