def mkTest(memimg_name=None):
a_shape = (matrix_size, matrix_size)
b_shape = (matrix_size, matrix_size)
c_shape = (a_shape[0], b_shape[0])
n_raw_a = axi.shape_to_length(a_shape)
n_raw_b = axi.shape_to_length(b_shape)
n_a = axi.shape_to_memory_size(a_shape, datawidth)
n_b = axi.shape_to_memory_size(b_shape, datawidth)
a = np.zeros(a_shape, dtype=np.int64)
b = np.zeros(b_shape, dtype=np.int64)
value = 1
for y in range(a_shape[0]):
for x in range(a_shape[1]):
if x == y:
a[y][x] = value
value += 1
else:
a[y][x] = 0
for y in range(b_shape[0]):
for x in range(b_shape[1]):
if x == y:
b[y][x] = 2
else:
b[y][x] = 0
a_addr = a_offset
size_a = n_a * datawidth // 8
b_addr = b_offset
size_b = n_b * datawidth // 8
mem = np.zeros([1024 * 1024 * 8 // axi_datawidth], dtype=np.int64)
axi.set_memory(mem, a, axi_datawidth, datawidth, a_addr)
axi.set_memory(mem, b, axi_datawidth, datawidth, b_addr)
led = mkLed()
m = Module('test')
params = m.copy_params(led)
ports = m.copy_sim_ports(led)
clk = ports['CLK']
rst = ports['RST']
memory = axi.AxiMemoryModel(m, 'memory', clk, rst,
mem_datawidth=axi_datawidth,
memimg=mem, memimg_name=memimg_name)
memory.connect(ports, 'maxi')
# AXI-Slave controller
_saxi = vthread.AXIMLite(m, '_saxi', clk, rst, noio=True)
_saxi.connect(ports, 'saxi')
# Timer
counter = m.Reg('counter', 32, initval=0)
seq = Seq(m, 'seq', clk, rst)
seq(
counter.inc()
)
def ctrl():
for i in range(100):
pass
awaddr = 4
print('# matrix_size = %d' % matrix_size)
_saxi.write(awaddr, matrix_size)
awaddr = 8
print('# a_offset = %d' % a_offset)
_saxi.write(awaddr, a_offset)
awaddr = 12
print('# b_offset = %d' % b_offset)
_saxi.write(awaddr, b_offset)
awaddr = 16
print('# c_offset = %d' % c_offset)
_saxi.write(awaddr, c_offset)
awaddr = 0
start_time = counter
print('# start time = %d' % start_time)
_saxi.write(awaddr, 1)
araddr = 20
v = _saxi.read(araddr)
while v == 0:
v = _saxi.read(araddr)
end_time = counter
print('# end time = %d' % end_time)
time = end_time - start_time
print('# exec time = %d' % time)
all_ok = True
for y in range(matrix_size):
for x in range(matrix_size):
v = memory.read(
c_offset + (y * matrix_size + x) * datawidth // 8)
if y == x and vthread.verilog.NotEql(v, (y + 1) * 2):
all_ok = False
print("NG [%d,%d] = %d" % (y, x, v))
if y != x and vthread.verilog.NotEql(v, 0):
all_ok = False
print("NG [%d,%d] = %d" % (y, x, v))
if all_ok:
print('# verify: PASSED')
else:
print('# verify: FAILED')
vthread.finish()
th = vthread.Thread(m, 'th_ctrl', clk, rst, ctrl)
fsm = th.start()
uut = m.Instance(led, 'uut',
params=m.connect_params(led),
ports=m.connect_ports(led))
simulation.setup_waveform(m, uut)
simulation.setup_clock(m, clk, hperiod=5)
init = simulation.setup_reset(m, rst, m.make_reset(), period=100)
init.add(
Delay(1000000),
Systask('finish'),
)
return m
def mkTest(memimg_name=None):
matrix_size = 16
a_shape = (matrix_size, matrix_size)
b_shape = (matrix_size, matrix_size)
c_shape = (a_shape[0], b_shape[0])
n_raw_a = axi.shape_to_length(a_shape)
n_raw_b = axi.shape_to_length(b_shape)
n_a = axi.shape_to_memory_size(a_shape, datawidth)
n_b = axi.shape_to_memory_size(b_shape, datawidth)
a = np.zeros(a_shape, dtype=np.int32)
b = np.zeros(b_shape, dtype=np.int32)
value = 1
for y in range(a_shape[0]):
for x in range(a_shape[1]):
if x == y:
a[y][x] = value
value += 1
else:
a[y][x] = 0
for y in range(b_shape[0]):
for x in range(b_shape[1]):
if x == y:
b[y][x] = 2
else:
b[y][x] = 0
a_addr = a_offset
size_a = n_a * datawidth // 8
b_addr = b_offset
size_b = n_b * datawidth // 8
mem = np.zeros([1024 * 1024 * 8 // axi_datawidth], dtype=np.int64)
axi.set_memory(mem, a, axi_datawidth, datawidth, a_addr)
axi.set_memory(mem, b, axi_datawidth, datawidth, b_addr)
led = mkLed(matrix_size)
m = Module('test')
params = m.copy_params(led)
ports = m.copy_sim_ports(led)
clk = ports['CLK']
rst = ports['RST']
memory = axi.AxiMemoryModel(m, 'memory', clk, rst,
mem_datawidth=axi_datawidth,
memimg=mem, memimg_name=memimg_name)
memory.connect(ports, 'myaxi')
uut = m.Instance(led, 'uut',
params=m.connect_params(led),
ports=m.connect_ports(led))
simulation.setup_waveform(m, uut)
simulation.setup_clock(m, clk, hperiod=5)
init = simulation.setup_reset(m, rst, m.make_reset(), period=100)
init.add(
Delay(1000000),
Systask('finish'),
)
return m
def mkTest(memimg_name=None):
a_shape = (matrix_size, matrix_size)
b_shape = (matrix_size, matrix_size)
c_shape = (a_shape[0], b_shape[0])
n_raw_a = axi.shape_to_length(a_shape)
n_raw_b = axi.shape_to_length(b_shape)
n_a = axi.shape_to_memory_size(a_shape, datawidth)
n_b = axi.shape_to_memory_size(b_shape, datawidth)
a = np.zeros(a_shape, dtype=np.int64)
b = np.zeros(b_shape, dtype=np.int64)
value = 1
for y in range(a_shape[0]):
for x in range(a_shape[1]):
if x == y:
a[y][x] = value
value += 1
else:
a[y][x] = 0
for y in range(b_shape[0]):
for x in range(b_shape[1]):
if x == y:
b[y][x] = 2
else:
b[y][x] = 0
a_addr = a_offset
size_a = n_a * datawidth // 8
b_addr = b_offset
size_b = n_b * datawidth // 8
mem = np.zeros([1024 * 1024 * 8 // axi_datawidth], dtype=np.int64)
axi.set_memory(mem, a, axi_datawidth, datawidth, a_addr)
axi.set_memory(mem, b, axi_datawidth, datawidth, b_addr)
led = mkLed()
m = Module('test')
params = m.copy_params(led)
ports = m.copy_sim_ports(led)
clk = ports['CLK']
rst = ports['RST']
memory = axi.AxiMemoryModel(m, 'memory', clk, rst,
mem_datawidth=axi_datawidth,
memimg=mem, memimg_name=memimg_name)
memory.connect(ports, 'maxi')
# AXI-Slave controller
_saxi = vthread.AXIMLite(m, '_saxi', clk, rst, noio=True)
_saxi.connect(ports, 'saxi')
# Timer
counter = m.Reg('counter', 32, initval=0)
seq = Seq(m, 'seq', clk, rst)
seq(
counter.inc()
)
def ctrl():
for i in range(100):
pass
awaddr = 4
print('# matrix_size = %d' % matrix_size)
_saxi.write(awaddr, matrix_size)
awaddr = 8
print('# a_offset = %d' % a_offset)
_saxi.write(awaddr, a_offset)
awaddr = 12
print('# b_offset = %d' % b_offset)
_saxi.write(awaddr, b_offset)
awaddr = 16
print('# c_offset = %d' % c_offset)
_saxi.write(awaddr, c_offset)
awaddr = 0
start_time = counter
print('# start time = %d' % start_time)
_saxi.write(awaddr, 1)
araddr = 20
v = _saxi.read(araddr)
while v == 0:
v = _saxi.read(araddr)
end_time = counter
print('# end time = %d' % end_time)
time = end_time - start_time
print('# exec time = %d' % time)
all_ok = True
for y in range(matrix_size):
for x in range(matrix_size):
v = memory.read(
c_offset + (y * matrix_size + x) * datawidth // 8)
if y == x and vthread.verilog.NotEql(v, (y + 1) * 2):
all_ok = False
print("NG [%d,%d] = %d" % (y, x, v))
if y != x and vthread.verilog.NotEql(v, 0):
all_ok = False
print("NG [%d,%d] = %d" % (y, x, v))
if all_ok:
print('# verify: PASSED')
else:
print('# verify: FAILED')
vthread.finish()
th = vthread.Thread(m, 'th_ctrl', clk, rst, ctrl)
fsm = th.start()
uut = m.Instance(led, 'uut',
params=m.connect_params(led),
ports=m.connect_ports(led))
simulation.setup_waveform(m, uut)
simulation.setup_clock(m, clk, hperiod=5)
init = simulation.setup_reset(m, rst, m.make_reset(), period=100)
init.add(
Delay(1000000),
Systask('finish'),
)
return m
