def __init__(self):
self.with_sample(dict(a1=vsc.bit_t(8), a2=vsc.bit_t(8)))
self.cp_a1 = vsc.coverpoint(
self.a1, bins=dict(a=vsc.wildcard_bin("0x8x", "0x6x")))
self.cp_a2 = vsc.coverpoint(
self.a2, bins=dict(a=vsc.wildcard_bin("0x8x", "0x6x")))
def __init__(self):
self.comment = ""
self.exception = vsc.rand_enum_t(illegal_instr_type_e)
self.reserved_c = vsc.rand_enum_t(reserved_c_instr_e)
self.instr_bin = vsc.rand_bit_t(32)
self.opcode = vsc.rand_bit_t(7)
self.compressed = vsc.rand_bit_t(1)
self.func3 = vsc.rand_bit_t(3)
self.func7 = vsc.rand_bit_t(7)
self.has_func3 = vsc.rand_bit_t(1)
self.has_func7 = vsc.rand_bit_t(1)
self.c_op = vsc.rand_bit_t(2)
self.c_msb = vsc.rand_bit_t(3)
self.csrs = []
# Default legal self.opcode for RV32I instructions
self.legal_opcode = vsc.list_t(vsc.bit_t(7))
self.legal_opcode = [3, 15, 19, 23, 35, 55, 99, 51, 103, 115, 111]
# Default legal self.opcode for RV32C instructions
self.legal_c00_opcode = vsc.list_t(vsc.bit_t(3))
self.legal_c00_opcode = [0, 2, 6]
self.legal_c10_opcode = vsc.list_t(vsc.bit_t(3))
self.legal_c10_opcode = [0, 2, 4, 6]
self.xlen = vsc.uint8_t(0)
self.xlen = rcs.XLEN
self.temp_1 = vsc.bit_t(6)
def __init__(self):
self.bit_width = 0
self.reset_val = vsc.bit_t(rcs.XLEN)
self.val = vsc.rand_bit_t(rcs.XLEN)
self.access_type = vsc.enum_t(reg_field_access_t)
self.hard_wired = vsc.bit_t(1)
self.name = ""
def __init__(self):
super().__init__()
self.fs1 = vsc.rand_enum_t(riscv_fpr_t)
self.fs2 = vsc.rand_enum_t(riscv_fpr_t)
self.fs3 = vsc.rand_enum_t(riscv_fpr_t)
self.fd = vsc.rand_enum_t(riscv_fpr_t)
self.has_fs1 = vsc.bit_t(1, 1)
self.has_fs2 = vsc.bit_t(1, 1)
self.has_fs3 = vsc.bit_t(1)
self.has_fd = vsc.bit_t(1, 1)
def __init__(self):
self.instr = None
self.cp_val = vsc.coverpoint(
lambda: self.instr.value[7:5],
cp_t=vsc.bit_t(3),
ignore_bins=dict(invalid_value=vsc.bin(0b101, 0b110)))
self.cp_a = vsc.coverpoint(
lambda: self.instr.a,
cp_t=vsc.bit_t(32),
ignore_bins=dict(invalid_a=vsc.bin(5, 3, 100, 124, 1110)))
def __init__(self):
self.with_sample(dict(a=vsc.bit_t(8)))
self.cp_a = vsc.coverpoint(
lambda: self.a[7:0],
bins=dict(a=vsc.wildcard_bin_array([], "0b1011011x",
"0b0x101010")))
def setup_misa(self):
misa = vsc.bit_t(rcs.XLEN)
if rcs.XLEN == 32:
misa[rcs.XLEN - 1:rcs.XLEN - 2] = 1
elif rcs.XLEN == 64:
misa[rcs.XLEN - 1:rcs.XLEN - 2] = 2
else:
misa[rcs.XLEN - 1:rcs.XLEN - 2] = 3
if cfg.check_misa_init_val:
self.instr_stream.append("{}csrr x15, {}".format(
pkg_ins.indent, hex(privileged_reg_t.MISA)))
for group in rcs.supported_isa:
if group in [
riscv_instr_group_t.RV32C, riscv_instr_group_t.RV64C,
riscv_instr_group_t.RV128C
]:
misa[misa_ext_t.MISA_EXT_C] = 1
elif group in [
riscv_instr_group_t.RV32I, riscv_instr_group_t.RV64I,
riscv_instr_group_t.RV128I
]:
misa[misa_ext_t.MISA_EXT_I] = 1
elif group in [
riscv_instr_group_t.RV32M, riscv_instr_group_t.RV64M
]:
misa[misa_ext_t.MISA_EXT_M] = 1
elif group in [
riscv_instr_group_t.RV32A, riscv_instr_group_t.RV64A
]:
misa[misa_ext_t.MISA_EXT_A] = 1
elif group in [
riscv_instr_group_t.RV32B, riscv_instr_group_t.RV64B
]:
misa[misa_ext_t.MISA_EXT_B] = 1
elif group in [
riscv_instr_group_t.RV32F, riscv_instr_group_t.RV64F,
riscv_instr_group_t.RV32FC
]:
misa[misa_ext_t.MISA_EXT_F] = 1
elif group in [
riscv_instr_group_t.RV32D, riscv_instr_group_t.RV64D,
riscv_instr_group_t.RV32DC
]:
misa[misa_ext_t.MISA_EXT_D] = 1
elif group in [riscv_instr_group_t.RVV]:
misa[misa_ext_t.MISA_EXT_V] = 1
elif group in [
riscv_instr_group_t.RV32X, riscv_instr_group_t.RV64X
]:
misa[misa_ext_t.MISA_EXT_X] = 1
else:
logging.critical("{} is not yet supported".format(group.name))
sys.exit(1)
if privileged_mode_t.SUPERVISOR_MODE.name in rcs.supported_privileged_mode:
misa[misa_ext_t.MISA_EXT_S] = 1
self.instr_stream.append("{}li x{}, {}".format(pkg_ins.indent,
cfg.gpr[0],
hex(misa.get_val())))
self.instr_stream.append("{}csrw {}, x{}".format(
pkg_ins.indent, hex(privileged_reg_t.MISA), cfg.gpr[0]))
def setup_satp(self, instrs):
satp_ppn_mask = vsc.bit_t(rcs.XLEN)
if rcs.SATP_MODE == satp_mode_t.BARE:
return
satp = riscv_privil_reg()
satp.init_reg(privileged_reg_t.SATP)
satp.set_field("MODE", rcs.SATP_MODE)
li0_instr = "li x{}, {}".format(cfg.gpr[0], hex(satp.get_val()))
csrw_instr = "csrw {}, x{} // satp".format(hex(privileged_reg_t.SATP),
cfg.gpr[0])
fld_name = satp.get_field_by_name("PPN")
satp_ppn_mask = hex((2**rcs.XLEN) - 1) >> (rcs.XLEN -
fld_name.bit_width)
# Load the root page table physical address
la_instr = "la x{}, page_table_0".format(cfg.gpr[0])
# Right shift to get PPN at 4k granularity
srli_instr = "srli x{}, x{}, 12".format(cfg.gpr[0], cfg.gpr[0])
li1_instr = "li x{}, {}".format(cfg.gpr[1], hex(satp_ppn_mask))
and_instr = "and x{}, x{}, x{}".format(cfg.gpr[0], cfg.gpr[0],
cfg.gpr[1])
# Set the PPN field for SATP
csrs_instr = "csrs {}, x{} // satp".format(hex(privileged_reg_t.SATP),
cfg.gpr[0])
instrs.extend((li0_instr, csrw_instr, la_instr, srli_instr, li1_instr,
and_instr, csrs_instr))
def __init__(self):
# Instruction attributes
self.group = vsc.enum_t(riscv_instr_group_t)
self.format = vsc.enum_t(riscv_instr_format_t)
self.category = vsc.enum_t(riscv_instr_category_t)
self.instr_name = vsc.enum_t(riscv_instr_name_t)
self.imm_type = vsc.enum_t(imm_t)
self.imm_len = vsc.bit_t(5)
# Operands
self.csr = vsc.rand_bit_t(12)
self.rs2 = vsc.rand_enum_t(riscv_reg_t)
self.rs1 = vsc.rand_enum_t(riscv_reg_t)
self.rd = vsc.rand_enum_t(riscv_reg_t)
self.imm = vsc.rand_bit_t(32)
# Helper Fields
self.imm_mask = vsc.uint32_t(0xffffffff)
self.is_branch_target = None
self.has_label = 1
self.atomic = 0
self.branch_assigned = None
self.process_load_store = 1
self.is_compressed = None
self.is_illegal_instr = None
self.is_hint_instr = None
self.is_floating_point = None
self.imm_str = None
self.comment = ""
self.label = ""
self.is_local_numeric_label = None
self.idx = -1
self.has_rs1 = vsc.bit_t(1)
self.has_rs2 = vsc.bit_t(1)
self.has_rd = vsc.bit_t(1)
self.has_imm = vsc.bit_t(1)
self.has_rs1 = 1
self.has_rs2 = 1
self.has_rd = 1
self.has_imm = 1
self.shift_t = vsc.uint32_t(0xffffffff)
self.mask = 32
self.XLEN = vsc.uint32_t(
32) # XLEN is used in constraint throughout the generator.
# Hence, XLEN should be of PyVSC type in order to use it in a constraint block
self.XLEN = rcs.XLEN
def __init__(self):
# Number of programs in the call stack
self.program_cnt = vsc.int_t(10)
# Handles of all programs
self.program_h = []
# Maximum call stack level
self.max_stack_level = vsc.int_t(50)
# Call stack level of each program
self.stack_level = vsc.randsz_list_t(vsc.bit_t(11))
def __init__(self):
# Define the parameters accepted by the sample function
self.with_sample({
'a' : vsc.bit_t(8),
'b' : vsc.bit_t(8)
})
self.a_cp = vsc.coverpoint( self.a, bins={
# Create 4 bins across the space 0..255
'a_bins': vsc.bin_array([4], [0,255])
})
self.b_cp = vsc.coverpoint(self.b, bins={
# Create one bin for each value (1,2,4,8)
'b_bins': vsc.bin_array([], 1, 2, 4, 8)
})
self.ab_cross = vsc.cross([self.a_cp, self.b_cp])
def __init__(self):
self.addr = rand_bit_t(16)
self.read_write = rand_enum_t(ubus_read_write_enum)
self.size = rand_bit_t(32)
self.data = vsc.randsz_list_t(vsc.uint8_t())
self.wait_state = vsc.randsz_list_t(vsc.bit_t(4))
self.error_pos = rand_bit_t(32)
self.transmit_delay = rand_bit_t(32)
self.master = ""
self.slave = ""
def init_floating_point_gpr_with_dpf(self, int_floating_gpr):
imm = vsc.bit_t(64)
imm = self.get_rand_dpf_value()
int_gpr1 = cfg.gpr[0].value
int_gpr2 = cfg.gpr[1].value
li_instr0 = "{}li x{}, {}".format(pkg_ins.indent, int_gpr1, imm[63:32])
# shift to upper 32bits
for _ in range(2):
slli_instr = "{}slli x{}, x{}, 16".format(pkg_ins.indent, int_gpr1, int_gpr1)
li_instr1 = "{}li x{}, {}".format(pkg_ins.indent, int_gpr2, imm[31:0])
or_instr = "{}or x{}, x{}, x{}".format(pkg_ins.indent, int_gpr2, int_gpr2, int_gpr1)
fmv_instr = "{}fmv.d.x f{}, x{}".format(pkg_ins.indent, int_floating_gpr, int_gpr2)
self.instr_stream.extend((li_instr0, slli_instr, li_instr1, or_instr, fmv_instr))
def setup_misa(self):
misa = vsc.bit_t(rcs.XLEN)
if rcs.XLEN == 32:
misa[rcs.XLEN - 1:rcs.XLEN - 2] = 1
elif rcs.XLEN == 64:
misa[rcs.XLEN - 1:rcs.XLEN - 2] = 2
else:
misa[rcs.XLEN - 1:rcs.XLEN - 2] = 3
if cfg.check_misa_init_val:
self.instr_stream.append("{}csrr x15, {}".format(pkg_ins.indent,
hex(privileged_reg_t.MISA)))
for i in range(len(rcs.supported_isa)):
if rcs.supported_isa[i] in [riscv_instr_group_t.RV32C.name,
riscv_instr_group_t.RV64C.name,
riscv_instr_group_t.RV128C.name]:
misa[misa_ext_t.MISA_EXT_C] = 1
elif rcs.supported_isa[i] in [riscv_instr_group_t.RV32I.name,
riscv_instr_group_t.RV64I.name,
riscv_instr_group_t.RV128I.name]:
misa[misa_ext_t.MISA_EXT_I] = 1
elif rcs.supported_isa[i] in [riscv_instr_group_t.RV32M.name,
riscv_instr_group_t.RV64M.name]:
misa[misa_ext_t.MISA_EXT_M] = 1
elif rcs.supported_isa[i] in [riscv_instr_group_t.RV32A.name,
riscv_instr_group_t.RV64A.name]:
misa[misa_ext_t.MISA_EXT_A] = 1
elif rcs.supported_isa[i] in [riscv_instr_group_t.RV32B.name,
riscv_instr_group_t.RV64B.name]:
misa[misa_ext_t.MISA_EXT_B] = 1
elif rcs.supported_isa[i] in [riscv_instr_group_t.RV32F.name,
riscv_instr_group_t.RV64F.name,
riscv_instr_group_t.RV32FC.name]:
misa[misa_ext_t.MISA_EXT_F] = 1
elif rcs.supported_isa[i] in [riscv_instr_group_t.RV32D.name,
riscv_instr_group_t.RV64D.name,
riscv_instr_group_t.RV32DC.name]:
misa[misa_ext_t.MISA_EXT_D] = 1
elif rcs.supported_isa[i] in [riscv_instr_group_t.RVV.name]:
misa[misa_ext_t.MISA_EXT_V] = 1
elif rcs.supported_isa[i] in [riscv_instr_group_t.RV32X.name,
riscv_instr_group_t.RV64X.name]:
misa[misa_ext_t.MISA_EXT_X] = 1
else:
logging.error("{} is not yet supported".format(rcs.supported_isa[i]))
if privileged_mode_t.SUPERVISOR_MODE.name in rcs.supported_privileged_mode:
misa[misa_ext_t.MISA_EXT_S] = 1
self.instr_stream.append("{}li x{}, {}".format(pkg_ins.indent, cfg.gpr[0].value,
hex(misa.get_val())))
self.instr_stream.append("{}csrw {}, x{}".format(pkg_ins.indent,
hex(privileged_reg_t.MISA), cfg.gpr[0].value))
def __init__(self):
self.x = vsc.rand_attr(vsc.bit_t(16))
def __init__(self):
self.x = vsc.attr(vsc.bit_t(16, i=0x12345))
def __init__(self):
self.reg_name = vsc.enum_t(privileged_reg_t)
self.offset = vsc.bit_t(12)
self.privil_level = vsc.enum_t(privileged_level_t)
self.val = vsc.bit_t(rcs.XLEN)
self.fld = vsc.rand_list_t(vsc.attr(riscv_reg_field()))
def __init__(self):
self.a = vsc.rand_list_t(vsc.bit_t(7),4)
def __init__(self):
super().__init__()
self.rs3 = vsc.rand_enum_t(riscv_reg_t)
self.has_rs3 = vsc.bit_t(1)
def __init__(self):
self.with_sample(dict(a=vsc.bit_t(8)))
self.a_cp = vsc.coverpoint(
self.a, bins=dict(a=vsc.bin_array([], [1, 16])))
def __init__(self):
self.with_sample(dict(a=vsc.bit_t(8)))
self.cp_a = vsc.coverpoint(
self.a, bins=dict(a=vsc.wildcard_bin_array([], "0x8x")))
def post_randomize(self):
mask = vsc.bit_t(rcs.XLEN, 2**rcs.XLEN - 1)
mask = mask >> (rcs.XLEN - self.bit_width)
self.val = mask & self.val
def __init__(self):
self.x = vsc.list_t(vsc.bit_t(16), init=[0, 1])
def __init__(self):
super().__init__()
self.a = vsc.rand_bit_t(8)
self.b = vsc.rand_bit_t(8)
self.temp = vsc.list_t(vsc.bit_t(8))
self.temp = [1, 2, 3, 4, 5, 6, 7, 8, 9]
def __init__(self):
self.fixed = vsc.rand_list_t(vsc.bit_t(8), sz=4)
self.dynamic = vsc.randsz_list_t(vsc.bit_t(8))
self.queue = vsc.randsz_list_t(vsc.bit_t(8))
def get_rand_dpf_value(self):
value = vsc.bit_t(64)
# TODO randcase
return value
def __init__(self):
self.with_sample(dict(a=vsc.bit_t(8)))
self.cp_a = vsc.coverpoint(
self.a, bins=dict(a=vsc.wildcard_bin((0x80, 0xF0))))
def __init__(self):
self.arr = vsc.rand_list_t(vsc.bit_t(8), sz=16)
def __init__(self):
# Program counter (PC) of the instruction
self.pc = vsc.bit_t(rcs.XLEN)
self.instr = None
# self.gpr = None # destination operand of the instruction
self.binary = vsc.bit_t(32) # Instruction binary
# self.mode = None # Instruction mode
self.trace = "None" # String representation of the instruction
# self.operands = "None" # Instruction operands (srcss/dests)
# self.pad = None # Not used
self.rs1_value = vsc.int_t(rcs.XLEN)
self.rs2_value = vsc.int_t(rcs.XLEN)
self.rs3_value = vsc.int_t(rcs.XLEN)
self.rd_value = vsc.int_t(rcs.XLEN)
self.fs1_value = vsc.int_t(rcs.XLEN)
self.fs2_value = vsc.int_t(rcs.XLEN)
self.fs3_value = vsc.int_t(rcs.XLEN)
self.fd_value = vsc.int_t(rcs.XLEN)
self.mem_addr = vsc.int_t(rcs.XLEN)
self.unaligned_pc = 0
self.unaligned_mem_access = 0
self.compressed = 0
self.branch_hit = 0
self.div_result = None
self.rs1_sign = 0
self.rs2_sign = 0
self.rs3_sign = 0
self.fs1_sign = 0
self.fs2_sign = 0
self.fs3_sign = 0
self.imm_sign = 0
self.rd_sign = 0
self.fd_sign = 0
self.gpr_hazard = hazard_e.NO_HAZARD
self.lsu_hazard = hazard_e.NO_HAZARD
self.rs1_special_value = 0
self.rs2_special_value = 0
self.rs3_special_value = 0
self.rd_special_value = 0
self.imm_special_value = 0
self.compare_result = 0
self.logical_similarity = 0
self.group = None
self.format = None
self.category = None
self.imm_type = None
self.csr = vsc.bit_t(12)
''' TODO: rs2, rs1, rd, group, format, category, imm_type will be
changed to vsc.enum_t once the issue with set/get_val is fixed '''
self.rs2 = 0
self.rs1 = 0
self.rd = 0
self.imm = vsc.int_t(32)
self.has_rs1 = 1
self.has_rs2 = 1
self.has_rd = 1
self.has_imm = 1
self.imm_len = 0
def __init__(self):
self.program_id = vsc.rand_bit_t(16)
self.call_stack_level = vsc.rand_uint32_t()
self.sub_program_id = vsc.rand_list_t(vsc.bit_t(16))
