Example #1
0
    def setup_compressor_memory (self,
                                 num_sensor,
                                 frame_sa,
                                 frame_sa_inc,
                                 last_frame_num,
                                 frame_full_width,
                                 window_width,
                                 window_height,
                                 window_left,
                                 window_top,
                                 byte32,
                                 tile_width,
                                 tile_vstep, # = 16
                                 tile_height, #= 18
                                 extra_pages,
                                 disable_need):
        """
        Setup memory controller for a compressor channel
        @param num_sensor -       sensor port number (0..3)
        @param frame_sa -         22-bit frame start address ((3 CA LSBs==0. BA==0)
        @param frame_sa_inc -     22-bit frame start address increment  ((3 CA LSBs==0. BA==0)
        @param last_frame_num -   16-bit number of the last frame in a buffer
        @param frame_full_width - 13-bit Padded line length (8-row increment), in 8-bursts (16 bytes)
        @param window_width -     13-bit - in 8*16=128 bit bursts
        @param window_height -    16-bit window height (in scan lines)
        @param window_left -      13-bit window left margin in 8-bursts (16 bytes)
        @param window_top -       16-bit window top margin (in scan lines
        @param byte32 -           32-byte columns
        @param tile_width         tile width,
        @param tile_vstep         tile vertical step in pixel rows (JPEG18/jp4 = 16)
        @param tile_height        tile height: 18 for color JPEG, 16 fore JP$ flavors,
        @param extra_pages        extra pages needed (1)
        @param disable_need       disable need (preference to sensor channels - they can not wait
        """
#        tile_vstep = 16
#        tile_height= 18
        base_addr = vrlg.MCONTR_CMPRS_BASE + vrlg.MCONTR_CMPRS_INC * num_sensor;
        mode=   x393_mcntrl.func_encode_mode_scan_tiled(
                                   skip_too_late = False,
                                   disable_need = disable_need,
                                   repetitive=    True,
                                   single =       False,
                                   reset_frame =  False,
                                   byte32 =       byte32,
                                   keep_open =    False,
                                   extra_pages =  extra_pages,
                                   write_mem =    False,
                                   enable =       True,
                                   chn_reset =    False)
        self.x393_axi_tasks.write_control_register(
                                    base_addr + vrlg.MCNTRL_TILED_STARTADDR,
                                    frame_sa) # RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0)
        self.x393_axi_tasks.write_control_register(
                                    base_addr + vrlg.MCNTRL_TILED_FRAME_SIZE,
                                    frame_sa_inc)
        self.x393_axi_tasks.write_control_register(
                                    base_addr + vrlg.MCNTRL_TILED_FRAME_LAST,
                                    last_frame_num)
        self.x393_axi_tasks.write_control_register(
                                    base_addr + vrlg.MCNTRL_TILED_FRAME_FULL_WIDTH,
                                    frame_full_width)
        self.x393_axi_tasks.write_control_register(
                                    base_addr + vrlg.MCNTRL_TILED_WINDOW_WH,
                                    ((window_height & 0xffff) << 16) | (window_width & 0xffff)) #/WINDOW_WIDTH + (WINDOW_HEIGHT<<16));
        self.x393_axi_tasks.write_control_register(
                                    base_addr + vrlg.MCNTRL_TILED_WINDOW_X0Y0,
                                    ((window_top & 0xffff) << 16) | (window_left & 0xffff)) #WINDOW_X0+ (WINDOW_Y0<<16));
        self.x393_axi_tasks.write_control_register(
                                    base_addr + vrlg.MCNTRL_TILED_WINDOW_STARTXY,
                                    0)
        self.x393_axi_tasks.write_control_register(
                                    base_addr + vrlg.MCNTRL_TILED_TILE_WHS,
                                    ((tile_vstep & 0xff) <<16) | ((tile_height & 0xff) <<8) | (tile_width & 0xff)) #//(tile_height<<8)+(tile_vstep<<16));
        self.x393_axi_tasks.write_control_register(
                                    base_addr + vrlg.MCNTRL_TILED_MODE,
                                    mode); 
Example #2
0
    def membridge_rw (self,
                      write_ddr3,                                   # input        write_ddr3;
#                      extra_pages,                                 # input  [1:0] extra_pages;
                      frame_start_addr =  None,                     # input [21:0] frame_start_addr;
                      window_full_width = None,                     # input [15:0] window_full_width;# 13 bit - in 8*16=128 bit bursts
                      window_width =      None,                     # input [15:0] window_width;     # 13 bit - in 8*16=128 bit bursts
                      window_height =     None,                     # input [15:0] window_height;    # 16 bit (only 14 are used here)
                      window_left =       None,                     # input [15:0] window_left;
                      window_top =        None,                     # input [15:0] window_top;
                      start64 =           0,                        # input [28:0] start64;          # relative start address of the transfer (set to 0 when writing lo_addr64)
                      lo_addr64 =         None,                     # input [28:0] lo_addr64;        # low address of the system memory range, in 64-bit words 
                      size64 =            None,                     # input [28:0] size64;           # size of the system memory range in 64-bit words
                      cont =              False,                    # input        continue;         # 0 start from start64, 1 - continue from where it was
                      cache =             0x3,
                      wait_ready =        False,
                      quiet=1):
        '''
        Set up and run data transfer between the system and videobuffer memory
        @param write_ddr3 True: from system memory to ddr3, False - from ddr3 to system memory
        @param frame_start_addr [21:0] Frame start address in video buffer  RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0)
        @param window_full_width  padded frame width in 8-word (16 byte) bursts - increment to the next line (after bank), currently 13 bits
        @param window_width window width in 16-byte bursts to be transferred, currently 13 bits (0 - maximal width 0f 2<<13)
        @param window_height window height to be transferred, 14 bits
        @param window_left window to be transferred left margin (relative to frame) in 16-byte bursts (13 bits)
        @param window_top window to be transferred top margin (relative to frame) 16-bit
        @param start64 start of transfer address in system memory, relative to the start of region (in 8-bytes)
        @param lo_addr64 start of the system memory buffer, in 8-bytes (byte_address >>3), 29 bits 
        @param size64 size of the transfer buffer in the system memory, in 8-bytes. Transfers will roll over to lo_addr64. 29 bits.
        @param cont True: continue from  the same address in the system memory, where the previous transfer stopped. False - start from lo_addr64+start64
        @param cache bits[3:0] - ARCHACHE, AWCACHE (default 0x3), bit[4] - debug mode, when each 64-bit word high 16 bits is replaced with:
               bits[63:60] - transfer id (incrementing each new transfer), bits[59:58]==0, [57:56] - mchtrl page number, [45:48] FIFO count (wcount)
        @param wait_ready poll status to see if the command finished
        @param quiet Reduce output
        '''
        if frame_start_addr is None:
            frame_start_addr =  vrlg.FRAME_START_ADDRESS # input [21:0] frame_start_addr;
        if window_full_width is None:
            window_full_width = vrlg.FRAME_FULL_WIDTH    # input [15:0] window_full_width;# 13 bit - in 8*16=128 bit bursts
        if window_width is None:
            window_width =      vrlg.WINDOW_WIDTH        # input [15:0] window_width;     # 13 bit - in 8*16=128 bit bursts
        if window_height is None:
            window_height =     vrlg.WINDOW_HEIGHT       # input [15:0] window_height;    # 16 bit (only 14 are used here)
        if window_left is None:
            window_left =       vrlg.WINDOW_X0           # input [15:0] window_left;
        if window_top is None:
            window_top =        vrlg.WINDOW_Y0           # input [15:0] window_top;
        if lo_addr64 is None:
            lo_addr64 =         BUFFER_ADDRESS//8        # input [28:0] lo_addr64;        # low address of the system memory range, in 64-bit words 
        if size64 is None:
            size64 =            BUFFER_LEN//8            # input [28:0] size64;           # size of the system memory range in 64-bit words
        
        window_height &= 0x3fff
        if window_height == 0:
            window_height = 0x4000
        window_width &= 0x1fff
        if window_width == 0:
            window_width = 0x2000
            
        if quiet <2:
            print("====== test_afi_rw: write=%s, frame_start=0x%x, window_full_width=%d, window_width=%d, window_height=%d, window_left=%d, window_top=%d"%(
                                      str(write_ddr3),  frame_start_addr, window_full_width,   window_width, window_height, window_left, window_top));
            print("len64=0x%x,  width64=0x%x, start64=0x%x, lo_addr64=0x%x, size64=0x%x, cache=0x%x"%(
                  (window_width << 1)*window_height,
                  (window_width << 1),
                  start64, lo_addr64, size64,cache))
        '''    
        mode=   func_encode_mode_scanline(
                    0, # extra_pages,
                    write_ddr3, # write_mem,
                    1, # enable
                    0)  # chn_reset
        '''
        mode=   x393_mcntrl.func_encode_mode_scan_tiled(
                                   disable_need = False,
                                   repetitive=    True,
                                   single =       False,
                                   reset_frame =  False,
                                   extra_pages =  0,
                                   write_mem =    write_ddr3,
                                   enable =       True,
                                   chn_reset =    False)

#        self.x393_axi_tasks.write_control_register(vrlg.MEMBRIDGE_ADDR + vrlg.MEMBRIDGE_WIDTH64,    width64);    
#        self.x393_axi_tasks.write_control_register(vrlg.MCNTRL_SCANLINE_CHN1_ADDR + vrlg.MCNTRL_SCANLINE_MODE,             0); # reset channel, including page address
        self.x393_axi_tasks.write_control_register(vrlg.MCNTRL_SCANLINE_CHN1_ADDR + vrlg.MCNTRL_SCANLINE_STARTADDR,        frame_start_addr) # RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0) 
        self.x393_axi_tasks.write_control_register(vrlg.MCNTRL_SCANLINE_CHN1_ADDR + vrlg.MCNTRL_SCANLINE_FRAME_FULL_WIDTH, window_full_width);
        self.x393_axi_tasks.write_control_register(vrlg.MCNTRL_SCANLINE_CHN1_ADDR + vrlg.MCNTRL_SCANLINE_WINDOW_WH,        (window_height << 16) | window_width) # WINDOW_WIDTH + (WINDOW_HEIGHT<<16));
        self.x393_axi_tasks.write_control_register(vrlg.MCNTRL_SCANLINE_CHN1_ADDR + vrlg.MCNTRL_SCANLINE_WINDOW_X0Y0,      (window_top << 16) | window_left)     # WINDOW_X0+ (WINDOW_Y0<<16));
        self.x393_axi_tasks.write_control_register(vrlg.MCNTRL_SCANLINE_CHN1_ADDR + vrlg.MCNTRL_SCANLINE_WINDOW_STARTXY,   0)
        self.x393_axi_tasks.write_control_register(vrlg.MCNTRL_SCANLINE_CHN1_ADDR + vrlg.MCNTRL_SCANLINE_MODE,             mode) 
        self.x393_axi_tasks.configure_channel_priority(1,0);    # lowest priority channel 1
        self.x393_axi_tasks.enable_memcntrl_en_dis(1,1);
#        write_control_register(test_mode_address,            TEST01_START_FRAME);
        self.afi_setup(0)
        self.membridge_setup(
            (window_width << 1)*window_height, # ((window_width[12:0]==0)? 15'h4000 : {1'b0,window_width[12:0],1'b0})*window_height[13:0], #len64,
            (window_width << 1),               # (window_width[12:0]==0)? 29'h4000 : {15'b0,window_width[12:0],1'b0}, # width64,
            start64,
            lo_addr64,
            size64,
            cache,
            quiet)
        self.membridge_start (cont)         
# just wait done (default timeout = 10 sec)
        if wait_ready:
            self.x393_axi_tasks.wait_status_condition ( # may also be read directly from the same bit of mctrl_linear_rw (address=5) status
                vrlg.MEMBRIDGE_STATUS_REG, # MCNTRL_TEST01_STATUS_REG_CHN3_ADDR,
                vrlg.MEMBRIDGE_ADDR +vrlg.MEMBRIDGE_STATUS_CNTRL, # MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN3_STATUS_CNTRL,
                vrlg.DEFAULT_STATUS_MODE,
                2 << vrlg.STATUS_2LSB_SHFT, # bit 24 - busy, bit 25 - frame done
                2 << vrlg.STATUS_2LSB_SHFT,  # mask for the 4-bit page number
                0, # equal to
                1); # synchronize sequence number
Example #3
0
    def membridge_rw(
            self,
            write_ddr3,  # input        write_ddr3;
            #                      extra_pages,                                 # input  [1:0] extra_pages;
        frame_start_addr=None,  # input [21:0] frame_start_addr;
            window_full_width=None,  # input [15:0] window_full_width;# 13 bit - in 8*16=128 bit bursts
            window_width=None,  # input [15:0] window_width;     # 13 bit - in 8*16=128 bit bursts
            window_height=None,  # input [15:0] window_height;    # 16 bit (only 14 are used here)
            window_left=None,  # input [15:0] window_left;
            window_top=None,  # input [15:0] window_top;
            start64=0,  # input [28:0] start64;          # relative start address of the transfer (set to 0 when writing lo_addr64)
            lo_addr64=None,  # input [28:0] lo_addr64;        # low address of the system memory range, in 64-bit words 
            size64=None,  # input [28:0] size64;           # size of the system memory range in 64-bit words
            cont=False,  # input        continue;         # 0 start from start64, 1 - continue from where it was
            cache=0x3,
            wait_ready=False,
            quiet=1):
        '''
        Set up and run data transfer between the system and videobuffer memory
        @param write_ddr3 True: from system memory to ddr3, False - from ddr3 to system memory
        @param frame_start_addr [21:0] Frame start address in video buffer  RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0)
        @param window_full_width  padded frame width in 8-word (16 byte) bursts - increment to the next line (after bank), currently 13 bits
        @param window_width window width in 16-byte bursts to be transferred, currently 13 bits (0 - maximal width 0f 2<<13)
        @param window_height window height to be transferred, 14 bits
        @param window_left window to be transferred left margin (relative to frame) in 16-byte bursts (13 bits)
        @param window_top window to be transferred top margin (relative to frame) 16-bit
        @param start64 start of transfer address in system memory, relative to the start of region (in 8-bytes)
        @param lo_addr64 start of the system memory buffer, in 8-bytes (byte_address >>3), 29 bits 
        @param size64 size of the transfer buffer in the system memory, in 8-bytes. Transfers will roll over to lo_addr64. 29 bits.
        @param cont True: continue from  the same address in the system memory, where the previous transfer stopped. False - start from lo_addr64+start64
        @param cache bits[3:0] - ARCHACHE, AWCACHE (default 0x3), bit[4] - debug mode, when each 64-bit word high 16 bits is replaced with:
               bits[63:60] - transfer id (incrementing each new transfer), bits[59:58]==0, [57:56] - mchtrl page number, [45:48] FIFO count (wcount)
        @param wait_ready poll status to see if the command finished
        @param quiet Reduce output
        '''
        if frame_start_addr is None:
            frame_start_addr = vrlg.FRAME_START_ADDRESS  # input [21:0] frame_start_addr;
        if window_full_width is None:
            window_full_width = vrlg.FRAME_FULL_WIDTH  # input [15:0] window_full_width;# 13 bit - in 8*16=128 bit bursts
        if window_width is None:
            window_width = vrlg.WINDOW_WIDTH  # input [15:0] window_width;     # 13 bit - in 8*16=128 bit bursts
        if window_height is None:
            window_height = vrlg.WINDOW_HEIGHT  # input [15:0] window_height;    # 16 bit (only 14 are used here)
        if window_left is None:
            window_left = vrlg.WINDOW_X0  # input [15:0] window_left;
        if window_top is None:
            window_top = vrlg.WINDOW_Y0  # input [15:0] window_top;
        if lo_addr64 is None:
            lo_addr64 = BUFFER_ADDRESS // 8  # input [28:0] lo_addr64;        # low address of the system memory range, in 64-bit words
        if size64 is None:
            size64 = BUFFER_LEN // 8  # input [28:0] size64;           # size of the system memory range in 64-bit words

        window_height &= 0x3fff
        if window_height == 0:
            window_height = 0x4000
        window_width &= 0x1fff
        if window_width == 0:
            window_width = 0x2000

        if quiet < 2:
            print(
                "====== test_afi_rw: write=%s, frame_start=0x%x, window_full_width=%d, window_width=%d, window_height=%d, window_left=%d, window_top=%d"
                % (str(write_ddr3), frame_start_addr, window_full_width,
                   window_width, window_height, window_left, window_top))
            print(
                "len64=0x%x,  width64=0x%x, start64=0x%x, lo_addr64=0x%x, size64=0x%x, cache=0x%x"
                % ((window_width << 1) * window_height,
                   (window_width << 1), start64, lo_addr64, size64, cache))
        '''    
        mode=   func_encode_mode_scanline(
                    0, # extra_pages,
                    write_ddr3, # write_mem,
                    1, # enable
                    0)  # chn_reset
        '''
        mode = x393_mcntrl.func_encode_mode_scan_tiled(skip_too_late=False,
                                                       disable_need=False,
                                                       repetitive=True,
                                                       single=False,
                                                       reset_frame=False,
                                                       extra_pages=0,
                                                       write_mem=write_ddr3,
                                                       enable=True,
                                                       chn_reset=False)

        #        self.x393_axi_tasks.write_control_register(vrlg.MEMBRIDGE_ADDR + vrlg.MEMBRIDGE_WIDTH64,    width64);
        #        self.x393_axi_tasks.write_control_register(vrlg.MCNTRL_SCANLINE_CHN1_ADDR + vrlg.MCNTRL_SCANLINE_MODE,             0); # reset channel, including page address
        self.x393_axi_tasks.write_control_register(
            vrlg.MCNTRL_SCANLINE_CHN1_ADDR + vrlg.MCNTRL_SCANLINE_STARTADDR,
            frame_start_addr
        )  # RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0)
        self.x393_axi_tasks.write_control_register(
            vrlg.MCNTRL_SCANLINE_CHN1_ADDR +
            vrlg.MCNTRL_SCANLINE_FRAME_FULL_WIDTH, window_full_width)
        self.x393_axi_tasks.write_control_register(
            vrlg.MCNTRL_SCANLINE_CHN1_ADDR + vrlg.MCNTRL_SCANLINE_WINDOW_WH,
            (window_height << 16)
            | window_width)  # WINDOW_WIDTH + (WINDOW_HEIGHT<<16));
        self.x393_axi_tasks.write_control_register(
            vrlg.MCNTRL_SCANLINE_CHN1_ADDR + vrlg.MCNTRL_SCANLINE_WINDOW_X0Y0,
            (window_top << 16) | window_left)  # WINDOW_X0+ (WINDOW_Y0<<16));
        self.x393_axi_tasks.write_control_register(
            vrlg.MCNTRL_SCANLINE_CHN1_ADDR +
            vrlg.MCNTRL_SCANLINE_WINDOW_STARTXY, 0)
        self.x393_axi_tasks.write_control_register(
            vrlg.MCNTRL_SCANLINE_CHN1_ADDR + vrlg.MCNTRL_SCANLINE_MODE, mode)
        self.x393_axi_tasks.configure_channel_priority(1, 0)
        # lowest priority channel 1
        self.x393_axi_tasks.enable_memcntrl_en_dis(1, 1)
        #        write_control_register(test_mode_address,            TEST01_START_FRAME);
        self.afi_setup(0)
        self.membridge_setup(
            (window_width << 1) *
            window_height,  # ((window_width[12:0]==0)? 15'h4000 : {1'b0,window_width[12:0],1'b0})*window_height[13:0], #len64,
            (
                window_width << 1
            ),  # (window_width[12:0]==0)? 29'h4000 : {15'b0,window_width[12:0],1'b0}, # width64,
            start64,
            lo_addr64,
            size64,
            cache,
            quiet)
        self.membridge_start(cont)
        # just wait done (default timeout = 10 sec)
        if wait_ready:
            self.x393_axi_tasks.wait_status_condition(  # may also be read directly from the same bit of mctrl_linear_rw (address=5) status
                vrlg.
                MEMBRIDGE_STATUS_REG,  # MCNTRL_TEST01_STATUS_REG_CHN3_ADDR,
                vrlg.MEMBRIDGE_ADDR + vrlg.
                MEMBRIDGE_STATUS_CNTRL,  # MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN3_STATUS_CNTRL,
                vrlg.DEFAULT_STATUS_MODE,
                2 <<
                vrlg.STATUS_2LSB_SHFT,  # bit 24 - busy, bit 25 - frame done
                2 << vrlg.STATUS_2LSB_SHFT,  # mask for the 4-bit page number
                0,  # equal to
                1)
Example #4
0
 def setup_compressor_memory(
         self,
         num_sensor,
         frame_sa,
         frame_sa_inc,
         last_frame_num,
         frame_full_width,
         window_width,
         window_height,
         window_left,
         window_top,
         byte32,
         tile_width,
         tile_vstep,  # = 16
         tile_height,  #= 18
         extra_pages,
         disable_need):
     """
     Setup memory controller for a compressor channel
     @param num_sensor -       sensor port number (0..3)
     @param frame_sa -         22-bit frame start address ((3 CA LSBs==0. BA==0)
     @param frame_sa_inc -     22-bit frame start address increment  ((3 CA LSBs==0. BA==0)
     @param last_frame_num -   16-bit number of the last frame in a buffer
     @param frame_full_width - 13-bit Padded line length (8-row increment), in 8-bursts (16 bytes)
     @param window_width -     13-bit - in 8*16=128 bit bursts
     @param window_height -    16-bit window height (in scan lines)
     @param window_left -      13-bit window left margin in 8-bursts (16 bytes)
     @param window_top -       16-bit window top margin (in scan lines
     @param byte32 -           32-byte columns
     @param tile_width         tile width,
     @param tile_vstep         tile vertical step in pixel rows (JPEG18/jp4 = 16)
     @param tile_height        tile height: 18 for color JPEG, 16 fore JP$ flavors,
     @param extra_pages        extra pages needed (1)
     @param disable_need       disable need (preference to sensor channels - they can not wait
     """
     #        tile_vstep = 16
     #        tile_height= 18
     base_addr = vrlg.MCONTR_CMPRS_BASE + vrlg.MCONTR_CMPRS_INC * num_sensor
     mode = x393_mcntrl.func_encode_mode_scan_tiled(
         skip_too_late=False,
         disable_need=disable_need,
         repetitive=True,
         single=False,
         reset_frame=False,
         byte32=byte32,
         keep_open=False,
         extra_pages=extra_pages,
         write_mem=False,
         enable=True,
         chn_reset=False)
     self.x393_axi_tasks.write_control_register(
         base_addr + vrlg.MCNTRL_TILED_STARTADDR, frame_sa
     )  # RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0)
     self.x393_axi_tasks.write_control_register(
         base_addr + vrlg.MCNTRL_TILED_FRAME_SIZE, frame_sa_inc)
     self.x393_axi_tasks.write_control_register(
         base_addr + vrlg.MCNTRL_TILED_FRAME_LAST, last_frame_num)
     self.x393_axi_tasks.write_control_register(
         base_addr + vrlg.MCNTRL_TILED_FRAME_FULL_WIDTH, frame_full_width)
     self.x393_axi_tasks.write_control_register(
         base_addr + vrlg.MCNTRL_TILED_WINDOW_WH,
         ((window_height & 0xffff) << 16) |
         (window_width & 0xffff))  #/WINDOW_WIDTH + (WINDOW_HEIGHT<<16));
     self.x393_axi_tasks.write_control_register(
         base_addr + vrlg.MCNTRL_TILED_WINDOW_X0Y0,
         ((window_top & 0xffff) << 16) |
         (window_left & 0xffff))  #WINDOW_X0+ (WINDOW_Y0<<16));
     self.x393_axi_tasks.write_control_register(
         base_addr + vrlg.MCNTRL_TILED_WINDOW_STARTXY, 0)
     self.x393_axi_tasks.write_control_register(
         base_addr + vrlg.MCNTRL_TILED_TILE_WHS,
         ((tile_vstep & 0xff) << 16) | ((tile_height & 0xff) << 8) |
         (tile_width & 0xff))  #//(tile_height<<8)+(tile_vstep<<16));
     self.x393_axi_tasks.write_control_register(
         base_addr + vrlg.MCNTRL_TILED_MODE, mode)
Example #5
0
    def test_tiled_read(
        self,  # \
        channel,  # input            [3:0] channel;
        byte32,  # input                  byte32;
        keep_open,  # input                  keep_open;
        extra_pages,  # input            [1:0] extra_pages;
        show_data,  # input                  show_data;
        window_width,  # input [15:0]           window_width;
        window_height,  # input [15:0]           window_height;
        window_left,  # input [15:0]           window_left;
        window_top,  # input [15:0]           window_top;
        tile_width,  # input [ 7:0]           tile_width;
        tile_height,  # input [ 7:0]           tile_height;
        tile_vstep,
    ):  # input [ 7:0]           tile_vstep;
        """
        Test tiled mode write (frame size/row increment is set in parameters) 
        <channel> channel number to use. Valid values: 2, 4
        <byte32>        use 32-byte wide columns (0 - use 16-byte ones)
        <keep_open>,    do not close page between accesses (for 8 or less rows only)
        <extra_pages>    2-bit number of extra pages that need to stay (not to be overwritten) in the buffer
        <show_data>      print read data
        <window_width>   13-bit window width in 8-bursts (16 bytes)
        <window_height>  16 bit window height
        <window_left>,   13-bit window left margin in 8-bursts (16 bytes)
        <window_top>     16-bit window top margin
        <tile_width>     6-bit tile width in 8-bursts (16 bytes) (0 -> 64)
        <tile_height>    6-bit tile_height (0->64)
        <tile_vstep>     6-bit tile vertical step (0->64) to control tole vertical overlap
        Returns read data as a list
        """
        result = []  # will be a 2-d array
        #        tiles_per_row= (window_width/tile_width)+  ((window_width % tile_width==0)?0:1);
        tiles_per_row = (window_width / tile_width) + (0, 1)[(window_width % tile_width) == 0]
        tile_rows_per_window = ((window_height - 1) / tile_vstep) + 1
        tile_size = tile_width * tile_height
        channel = (0, 1)[channel]
        keep_open = (0, 1)[keep_open]
        show_data = (0, 1)[show_data]
        print(
            "====== test_tiled_read: channel=%d, byte32=%d, keep_open=%d, extra_pages=%d,  show_data=%d"
            % (channel, byte32, keep_open, extra_pages, show_data)
        )
        if channel == 2:
            start_addr = vrlg.MCNTRL_TILED_CHN2_ADDR
            status_address = vrlg.MCNTRL_TEST01_STATUS_REG_CHN2_ADDR
            status_control_address = vrlg.MCNTRL_TEST01_ADDR + vrlg.MCNTRL_TEST01_CHN2_STATUS_CNTRL
            test_mode_address = vrlg.MCNTRL_TEST01_ADDR + vrlg.MCNTRL_TEST01_CHN2_MODE
        elif channel == 4:
            start_addr = vrlg.MCNTRL_TILED_CHN4_ADDR
            status_address = vrlg.MCNTRL_TEST01_STATUS_REG_CHN4_ADDR
            status_control_address = vrlg.MCNTRL_TEST01_ADDR + vrlg.MCNTRL_TEST01_CHN4_STATUS_CNTRL
            test_mode_address = vrlg.MCNTRL_TEST01_ADDR + vrlg.MCNTRL_TEST01_CHN4_MODE
        else:
            print("**** ERROR: Invalid channel, only 2 and 4 are valid")
            start_addr = vrlg.MCNTRL_TILED_CHN2_ADDR
            status_address = vrlg.MCNTRL_TEST01_STATUS_REG_CHN2_ADDR
            status_control_address = vrlg.MCNTRL_TEST01_ADDR + vrlg.MCNTRL_TEST01_CHN2_STATUS_CNTRL
            test_mode_address = vrlg.MCNTRL_TEST01_ADDR + vrlg.MCNTRL_TEST01_CHN2_MODE

        """
        mode=   self.func_encode_mode_tiled(
                                            byte32,
                                            keep_open,
                                            extra_pages,
                                            0, # write_mem,
                                            1, # enable
                                            0)  # chn_reset
        """
        mode = x393_mcntrl.func_encode_mode_scan_tiled(
            disable_need=False,
            repetitive=True,
            single=False,
            reset_frame=False,
            byte32=byte32,
            keep_open=keep_open,
            extra_pages=extra_pages,
            write_mem=False,
            enable=True,
            chn_reset=False,
        )

        self.x393_axi_tasks.write_control_register(start_addr + vrlg.MCNTRL_TILED_MODE, 0)
        # reset channel, including page address
        self.x393_axi_tasks.write_control_register(
            start_addr + vrlg.MCNTRL_TILED_STARTADDR, vrlg.FRAME_START_ADDRESS
        )  # RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0)
        self.x393_axi_tasks.write_control_register(
            start_addr + vrlg.MCNTRL_TILED_FRAME_FULL_WIDTH, vrlg.FRAME_FULL_WIDTH
        )
        self.x393_axi_tasks.write_control_register(
            start_addr + vrlg.MCNTRL_TILED_WINDOW_WH, concat(((window_height, 16), (window_width, 16)))[0]
        )  # {window_height,window_width});
        self.x393_axi_tasks.write_control_register(
            start_addr + vrlg.MCNTRL_TILED_WINDOW_X0Y0, concat(((window_top, 16), (window_left, 16)))[0]
        )  #  {window_top,window_left});
        self.x393_axi_tasks.write_control_register(
            start_addr + vrlg.MCNTRL_TILED_WINDOW_STARTXY, concat(((vrlg.TILED_STARTY, 16), (vrlg.TILED_STARTX, 16)))[0]
        )  #  TILED_STARTX+(TILED_STARTY<<16));
        self.x393_axi_tasks.write_control_register(
            start_addr + vrlg.MCNTRL_TILED_TILE_WHS, concat(((tile_vstep, 8), (tile_height, 8), (tile_width, 8)))[0]
        )  # {8'b0,tile_vstep,tile_height,tile_width});#tile_width+(tile_height<<8)+(tile_vstep<<16));
        self.x393_axi_tasks.write_control_register(start_addr + vrlg.MCNTRL_TILED_MODE, mode)
        # set mode register: {extra_pages[1:0],enable,!reset}
        self.x393_axi_tasks.configure_channel_priority(channel, 0)  # lowest priority channel 3
        self.x393_axi_tasks.enable_memcntrl_en_dis(channel, 1)
        self.x393_axi_tasks.write_control_register(test_mode_address, vrlg.TEST01_START_FRAME)
        for ii in range(
            tiles_per_row * tile_rows_per_window
        ):  # (ii=0;ii<(tiles_per_row * tile_rows_per_window);ii = ii+1) begin
            self.x393_axi_tasks.wait_status_condition(
                status_address,  # MCNTRL_TEST01_STATUS_REG_CHN4_ADDR,
                status_control_address,  # MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN4_STATUS_CNTRL,
                vrlg.DEFAULT_STATUS_MODE,
                ii << 16,  # -TEST_INITIAL_BURST)<<16, # 4-bit page number
                0xF << 16,  #'hf << 16,  # mask for the 4-bit page number
                1,  # not equal to
                (0, 1)[ii == 0],
            )  # synchronize sequence number - only first time, next just wait fro auto update
            if show_data:
                print("########### test_tiled_read block %d: channel=%d" % (ii, channel))

            result.append(
                self.x393_mcntrl_buffers.read_block_buf_chn(
                    channel,
                    (ii & 3),
                    tile_size << 2,
                    #                                                                       1, # chn=0, page=3, number of 32-bit words=256, show_rslt
                    show_data,
                )
            )
            self.x393_axi_tasks.write_control_register(test_mode_address, vrlg.TEST01_NEXT_PAGE)
        #     enable_memcntrl_en_dis(channel,0); # disable channel
        return result
Example #6
0
    def test_tiled_write(
        self,  #
        channel,  # input            [3:0] channel;
        byte32,  # input                  byte32;
        keep_open,  # input                  keep_open;
        extra_pages,  # input            [1:0] extra_pages;
        wait_done,  # input                  wait_done;
        window_width,  # input [15:0]           window_width;
        window_height,  # input [15:0]           window_height;
        window_left,  # input [15:0]           window_left;
        window_top,  # input [15:0]           window_top;
        tile_width,  # input [ 7:0]           tile_width;
        tile_height,  # input [ 7:0]           tile_height;
        tile_vstep,
    ):  # input [ 7:0]           tile_vstep;
        """
        Test tiled mode write (frame size/row increment is set in parameters) 
        <channel> channel number to use. Valid values: 2, 4
        <byte32>        use 32-byte wide columns (0 - use 16-byte ones)
        <keep_open>,    do not close page between accesses (for 8 or less rows only)
        <extra_pages>    2-bit number of extra pages that need to stay (not to be overwritten) in the buffer
        <wait_done>      wait for operation finished
        <window_width>   13-bit window width in 8-bursts (16 bytes)
        <window_height>  16 bit window height
        <window_left>,   13-bit window left margin in 8-bursts (16 bytes)
        <window_top>     16-bit window top margin
        <tile_width>     6-bit tile width in 8-bursts (16 bytes) (0 -> 64)
        <tile_height>    6-bit tile_height (0->64)
        <tile_vstep>     6-bit tile vertical step (0->64) to control tole vertical overlap
        """

        #        tiles_per_row= (window_width/tile_width)+  ((window_width % tile_width==0)?0:1);
        tiles_per_row = (window_width / tile_width) + (0, 1)[(window_width % tile_width) == 0]
        tile_rows_per_window = ((window_height - 1) / tile_vstep) + 1
        tile_size = tile_width * tile_height
        channel = (0, 1)[channel]
        keep_open = (0, 1)[keep_open]
        wait_done = (0, 1)[wait_done]

        print(
            "====== test_tiled_write: channel=%d, byte32=%d, keep_open=%d, extra_pages=%d,  wait_done=%d"
            % (channel, byte32, keep_open, extra_pages, wait_done)
        )
        if channel == 2:
            start_addr = vrlg.MCNTRL_TILED_CHN2_ADDR
            status_address = vrlg.MCNTRL_TEST01_STATUS_REG_CHN2_ADDR
            status_control_address = vrlg.MCNTRL_TEST01_ADDR + vrlg.MCNTRL_TEST01_CHN2_STATUS_CNTRL
            test_mode_address = vrlg.MCNTRL_TEST01_ADDR + vrlg.MCNTRL_TEST01_CHN2_MODE
        elif channel == 4:
            start_addr = vrlg.MCNTRL_TILED_CHN4_ADDR
            status_address = vrlg.MCNTRL_TEST01_STATUS_REG_CHN4_ADDR
            status_control_address = vrlg.MCNTRL_TEST01_ADDR + vrlg.MCNTRL_TEST01_CHN4_STATUS_CNTRL
            test_mode_address = vrlg.MCNTRL_TEST01_ADDR + vrlg.MCNTRL_TEST01_CHN4_MODE
        else:
            print("**** ERROR: Invalid channel, only 2 and 4 are valid")
            start_addr = vrlg.MCNTRL_TILED_CHN2_ADDR
            status_address = vrlg.MCNTRL_TEST01_STATUS_REG_CHN2_ADDR
            status_control_address = vrlg.MCNTRL_TEST01_ADDR + vrlg.MCNTRL_TEST01_CHN2_STATUS_CNTRL
            test_mode_address = vrlg.MCNTRL_TEST01_ADDR + vrlg.MCNTRL_TEST01_CHN2_MODE
        """    
        mode=   self.func_encode_mode_tiled(
                                            byte32,
                                            keep_open,
                                            extra_pages,
                                            1,           # write_mem,
                                            1,           # enable
                                            0)           # chn_reset
        """
        mode = x393_mcntrl.func_encode_mode_scan_tiled(
            disable_need=False,
            repetitive=True,
            single=False,
            reset_frame=False,
            byte32=byte32,
            keep_open=keep_open,
            extra_pages=extra_pages,
            write_mem=True,
            enable=True,
            chn_reset=False,
        )

        self.x393_axi_tasks.write_control_register(start_addr + vrlg.MCNTRL_TILED_MODE, 0)
        # reset channel, including page address
        self.x393_axi_tasks.write_control_register(
            start_addr + vrlg.MCNTRL_TILED_STARTADDR, vrlg.FRAME_START_ADDRESS
        )  # RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0)
        self.x393_axi_tasks.write_control_register(
            start_addr + vrlg.MCNTRL_TILED_FRAME_FULL_WIDTH, vrlg.FRAME_FULL_WIDTH
        )
        self.x393_axi_tasks.write_control_register(
            start_addr + vrlg.MCNTRL_TILED_WINDOW_WH, concat(((window_height, 16), (window_width, 16)))[0]
        )  # {window_height,window_width});
        self.x393_axi_tasks.write_control_register(
            start_addr + vrlg.MCNTRL_TILED_WINDOW_X0Y0, concat(((window_top, 16), (window_left, 16)))[0]
        )  #  {window_top,window_left});
        self.x393_axi_tasks.write_control_register(
            start_addr + vrlg.MCNTRL_TILED_WINDOW_STARTXY, concat(((vrlg.TILED_STARTY, 16), (vrlg.TILED_STARTX, 16)))[0]
        )  #  TILED_STARTX+(TILED_STARTY<<16));
        self.x393_axi_tasks.write_control_register(
            start_addr + vrlg.MCNTRL_TILED_TILE_WHS, concat(((tile_vstep, 8), (tile_height, 8), (tile_width, 8)))[0]
        )  # {8'b0,tile_vstep,tile_height,tile_width});#tile_width+(tile_height<<8)+(tile_vstep<<16));
        self.x393_axi_tasks.write_control_register(start_addr + vrlg.MCNTRL_TILED_MODE, mode)
        # set mode register: {extra_pages[1:0],enable,!reset}
        self.x393_axi_tasks.configure_channel_priority(channel, 0)  # lowest priority channel 3
        self.x393_axi_tasks.enable_memcntrl_en_dis(channel, 1)
        self.x393_axi_tasks.write_control_register(test_mode_address, vrlg.TEST01_START_FRAME)

        for ii in range(vrlg.TEST_INITIAL_BURST):  # for (ii=0;ii<TEST_INITIAL_BURST;ii=ii+1) begin
            print("########### test_tiled_write block %d: channel=%d" % (ii, channel))
            startx = window_left + ((ii % tiles_per_row) * tile_width)
            starty = window_top + (ii / tile_rows_per_window)  # SCANLINE_CUR_Y);
            self.x393_mcntrl_buffers.write_block_scanline_chn(  # TODO: Make a different tile buffer data, matching the order
                channel,  # channel
                (ii & 3),
                tile_size,
                startx,  # window_left + ((ii % tiles_per_row) * tile_width),
                starty,
            )
            # window_top + (ii / tile_rows_per_window)); # SCANLINE_CUR_Y);\

        for ii in range(
            tiles_per_row * tile_rows_per_window
        ):  # for (ii=0;ii<(tiles_per_row * tile_rows_per_window);ii = ii+1) begin
            if ii >= vrlg.TEST_INITIAL_BURST:  # ) begin # wait page ready and fill page after first 4 are filled
                self.x393_axi_tasks.wait_status_condition(
                    status_address,  # MCNTRL_TEST01_STATUS_REG_CHN5_ADDR,
                    status_control_address,  # MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN5_STATUS_CNTRL,
                    vrlg.DEFAULT_STATUS_MODE,
                    (ii - vrlg.TEST_INITIAL_BURST) << 16,  # 4-bit page number
                    0xF << 16,  # 'hf << 16,  # mask for the 4-bit page number
                    1,  # not equal to
                    (0, 1)[ii == vrlg.TEST_INITIAL_BURST],
                )
                # synchronize sequence number - only first time, next just wait fro auto update
                print("########### test_tiled_write block %d: channel=%d" % (ii, channel))
                startx = window_left + ((ii % tiles_per_row) * tile_width)
                starty = window_top + (ii / tile_rows_per_window)
                self.x393_mcntrl_buffers.write_block_scanline_chn(  # TODO: Make a different tile buffer data, matching the order
                    channel,  # channel
                    (ii & 3),
                    tile_size,
                    startx,  # window_left + ((ii % tiles_per_row) * tile_width),
                    starty,
                )  # window_top + (ii / tile_rows_per_window)); # SCANLINE_CUR_Y);\
            self.x393_axi_tasks.write_control_register(test_mode_address, vrlg.TEST01_NEXT_PAGE)
        if wait_done:
            self.x393_axi_tasks.wait_status_condition(  # may also be read directly from the same bit of mctrl_linear_rw (address=5) status
                status_address,  # MCNTRL_TEST01_STATUS_REG_CHN3_ADDR,
                status_control_address,  # MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN3_STATUS_CNTRL,
                vrlg.DEFAULT_STATUS_MODE,
                2 << vrlg.STATUS_2LSB_SHFT,  # bit 24 - busy, bit 25 - frame done
                2 << vrlg.STATUS_2LSB_SHFT,  # mask for the 4-bit page number
                0,  # equal to
                0,
            )  # no need to synchronize sequence number
Example #7
0
    def test_scanline_read(
        self,  # SuppressThisWarning VEditor - may be unused
        channel,  # input            [3:0] channel;
        extra_pages,  # input            [1:0] extra_pages;
        show_data,  # input                  extra_pages;
        window_width,  # input [15:0]           window_width;
        window_height,  # input [15:0]           window_height;
        window_left,  # input [15:0]           window_left;
        window_top,  # input [15:0]           window_top;
        frame_start_addr=0x0,  # 1000,
        frame_full_width=0xC0,
    ):
        """
        Test scanline read (frame size/row increment is set in parameters) 
        @param channel channel number to use. Valid values: 1, 3
        @param extra_pages    2-bit number of extra pages that need to stay (not to be overwritten) in the buffer
        @param show_data      print read data 
        @param window_width   13-bit window width in 8-bursts (16 bytes)
        @param window_height  16 bit window height
        @param window_left,   13-bit window left margin in 8-bursts (16 bytes)
        @param window_top     16-bit window top margin
        @param frame_start_addr - frame start address (was 0x1000)
        @param frame_full_width - frame full width in bursts (16 bytes) - was 0xc0
        @return read data as list
        """
        if show_data == 2:
            result = self.test_scanline_read(
                channel=channel,  # input            [3:0] channel;
                extra_pages=extra_pages,  # input            [1:0] extra_pages;
                show_data=0,  # input                  extra_pages;
                window_width=window_width,  # input [15:0]           window_width;
                window_height=window_height,  # input [15:0]           window_height;
                window_left=window_left,  # input [15:0]           window_left;
                window_top=window_top,
            )
            for line_no, line in enumerate(result):
                print("%03x:" % (line_no), end=" ")
                for i in range(len(line) // 2):
                    d = line[2 * i] + (line[2 * i + 1] << 32)
                    print("%16x" % (d), end=" ")
                print()
            return result

        result = []  # will be a 2-d array

        #        pages_per_row= (window_width>>NUM_XFER_BITS)+((window_width[NUM_XFER_BITS-1:0]==0)?0:1);
        pages_per_row = (window_width >> vrlg.NUM_XFER_BITS) + (1, 0)[
            (window_width & ((1 << vrlg.NUM_XFER_BITS)) - 1) == 0
        ]  # (window_width>>NUM_XFER_BITS)+((window_width[NUM_XFER_BITS-1:0]==0)?0:1);

        print(
            "====== test_scanline_read: channel=%d, extra_pages=%d,  show_data=%d" % (channel, extra_pages, show_data)
        )
        """
        if   channel == 1:
            start_addr=             vrlg.MCNTRL_SCANLINE_CHN1_ADDR
            status_address=         vrlg.MCNTRL_TEST01_STATUS_REG_CHN1_ADDR
            status_control_address= vrlg.MCNTRL_TEST01_ADDR + vrlg.MCNTRL_TEST01_CHN1_STATUS_CNTRL
            test_mode_address=      vrlg.MCNTRL_TEST01_ADDR + vrlg.MCNTRL_TEST01_CHN1_MODE
        """
        if channel == 3:
            start_addr = vrlg.MCNTRL_SCANLINE_CHN3_ADDR
            status_address = vrlg.MCNTRL_TEST01_STATUS_REG_CHN3_ADDR
            status_control_address = vrlg.MCNTRL_TEST01_ADDR + vrlg.MCNTRL_TEST01_CHN3_STATUS_CNTRL
            test_mode_address = vrlg.MCNTRL_TEST01_ADDR + vrlg.MCNTRL_TEST01_CHN3_MODE
        else:
            print("**** ERROR: Invalid channel, only 3 is valid")
            start_addr = vrlg.MCNTRL_SCANLINE_CHN3_ADDR
            status_address = vrlg.MCNTRL_TEST01_STATUS_REG_CHN3_ADDR
            status_control_address = vrlg.MCNTRL_TEST01_ADDR + vrlg.MCNTRL_TEST01_CHN3_STATUS_CNTRL
            test_mode_address = vrlg.MCNTRL_TEST01_ADDR + vrlg.MCNTRL_TEST01_CHN3_MODE
        """    
        mode=   self.func_encode_mode_scanline(
                                               extra_pages,
                                               0, # write_mem,
                                               1, # enable
                                               0)  # chn_reset
        """
        mode = x393_mcntrl.func_encode_mode_scan_tiled(
            disable_need=False,
            repetitive=True,
            single=False,
            reset_frame=False,
            extra_pages=extra_pages,
            write_mem=False,
            enable=True,
            chn_reset=False,
        )

        # program to the
        self.x393_axi_tasks.write_control_register(start_addr + vrlg.MCNTRL_SCANLINE_MODE, 0)
        # reset channel, including page address
        self.x393_axi_tasks.write_control_register(start_addr + vrlg.MCNTRL_SCANLINE_STARTADDR, frame_start_addr)
        # RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0)
        self.x393_axi_tasks.write_control_register(start_addr + vrlg.MCNTRL_SCANLINE_FRAME_FULL_WIDTH, frame_full_width)
        self.x393_axi_tasks.write_control_register(
            start_addr + vrlg.MCNTRL_SCANLINE_WINDOW_WH, (window_height << 16) | window_width
        )
        # WINDOW_WIDTH + (WINDOW_HEIGHT<<16));
        self.x393_axi_tasks.write_control_register(
            start_addr + vrlg.MCNTRL_SCANLINE_WINDOW_X0Y0, (window_top << 16) | window_left
        )
        # WINDOW_X0+ (WINDOW_Y0<<16));
        self.x393_axi_tasks.write_control_register(
            start_addr + vrlg.MCNTRL_SCANLINE_WINDOW_STARTXY, vrlg.SCANLINE_STARTX + (vrlg.SCANLINE_STARTY << 16)
        )
        self.x393_axi_tasks.write_control_register(start_addr + vrlg.MCNTRL_SCANLINE_MODE, mode)
        # set mode register: {extra_pages[1:0],enable,!reset}
        self.x393_axi_tasks.configure_channel_priority(channel, 0)
        # lowest priority channel 3
        self.x393_axi_tasks.enable_memcntrl_en_dis(channel, 1)
        self.x393_axi_tasks.write_control_register(test_mode_address, vrlg.TEST01_START_FRAME)
        for ii in range(window_height * pages_per_row):  # for (ii=0;ii<(window_height * pages_per_row);ii = ii+1) begin
            if pages_per_row > 1:
                if (ii % pages_per_row) < (pages_per_row - 1):
                    xfer_size = 1 << vrlg.NUM_XFER_BITS
                else:
                    xfer_size = window_width % (1 << vrlg.NUM_XFER_BITS)
            else:
                xfer_size = window_width & 0xFFFF
            self.x393_axi_tasks.wait_status_condition(
                status_address,  # MCNTRL_TEST01_STATUS_REG_CHN2_ADDR,
                status_control_address,  # MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN2_STATUS_CNTRL,
                vrlg.DEFAULT_STATUS_MODE,
                (ii) << 16,  # -TEST_INITIAL_BURST)<<16, # 4-bit page number
                0xF << 16,  #'hf << 16,  # mask for the 4-bit page number
                1,  # not equal to
                (0, 1)[ii == 0],
            )  # synchronize sequence number - only first time, next just wait for auto update
            # read block (if needed), for now just skip
            if show_data:
                print("########### test_scanline_read block %d: channel=%d" % (ii, channel))
            result.append(
                self.x393_mcntrl_buffers.read_block_buf_chn(
                    channel,
                    (ii & 3),
                    xfer_size << 2,
                    #                                                                       1, # chn=0, page=3, number of 32-bit words=256, show_rslt
                    show_data,
                )
            )
            self.x393_axi_tasks.write_control_register(test_mode_address, vrlg.TEST01_NEXT_PAGE)
        return result
Example #8
0
    def test_scanline_write(
        self,  #
        channel,  # input            [3:0] channel;
        extra_pages,  # input            [1:0] extra_pages;
        wait_done,  # input                  wait_done;
        window_width,  # input [15:0]           window_width;
        window_height,  # input [15:0]           window_height;
        window_left,  # input [15:0]           window_left;
        window_top,
    ):  # input [15:0]           window_top;
        """
        Test scanline write (frame size/row increment is set in parameters) 
        <channel> channel number to use. Valid values: 1, 3
        <extra_pages>    2-bit number of extra pages that need to stay (not to be overwritten) in the buffer
        <wait_done>      for operation finished
        <window_width>   13-bit window width in 8-bursts (16 bytes)
        <window_height>  16 bit window height
        <window_left>,   13-bit window left margin in 8-bursts (16 bytes)
        <window_top>     16-bit window top margin
        """
        #   integer startx,starty; # temporary - because of the vdt bug with integer ports
        #        pages_per_row= (window_width>>NUM_XFER_BITS)+((window_width[NUM_XFER_BITS-1:0]==0)?0:1);
        pages_per_row = (window_width >> vrlg.NUM_XFER_BITS) + (1, 0)[
            (window_width & ((1 << vrlg.NUM_XFER_BITS)) - 1) == 0
        ]  # (window_width>>NUM_XFER_BITS)+((window_width[NUM_XFER_BITS-1:0]==0)?0:1);
        print(
            "====== test_scanline_write: channel=%d, extra_pages=%d,  wait_done=%d" % (channel, extra_pages, wait_done)
        )
        """
        if   channel == 1:
            start_addr=             vrlg.MCNTRL_SCANLINE_CHN1_ADDR
            status_address=         vrlg.MCNTRL_TEST01_STATUS_REG_CHN1_ADDR
            status_control_address= vrlg.MCNTRL_TEST01_ADDR + vrlg.MCNTRL_TEST01_CHN1_STATUS_CNTRL
            test_mode_address=      vrlg.MCNTRL_TEST01_ADDR + vrlg.MCNTRL_TEST01_CHN1_MODE
        """
        if channel == 3:
            start_addr = vrlg.MCNTRL_SCANLINE_CHN3_ADDR
            status_address = vrlg.MCNTRL_TEST01_STATUS_REG_CHN3_ADDR
            status_control_address = vrlg.MCNTRL_TEST01_ADDR + vrlg.MCNTRL_TEST01_CHN3_STATUS_CNTRL
            test_mode_address = vrlg.MCNTRL_TEST01_ADDR + vrlg.MCNTRL_TEST01_CHN3_MODE
        else:
            print("**** ERROR: Invalid channel, only 3 is valid")
            start_addr = vrlg.MCNTRL_SCANLINE_CHN1_ADDR
            status_address = vrlg.MCNTRL_TEST01_STATUS_REG_CHN3_ADDR
            status_control_address = vrlg.MCNTRL_TEST01_ADDR + vrlg.MCNTRL_TEST01_CHN3_STATUS_CNTRL
            test_mode_address = vrlg.MCNTRL_TEST01_ADDR + vrlg.MCNTRL_TEST01_CHN3_MODE

        """
        mode=   self.func_encode_mode_scanline(
                    extra_pages,
                    1,  # write_mem,
                    1,  # enable
                    0)  # chn_reset
        """
        mode = x393_mcntrl.func_encode_mode_scan_tiled(
            disable_need=False,
            repetitive=True,
            single=False,
            reset_frame=False,
            extra_pages=extra_pages,
            write_mem=True,
            enable=True,
            chn_reset=False,
        )

        self.x393_axi_tasks.write_control_register(start_addr + vrlg.MCNTRL_SCANLINE_MODE, 0)
        # reset channel, including page address
        self.x393_axi_tasks.write_control_register(
            start_addr + vrlg.MCNTRL_SCANLINE_STARTADDR, vrlg.FRAME_START_ADDRESS
        )
        # RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0)
        self.x393_axi_tasks.write_control_register(
            start_addr + vrlg.MCNTRL_SCANLINE_FRAME_FULL_WIDTH, vrlg.FRAME_FULL_WIDTH
        )
        self.x393_axi_tasks.write_control_register(
            start_addr + vrlg.MCNTRL_SCANLINE_WINDOW_WH, (window_height << 16) | window_width
        )
        # WINDOW_WIDTH + (WINDOW_HEIGHT<<16));
        self.x393_axi_tasks.write_control_register(
            start_addr + vrlg.MCNTRL_SCANLINE_WINDOW_X0Y0, (window_top << 16) | window_left
        )
        # WINDOW_X0+ (WINDOW_Y0<<16));
        self.x393_axi_tasks.write_control_register(
            start_addr + vrlg.MCNTRL_SCANLINE_WINDOW_STARTXY, vrlg.SCANLINE_STARTX + (vrlg.SCANLINE_STARTY << 16)
        )
        self.x393_axi_tasks.write_control_register(start_addr + vrlg.MCNTRL_SCANLINE_MODE, mode)
        self.x393_axi_tasks.configure_channel_priority(channel, 0)
        # lowest priority channel 3
        #        enable_memcntrl_channels(16'h000b); # channels 0,1,3 are enabled
        self.x393_axi_tasks.enable_memcntrl_en_dis(channel, 1)
        self.x393_axi_tasks.write_control_register(test_mode_address, vrlg.TEST01_START_FRAME)
        for ii in range(0, vrlg.TEST_INITIAL_BURST):  # for (ii=0;ii<TEST_INITIAL_BURST;ii=ii+1) begin
            # VDT bugs: 1:does not propagate undefined width through ?:, 2: - does not allow to connect it to task integer input, 3: shows integer input width as 1
            if pages_per_row > 1:
                if (ii % pages_per_row) < (pages_per_row - 1):
                    xfer_size = 1 << vrlg.NUM_XFER_BITS
                else:
                    xfer_size = window_width % (1 << vrlg.NUM_XFER_BITS)
            else:
                xfer_size = window_width & 0xFFFF

            print("########### test_scanline_write block %d: channel=%d" % (ii, channel))
            startx = window_left + ((ii % pages_per_row) << vrlg.NUM_XFER_BITS)
            starty = window_top + (ii / pages_per_row)
            self.x393_mcntrl_buffers.write_block_scanline_chn(
                channel,
                (ii & 3),
                xfer_size,
                startx,  # window_left + ((ii % pages_per_row)<<NUM_XFER_BITS),  # SCANLINE_CUR_X,
                starty,
            )  # window_top + (ii / pages_per_row)); # SCANLINE_CUR_Y);\

        for ii in range(
            window_height * pages_per_row
        ):  # for (ii=0;ii< (window_height * pages_per_row) ;ii = ii+1) begin # here assuming 1 page per line
            if ii >= vrlg.TEST_INITIAL_BURST:  #  begin # wait page ready and fill page after first 4 are filled
                self.x393_axi_tasks.wait_status_condition(
                    status_address,  # MCNTRL_TEST01_STATUS_REG_CHN3_ADDR,
                    status_control_address,  # MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN3_STATUS_CNTRL,
                    vrlg.DEFAULT_STATUS_MODE,
                    (ii - vrlg.TEST_INITIAL_BURST) << 16,  # 4-bit page number
                    0xF << 16,  #'hf << 16,  # mask for the 4-bit page number
                    1,  # not equal to
                    (0, 1)[ii == vrlg.TEST_INITIAL_BURST],
                )  # synchronize sequence number - only first time, next just wait fro auto update
                if pages_per_row > 1:
                    if (ii % pages_per_row) < (pages_per_row - 1):
                        xfer_size = 1 << vrlg.NUM_XFER_BITS
                    else:
                        xfer_size = window_width % (1 << vrlg.NUM_XFER_BITS)
                else:
                    xfer_size = window_width & 0xFFFF

                print("########### test_scanline_write block %d: channel=%d" % (ii, channel))
                startx = window_left + ((ii % pages_per_row) << vrlg.NUM_XFER_BITS)
                starty = window_top + (ii / pages_per_row)
                self.x393_mcntrl_buffers.write_block_scanline_chn(
                    channel,
                    (ii & 3),
                    xfer_size,
                    startx,  # window_left + ((ii % pages_per_row)<<NUM_XFER_BITS),  # SCANLINE_CUR_X,
                    starty,
                )  # window_top + (ii / pages_per_row)); # SCANLINE_CUR_Y);
            self.x393_axi_tasks.write_control_register(test_mode_address, vrlg.TEST01_NEXT_PAGE)
        if wait_done:
            self.x393_axi_tasks.wait_status_condition(  # may also be read directly from the same bit of mctrl_linear_rw (address=5) status
                status_address,  # MCNTRL_TEST01_STATUS_REG_CHN3_ADDR,
                status_control_address,  # MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN3_STATUS_CNTRL,
                vrlg.DEFAULT_STATUS_MODE,
                2 << vrlg.STATUS_2LSB_SHFT,  # bit 24 - busy, bit 25 - frame done
                2 << vrlg.STATUS_2LSB_SHFT,  # mask for the 4-bit page number
                0,  # equal to
                0,
            )
Example #9
0
 def control_compressor_memory(self,
                           num_sensor,
                           command,
                           reset_frame = False,
                           copy_frame = False,
                           abort_late = False,
                           verbose = 1):
     """
     Control memory access (write) of a sensor channel
     @param num_sensor - memory sensor channel (or all)
     @param command -    one of (case insensitive):
            reset       - reset channel, channel pointers immediately,
            stop        - stop at the end of the frame (if repetitive),
            single      - acquire single frame ,
            repetitive  - repetitive mode
     @param reset_frame - reset frame number
     @param copy_frame  - copy frame number from the master channel (non-persistent)
     @param abort_late  -  abort frame r/w at the next frame sync, if not finished. Wait for pending memory transfers
     @param vebose -      verbose level       
     """
     try:
         if (num_sensor == all) or (num_sensor[0].upper() == "A"): #all is a built-in function
             for num_sensor in range(4):
                 print ('num_sensor = ',num_sensor)
                 self.control_compressor_memory(num_sensor = num_sensor,
                                                command =    command,
                                                reset_frame = reset_frame,
                                                copy_frame = copy_frame,
                                                abort_late = abort_late,
                                                verbose =    verbose)
             return
     except:
         pass
     
     
     rpt =    False
     sngl =   False
     en =     False
     rst =    False
     byte32 = True
     if command[:3].upper() ==   'RES':
         rst = True
     elif command[:2].upper() == 'ST':
         pass
     elif command[:2].upper() == 'SI':
         sngl = True
         en =   True
     elif command[:3].upper() == 'REP':
         rpt =  True
         en =   True
     else:
         print ("Unrecognized command %s. Valid commands are RESET, STOP, SINGLE, REPETITIVE"%(command))
         return    
                             
     base_addr = vrlg.MCONTR_CMPRS_BASE + vrlg.MCONTR_CMPRS_INC * num_sensor;
     mode=   x393_mcntrl.func_encode_mode_scan_tiled(
                                skip_too_late = True,                     
                                disable_need = False,
                                repetitive=    rpt,
                                single =       sngl,
                                reset_frame =  reset_frame,
                                byte32 =       byte32,
                                keep_open =    False,
                                extra_pages =  0,
                                write_mem =    False,
                                enable =       en,
                                chn_reset =    rst,
                                copy_frame = copy_frame,
                                abort_late =   abort_late)
     
     self.x393_axi_tasks.write_control_register(base_addr + vrlg.MCNTRL_TILED_MODE,  mode) 
     if verbose > 0 :
         print ("write_control_register(0x%08x, 0x%08x)"%(base_addr + vrlg.MCNTRL_TILED_MODE,  mode))