def bench():
# Parameters
PORTS = 2
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
up_xfcp_in_tdata_list = [Signal(intbv(0)[8:]) for i in range(PORTS)]
up_xfcp_in_tvalid_list = [Signal(bool(0)) for i in range(PORTS)]
up_xfcp_in_tlast_list = [Signal(bool(0)) for i in range(PORTS)]
up_xfcp_in_tuser_list = [Signal(bool(0)) for i in range(PORTS)]
up_xfcp_in_tdata = ConcatSignal(*reversed(up_xfcp_in_tdata_list))
up_xfcp_in_tvalid = ConcatSignal(*reversed(up_xfcp_in_tvalid_list))
up_xfcp_in_tlast = ConcatSignal(*reversed(up_xfcp_in_tlast_list))
up_xfcp_in_tuser = ConcatSignal(*reversed(up_xfcp_in_tuser_list))
up_xfcp_out_tready_list = [Signal(bool(0)) for i in range(PORTS)]
up_xfcp_out_tready = ConcatSignal(*reversed(up_xfcp_out_tready_list))
down_xfcp_in_tdata = Signal(intbv(0)[8:])
down_xfcp_in_tvalid = Signal(bool(0))
down_xfcp_in_tlast = Signal(bool(0))
down_xfcp_in_tuser = Signal(bool(0))
down_xfcp_out_tready = Signal(bool(0))
# Outputs
up_xfcp_in_tready = Signal(intbv(0)[PORTS:])
up_xfcp_in_tready_list = [up_xfcp_in_tready(i) for i in range(PORTS)]
up_xfcp_out_tdata = Signal(intbv(0)[PORTS * 8:])
up_xfcp_out_tvalid = Signal(intbv(0)[PORTS:])
up_xfcp_out_tlast = Signal(intbv(0)[PORTS:])
up_xfcp_out_tuser = Signal(intbv(0)[PORTS:])
up_xfcp_out_tdata_list = [
up_xfcp_out_tdata((i + 1) * 8, i * 8) for i in range(PORTS)
]
up_xfcp_out_tvalid_list = [up_xfcp_out_tvalid(i) for i in range(PORTS)]
up_xfcp_out_tlast_list = [up_xfcp_out_tlast(i) for i in range(PORTS)]
up_xfcp_out_tuser_list = [up_xfcp_out_tuser(i) for i in range(PORTS)]
down_xfcp_in_tready = Signal(bool(0))
down_xfcp_out_tdata = Signal(intbv(0)[8:])
down_xfcp_out_tvalid = Signal(bool(0))
down_xfcp_out_tlast = Signal(bool(0))
down_xfcp_out_tuser = Signal(bool(0))
# XFCP ports
up_xfcp_port_out_pause_list = []
up_xfcp_port_in_pause_list = []
up_xfcp_port_list = []
up_xfcp_port_logic_list = []
for k in range(PORTS):
port = xfcp.XFCPPort()
op = Signal(bool(0))
ip = Signal(bool(0))
up_xfcp_port_list.append(port)
up_xfcp_port_out_pause_list.append(op)
up_xfcp_port_in_pause_list.append(ip)
up_xfcp_port_logic_list.append(
port.create_logic(clk=clk,
rst=rst,
xfcp_in_tdata=up_xfcp_out_tdata_list[k],
xfcp_in_tvalid=up_xfcp_out_tvalid_list[k],
xfcp_in_tready=up_xfcp_out_tready_list[k],
xfcp_in_tlast=up_xfcp_out_tlast_list[k],
xfcp_in_tuser=up_xfcp_out_tuser_list[k],
xfcp_out_tdata=up_xfcp_in_tdata_list[k],
xfcp_out_tvalid=up_xfcp_in_tvalid_list[k],
xfcp_out_tready=up_xfcp_in_tready_list[k],
xfcp_out_tlast=up_xfcp_in_tlast_list[k],
xfcp_out_tuser=up_xfcp_in_tuser_list[k],
pause_source=ip,
pause_sink=op,
name='up_xfcp_port_%d' % k))
down_xfcp_port_out_pause = Signal(bool(0))
down_xfcp_port_in_pause = Signal(bool(0))
down_xfcp_port = xfcp.XFCPPort()
down_xfcp_port_logic = down_xfcp_port.create_logic(
clk=clk,
rst=rst,
xfcp_in_tdata=down_xfcp_out_tdata,
xfcp_in_tvalid=down_xfcp_out_tvalid,
xfcp_in_tready=down_xfcp_out_tready,
xfcp_in_tlast=down_xfcp_out_tlast,
xfcp_in_tuser=down_xfcp_out_tuser,
xfcp_out_tdata=down_xfcp_in_tdata,
xfcp_out_tvalid=down_xfcp_in_tvalid,
xfcp_out_tready=down_xfcp_in_tready,
xfcp_out_tlast=down_xfcp_in_tlast,
xfcp_out_tuser=down_xfcp_in_tuser,
pause_source=down_xfcp_port_in_pause,
pause_sink=down_xfcp_port_out_pause,
name='down_xfcp_port')
# DUT
if os.system(build_cmd):
raise Exception("Error running build command")
dut = Cosimulation("vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
up_xfcp_in_tdata=up_xfcp_in_tdata,
up_xfcp_in_tvalid=up_xfcp_in_tvalid,
up_xfcp_in_tready=up_xfcp_in_tready,
up_xfcp_in_tlast=up_xfcp_in_tlast,
up_xfcp_in_tuser=up_xfcp_in_tuser,
up_xfcp_out_tdata=up_xfcp_out_tdata,
up_xfcp_out_tvalid=up_xfcp_out_tvalid,
up_xfcp_out_tready=up_xfcp_out_tready,
up_xfcp_out_tlast=up_xfcp_out_tlast,
up_xfcp_out_tuser=up_xfcp_out_tuser,
down_xfcp_in_tdata=down_xfcp_in_tdata,
down_xfcp_in_tvalid=down_xfcp_in_tvalid,
down_xfcp_in_tready=down_xfcp_in_tready,
down_xfcp_in_tlast=down_xfcp_in_tlast,
down_xfcp_in_tuser=down_xfcp_in_tuser,
down_xfcp_out_tdata=down_xfcp_out_tdata,
down_xfcp_out_tvalid=down_xfcp_out_tvalid,
down_xfcp_out_tready=down_xfcp_out_tready,
down_xfcp_out_tlast=down_xfcp_out_tlast,
down_xfcp_out_tuser=down_xfcp_out_tuser)
@always(delay(4))
def clkgen():
clk.next = not clk
def wait_normal():
i = 4
while i > 0:
i = max(0, i - 1)
if not up_xfcp_port_list[0].idle(
) or not up_xfcp_port_list[1].idle() or not down_xfcp_port.idle():
i = 4
yield clk.posedge
def wait_pause_source():
i = 2
while i > 0:
i = max(0, i - 1)
if not up_xfcp_port_list[0].idle(
) or not up_xfcp_port_list[1].idle() or not down_xfcp_port.idle():
i = 2
up_xfcp_port_in_pause_list[0].next = True
up_xfcp_port_in_pause_list[1].next = True
down_xfcp_port_in_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
up_xfcp_port_in_pause_list[0].next = False
up_xfcp_port_in_pause_list[1].next = False
down_xfcp_port_in_pause.next = False
yield clk.posedge
def wait_pause_sink():
i = 2
while i > 0:
i = max(0, i - 1)
if not up_xfcp_port_list[0].idle(
) or not up_xfcp_port_list[1].idle() or not down_xfcp_port.idle():
i = 2
up_xfcp_port_out_pause_list[0].next = True
up_xfcp_port_out_pause_list[1].next = True
down_xfcp_port_out_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
up_xfcp_port_out_pause_list[0].next = False
up_xfcp_port_out_pause_list[1].next = False
down_xfcp_port_out_pause.next = False
yield clk.posedge
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
# testbench stimulus
yield clk.posedge
print("test 1: downstream packets")
current_test.next = 1
pkt = xfcp.XFCPFrame()
pkt.ptype = 1
pkt.path = [1, 2, 3]
pkt.payload = bytearray(range(8))
for wait in wait_normal, wait_pause_source, wait_pause_sink:
up_xfcp_port_list[0].send(pkt)
yield clk.posedge
up_xfcp_port_list[1].send(pkt)
yield clk.posedge
yield wait()
yield clk.posedge
rx_pkt = down_xfcp_port.recv()
check_pkt = xfcp.XFCPFrame(pkt)
check_pkt.rpath.insert(0, 0)
print(rx_pkt)
assert rx_pkt == check_pkt
rx_pkt = down_xfcp_port.recv()
check_pkt = xfcp.XFCPFrame(pkt)
check_pkt.rpath.insert(0, 1)
print(rx_pkt)
assert rx_pkt == check_pkt
yield delay(100)
yield clk.posedge
print("test 2: upstream packets")
current_test.next = 2
pkt0 = xfcp.XFCPFrame()
pkt0.ptype = 1
pkt0.path = [1, 2, 3]
pkt0.rpath = [0]
pkt0.payload = bytearray(range(8))
pkt1 = xfcp.XFCPFrame(pkt0)
pkt1.rpath = [1]
for wait in wait_normal, wait_pause_source, wait_pause_sink:
down_xfcp_port.send(pkt0)
down_xfcp_port.send(pkt1)
yield clk.posedge
yield wait()
yield clk.posedge
rx_pkt = up_xfcp_port_list[0].recv()
check_pkt = xfcp.XFCPFrame(pkt0)
check_pkt.rpath = check_pkt.rpath[1:]
print(rx_pkt)
assert rx_pkt == check_pkt
rx_pkt = up_xfcp_port_list[1].recv()
check_pkt = xfcp.XFCPFrame(pkt1)
check_pkt.rpath = check_pkt.rpath[1:]
print(rx_pkt)
assert rx_pkt == check_pkt
yield delay(100)
yield clk.posedge
print("test 3: downstream packets, various path and rpath")
current_test.next = 3
for p in range(3):
for rp in range(3):
pkt = xfcp.XFCPFrame()
pkt.ptype = 1
pkt.path = list(range(1, p + 1))
pkt.rpath = list(range(1 + p, rp + p + 1))
pkt.payload = bytearray(range(8))
for wait in wait_normal, wait_pause_source, wait_pause_sink:
up_xfcp_port_list[0].send(pkt)
yield clk.posedge
up_xfcp_port_list[1].send(pkt)
yield clk.posedge
yield wait()
yield clk.posedge
rx_pkt = down_xfcp_port.recv()
check_pkt = xfcp.XFCPFrame(pkt)
check_pkt.rpath.insert(0, 0)
print(rx_pkt)
assert rx_pkt == check_pkt
rx_pkt = down_xfcp_port.recv()
check_pkt = xfcp.XFCPFrame(pkt)
check_pkt.rpath.insert(0, 1)
print(rx_pkt)
assert rx_pkt == check_pkt
yield delay(100)
yield clk.posedge
print("test 4: upstream packets, various path and rpath")
current_test.next = 4
for p in range(3):
for rp in range(3):
pkt0 = xfcp.XFCPFrame()
pkt0.ptype = 1
pkt0.path = list(range(1, p + 1))
pkt0.rpath = [0] + list(range(1 + p, rp + p + 1))
pkt0.payload = bytearray(range(8))
pkt1 = xfcp.XFCPFrame(pkt0)
pkt1.rpath = [1] + list(range(1 + p, rp + p + 1))
for wait in wait_normal, wait_pause_source, wait_pause_sink:
down_xfcp_port.send(pkt0)
down_xfcp_port.send(pkt1)
yield clk.posedge
yield wait()
yield clk.posedge
rx_pkt = up_xfcp_port_list[0].recv()
check_pkt = xfcp.XFCPFrame(pkt0)
check_pkt.rpath = check_pkt.rpath[1:]
print(rx_pkt)
assert rx_pkt == check_pkt
rx_pkt = up_xfcp_port_list[1].recv()
check_pkt = xfcp.XFCPFrame(pkt1)
check_pkt.rpath = check_pkt.rpath[1:]
print(rx_pkt)
assert rx_pkt == check_pkt
yield delay(100)
yield clk.posedge
print("test 5: test invalid packets")
current_test.next = 5
pkt1 = xfcp.XFCPFrame()
pkt1.rpath = [10]
pkt1.ptype = 1
pkt1.payload = bytearray(range(8))
pkt2 = xfcp.XFCPFrame()
pkt2.path = [0] * 40
pkt2.rpath = [0]
pkt2.ptype = 1
pkt2.payload = bytearray(range(8))
for wait in wait_normal, wait_pause_source, wait_pause_sink:
down_xfcp_port.send(pkt1)
down_xfcp_port.send(pkt2)
yield clk.posedge
yield wait()
yield clk.posedge
rx_pkt = up_xfcp_port_list[0].recv()
assert rx_pkt is None
rx_pkt = up_xfcp_port_list[1].recv()
assert rx_pkt is None
rx_pkt = down_xfcp_port.recv()
assert rx_pkt is None
yield delay(100)
raise StopSimulation
return instances()
def bench():
# Parameters
PORTS = 4
XFCP_ID_TYPE = 0x0100
XFCP_ID_STR = "XFCP Switch"
XFCP_EXT_ID = b''
XFCP_EXT_ID_STR = ""
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
up_xfcp_in_tdata = Signal(intbv(0)[8:])
up_xfcp_in_tvalid = Signal(bool(0))
up_xfcp_in_tlast = Signal(bool(0))
up_xfcp_in_tuser = Signal(bool(0))
up_xfcp_out_tready = Signal(bool(0))
down_xfcp_in_tdata_list = [Signal(intbv(0)[8:]) for i in range(PORTS)]
down_xfcp_in_tvalid_list = [Signal(bool(0)) for i in range(PORTS)]
down_xfcp_in_tlast_list = [Signal(bool(0)) for i in range(PORTS)]
down_xfcp_in_tuser_list = [Signal(bool(0)) for i in range(PORTS)]
down_xfcp_in_tdata = ConcatSignal(*reversed(down_xfcp_in_tdata_list))
down_xfcp_in_tvalid = ConcatSignal(*reversed(down_xfcp_in_tvalid_list))
down_xfcp_in_tlast = ConcatSignal(*reversed(down_xfcp_in_tlast_list))
down_xfcp_in_tuser = ConcatSignal(*reversed(down_xfcp_in_tuser_list))
down_xfcp_out_tready_list = [Signal(bool(0)) for i in range(PORTS)]
down_xfcp_out_tready = ConcatSignal(*reversed(down_xfcp_out_tready_list))
# Outputs
up_xfcp_in_tready = Signal(bool(0))
up_xfcp_out_tdata = Signal(intbv(0)[8:])
up_xfcp_out_tvalid = Signal(bool(0))
up_xfcp_out_tlast = Signal(bool(0))
up_xfcp_out_tuser = Signal(bool(0))
down_xfcp_in_tready = Signal(intbv(0)[PORTS:])
down_xfcp_in_tready_list = [down_xfcp_in_tready(i) for i in range(PORTS)]
down_xfcp_out_tdata = Signal(intbv(0)[PORTS * 8:])
down_xfcp_out_tvalid = Signal(intbv(0)[PORTS:])
down_xfcp_out_tlast = Signal(intbv(0)[PORTS:])
down_xfcp_out_tuser = Signal(intbv(0)[PORTS:])
down_xfcp_out_tdata_list = [
down_xfcp_out_tdata((i + 1) * 8, i * 8) for i in range(PORTS)
]
down_xfcp_out_tvalid_list = [down_xfcp_out_tvalid(i) for i in range(PORTS)]
down_xfcp_out_tlast_list = [down_xfcp_out_tlast(i) for i in range(PORTS)]
down_xfcp_out_tuser_list = [down_xfcp_out_tuser(i) for i in range(PORTS)]
# XFCP ports
up_xfcp_port_out_pause = Signal(bool(0))
up_xfcp_port_in_pause = Signal(bool(0))
up_xfcp_port = xfcp.XFCPPort()
up_xfcp_port_logic = up_xfcp_port.create_logic(
clk=clk,
rst=rst,
xfcp_in_tdata=up_xfcp_out_tdata,
xfcp_in_tvalid=up_xfcp_out_tvalid,
xfcp_in_tready=up_xfcp_out_tready,
xfcp_in_tlast=up_xfcp_out_tlast,
xfcp_in_tuser=up_xfcp_out_tuser,
xfcp_out_tdata=up_xfcp_in_tdata,
xfcp_out_tvalid=up_xfcp_in_tvalid,
xfcp_out_tready=up_xfcp_in_tready,
xfcp_out_tlast=up_xfcp_in_tlast,
xfcp_out_tuser=up_xfcp_in_tuser,
pause_source=up_xfcp_port_in_pause,
pause_sink=up_xfcp_port_out_pause,
name='up_xfcp_port')
down_xfcp_port_out_pause_list = []
down_xfcp_port_in_pause_list = []
down_xfcp_port_list = []
down_xfcp_port_logic_list = []
for k in range(PORTS):
port = xfcp.XFCPPort()
op = Signal(bool(0))
ip = Signal(bool(0))
down_xfcp_port_list.append(port)
down_xfcp_port_out_pause_list.append(op)
down_xfcp_port_in_pause_list.append(ip)
down_xfcp_port_logic_list.append(
port.create_logic(clk=clk,
rst=rst,
xfcp_in_tdata=down_xfcp_out_tdata_list[k],
xfcp_in_tvalid=down_xfcp_out_tvalid_list[k],
xfcp_in_tready=down_xfcp_out_tready_list[k],
xfcp_in_tlast=down_xfcp_out_tlast_list[k],
xfcp_in_tuser=down_xfcp_out_tuser_list[k],
xfcp_out_tdata=down_xfcp_in_tdata_list[k],
xfcp_out_tvalid=down_xfcp_in_tvalid_list[k],
xfcp_out_tready=down_xfcp_in_tready_list[k],
xfcp_out_tlast=down_xfcp_in_tlast_list[k],
xfcp_out_tuser=down_xfcp_in_tuser_list[k],
pause_source=ip,
pause_sink=op,
name='down_xfcp_port_%d' % k))
# DUT
if os.system(build_cmd):
raise Exception("Error running build command")
dut = Cosimulation("vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
up_xfcp_in_tdata=up_xfcp_in_tdata,
up_xfcp_in_tvalid=up_xfcp_in_tvalid,
up_xfcp_in_tready=up_xfcp_in_tready,
up_xfcp_in_tlast=up_xfcp_in_tlast,
up_xfcp_in_tuser=up_xfcp_in_tuser,
up_xfcp_out_tdata=up_xfcp_out_tdata,
up_xfcp_out_tvalid=up_xfcp_out_tvalid,
up_xfcp_out_tready=up_xfcp_out_tready,
up_xfcp_out_tlast=up_xfcp_out_tlast,
up_xfcp_out_tuser=up_xfcp_out_tuser,
down_xfcp_in_tdata=down_xfcp_in_tdata,
down_xfcp_in_tvalid=down_xfcp_in_tvalid,
down_xfcp_in_tready=down_xfcp_in_tready,
down_xfcp_in_tlast=down_xfcp_in_tlast,
down_xfcp_in_tuser=down_xfcp_in_tuser,
down_xfcp_out_tdata=down_xfcp_out_tdata,
down_xfcp_out_tvalid=down_xfcp_out_tvalid,
down_xfcp_out_tready=down_xfcp_out_tready,
down_xfcp_out_tlast=down_xfcp_out_tlast,
down_xfcp_out_tuser=down_xfcp_out_tuser)
@always(delay(4))
def clkgen():
clk.next = not clk
def wait_normal():
i = 4
while i > 0:
i = max(0, i - 1)
if not up_xfcp_port.idle() or not down_xfcp_port_list[0].idle(
) or not down_xfcp_port_list[1].idle() or not down_xfcp_port_list[
2].idle() or not down_xfcp_port_list[3].idle():
i = 4
yield clk.posedge
def wait_pause_source():
i = 2
while i > 0:
i = max(0, i - 1)
if not up_xfcp_port.idle() or not down_xfcp_port_list[0].idle(
) or not down_xfcp_port_list[1].idle() or not down_xfcp_port_list[
2].idle() or not down_xfcp_port_list[3].idle():
i = 2
up_xfcp_port_in_pause.next = True
down_xfcp_port_in_pause_list[0].next = True
down_xfcp_port_in_pause_list[1].next = True
down_xfcp_port_in_pause_list[2].next = True
down_xfcp_port_in_pause_list[3].next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
up_xfcp_port_in_pause.next = False
down_xfcp_port_in_pause_list[0].next = False
down_xfcp_port_in_pause_list[1].next = False
down_xfcp_port_in_pause_list[2].next = False
down_xfcp_port_in_pause_list[3].next = False
yield clk.posedge
def wait_pause_sink():
i = 2
while i > 0:
i = max(0, i - 1)
if not up_xfcp_port.idle() or not down_xfcp_port_list[0].idle(
) or not down_xfcp_port_list[1].idle() or not down_xfcp_port_list[
2].idle() or not down_xfcp_port_list[3].idle():
i = 2
up_xfcp_port_out_pause.next = True
down_xfcp_port_out_pause_list[0].next = True
down_xfcp_port_out_pause_list[1].next = True
down_xfcp_port_out_pause_list[2].next = True
down_xfcp_port_out_pause_list[3].next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
up_xfcp_port_out_pause.next = False
down_xfcp_port_out_pause_list[0].next = False
down_xfcp_port_out_pause_list[1].next = False
down_xfcp_port_out_pause_list[2].next = False
down_xfcp_port_out_pause_list[3].next = False
yield clk.posedge
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
# testbench stimulus
yield clk.posedge
print("test 1: downstream packets")
current_test.next = 1
pkt0 = xfcp.XFCPFrame()
pkt0.path = [0]
pkt0.ptype = 1
pkt0.payload = bytearray(range(8))
pkt1 = xfcp.XFCPFrame(pkt0)
pkt1.path = [1]
pkt2 = xfcp.XFCPFrame(pkt0)
pkt2.path = [2]
pkt3 = xfcp.XFCPFrame(pkt0)
pkt3.path = [3]
for wait in wait_normal, wait_pause_source, wait_pause_sink:
up_xfcp_port.send(pkt0)
up_xfcp_port.send(pkt1)
up_xfcp_port.send(pkt2)
up_xfcp_port.send(pkt3)
yield clk.posedge
yield wait()
yield clk.posedge
rx_pkt = down_xfcp_port_list[0].recv()
check_pkt = xfcp.XFCPFrame(pkt0)
check_pkt.path = check_pkt.path[1:]
print(rx_pkt)
assert rx_pkt == check_pkt
rx_pkt = down_xfcp_port_list[1].recv()
check_pkt = xfcp.XFCPFrame(pkt1)
check_pkt.path = check_pkt.path[1:]
print(rx_pkt)
assert rx_pkt == check_pkt
rx_pkt = down_xfcp_port_list[2].recv()
check_pkt = xfcp.XFCPFrame(pkt2)
check_pkt.path = check_pkt.path[1:]
print(rx_pkt)
assert rx_pkt == check_pkt
rx_pkt = down_xfcp_port_list[3].recv()
check_pkt = xfcp.XFCPFrame(pkt3)
check_pkt.path = check_pkt.path[1:]
print(rx_pkt)
assert rx_pkt == check_pkt
yield delay(100)
yield clk.posedge
print("test 2: upstream packets")
current_test.next = 2
pkt = xfcp.XFCPFrame()
pkt.ptype = 1
pkt.payload = bytearray(range(8))
for wait in wait_normal, wait_pause_source, wait_pause_sink:
down_xfcp_port_list[0].send(pkt)
yield clk.posedge
down_xfcp_port_list[1].send(pkt)
down_xfcp_port_list[2].send(pkt)
down_xfcp_port_list[3].send(pkt)
yield clk.posedge
yield wait()
yield clk.posedge
rx_pkt = up_xfcp_port.recv()
check_pkt = xfcp.XFCPFrame(pkt)
check_pkt.path.insert(0, 0)
print(rx_pkt)
assert rx_pkt == check_pkt
rx_pkt = up_xfcp_port.recv()
check_pkt = xfcp.XFCPFrame(pkt)
check_pkt.path.insert(0, 1)
print(rx_pkt)
assert rx_pkt == check_pkt
rx_pkt = up_xfcp_port.recv()
check_pkt = xfcp.XFCPFrame(pkt)
check_pkt.path.insert(0, 2)
print(rx_pkt)
assert rx_pkt == check_pkt
rx_pkt = up_xfcp_port.recv()
check_pkt = xfcp.XFCPFrame(pkt)
check_pkt.path.insert(0, 3)
print(rx_pkt)
assert rx_pkt == check_pkt
yield delay(100)
yield clk.posedge
print("test 3: test id")
current_test.next = 3
pkt = xfcp.XFCPFrame()
pkt.ptype = 0xFE
pkt.payload = b''
for wait in wait_normal, wait_pause_source, wait_pause_sink:
up_xfcp_port.send(pkt)
yield clk.posedge
yield wait()
yield clk.posedge
rx_pkt = up_xfcp_port.recv()
print(rx_pkt)
assert rx_pkt.ptype == 0xff
assert len(rx_pkt.payload.data) == 32
yield delay(100)
yield clk.posedge
print("test 4: test id with trailing bytes")
current_test.next = 4
pkt1 = xfcp.XFCPFrame()
pkt1.ptype = 0xFE
pkt1.payload = b'\x00' * 256
pkt2 = xfcp.XFCPFrame()
pkt2.ptype = 0xFE
pkt2.payload = b'\x00' * 8
for wait in wait_normal, wait_pause_source, wait_pause_sink:
up_xfcp_port.send(pkt1)
up_xfcp_port.send(pkt2)
yield clk.posedge
yield wait()
yield clk.posedge
rx_pkt = up_xfcp_port.recv()
print(rx_pkt)
assert rx_pkt.ptype == 0xff
assert len(rx_pkt.payload.data) == 32
rx_pkt = up_xfcp_port.recv()
print(rx_pkt)
assert rx_pkt.ptype == 0xff
assert len(rx_pkt.payload.data) == 32
yield delay(100)
yield clk.posedge
print("test 5: test id with rpath")
current_test.next = 5
pkt = xfcp.XFCPFrame()
pkt.rpath = [1, 2, 3]
pkt.ptype = 0xFE
pkt.payload = b'\x00' * 8
for wait in wait_normal, wait_pause_source, wait_pause_sink:
up_xfcp_port.send(pkt)
yield clk.posedge
yield wait()
yield clk.posedge
rx_pkt = up_xfcp_port.recv()
print(rx_pkt)
assert rx_pkt.rpath == [1, 2, 3]
assert rx_pkt.ptype == 0xff
assert len(rx_pkt.payload.data) == 32
yield delay(100)
yield clk.posedge
print("test 6: test invalid packets")
current_test.next = 6
pkt1 = xfcp.XFCPFrame()
pkt1.ptype = 0x99
pkt1.payload = b'\x00' * 8
pkt2 = xfcp.XFCPFrame()
pkt2.path = [10]
pkt2.ptype = 0xFE
pkt2.payload = b''
for wait in wait_normal, wait_pause_source, wait_pause_sink:
up_xfcp_port.send(pkt1)
up_xfcp_port.send(pkt2)
yield clk.posedge
yield wait()
yield clk.posedge
rx_pkt = up_xfcp_port.recv()
assert rx_pkt is None
rx_pkt = down_xfcp_port_list[0].recv()
assert rx_pkt is None
rx_pkt = down_xfcp_port_list[1].recv()
assert rx_pkt is None
rx_pkt = down_xfcp_port_list[2].recv()
assert rx_pkt is None
rx_pkt = down_xfcp_port_list[3].recv()
assert rx_pkt is None
yield delay(100)
raise StopSimulation
return instances()
def bench():
# Parameters
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
s_eth_axis_tdata = Signal(intbv(0)[8:])
s_eth_axis_tvalid = Signal(bool(0))
s_eth_axis_tlast = Signal(bool(0))
s_eth_axis_tuser = Signal(bool(0))
m_eth_axis_tready = Signal(bool(0))
down_xfcp_in_tdata = Signal(intbv(0)[8:])
down_xfcp_in_tvalid = Signal(bool(0))
down_xfcp_in_tlast = Signal(bool(0))
down_xfcp_in_tuser = Signal(bool(0))
down_xfcp_out_tready = Signal(bool(0))
local_mac = Signal(intbv(0)[48:])
local_ip = Signal(intbv(0)[32:])
local_port = Signal(intbv(0)[16:])
gateway_ip = Signal(intbv(0)[32:])
subnet_mask = Signal(intbv(0)[32:])
# Outputs
s_eth_axis_tready = Signal(bool(0))
m_eth_axis_tdata = Signal(intbv(0)[8:])
m_eth_axis_tvalid = Signal(bool(0))
m_eth_axis_tlast = Signal(bool(0))
m_eth_axis_tuser = Signal(bool(0))
down_xfcp_in_tready = Signal(bool(0))
down_xfcp_out_tdata = Signal(intbv(0)[8:])
down_xfcp_out_tvalid = Signal(bool(0))
down_xfcp_out_tlast = Signal(bool(0))
down_xfcp_out_tuser = Signal(bool(0))
# sources and sinks
eth_source_pause = Signal(bool(0))
eth_sink_pause = Signal(bool(0))
eth_source = axis_ep.AXIStreamSource()
eth_source_logic = eth_source.create_logic(clk,
rst,
tdata=s_eth_axis_tdata,
tvalid=s_eth_axis_tvalid,
tready=s_eth_axis_tready,
tlast=s_eth_axis_tlast,
tuser=s_eth_axis_tuser,
pause=eth_source_pause,
name='eth_source')
eth_sink = axis_ep.AXIStreamSink()
eth_sink_logic = eth_sink.create_logic(clk,
rst,
tdata=m_eth_axis_tdata,
tvalid=m_eth_axis_tvalid,
tready=m_eth_axis_tready,
tlast=m_eth_axis_tlast,
tuser=m_eth_axis_tuser,
pause=eth_sink_pause,
name='eth_sink')
# XFCP ports
down_xfcp_port = xfcp.XFCPPort()
down_xfcp_port_logic = down_xfcp_port.create_logic(
clk=clk,
rst=rst,
xfcp_in_tdata=down_xfcp_out_tdata,
xfcp_in_tvalid=down_xfcp_out_tvalid,
xfcp_in_tready=down_xfcp_out_tready,
xfcp_in_tlast=down_xfcp_out_tlast,
xfcp_in_tuser=down_xfcp_out_tuser,
xfcp_out_tdata=down_xfcp_in_tdata,
xfcp_out_tvalid=down_xfcp_in_tvalid,
xfcp_out_tready=down_xfcp_in_tready,
xfcp_out_tlast=down_xfcp_in_tlast,
xfcp_out_tuser=down_xfcp_in_tuser,
name='down_xfcp_port')
# DUT
if os.system(build_cmd):
raise Exception("Error running build command")
dut = Cosimulation("vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
s_eth_axis_tdata=s_eth_axis_tdata,
s_eth_axis_tvalid=s_eth_axis_tvalid,
s_eth_axis_tready=s_eth_axis_tready,
s_eth_axis_tlast=s_eth_axis_tlast,
s_eth_axis_tuser=s_eth_axis_tuser,
m_eth_axis_tdata=m_eth_axis_tdata,
m_eth_axis_tvalid=m_eth_axis_tvalid,
m_eth_axis_tready=m_eth_axis_tready,
m_eth_axis_tlast=m_eth_axis_tlast,
m_eth_axis_tuser=m_eth_axis_tuser,
down_xfcp_in_tdata=down_xfcp_in_tdata,
down_xfcp_in_tvalid=down_xfcp_in_tvalid,
down_xfcp_in_tready=down_xfcp_in_tready,
down_xfcp_in_tlast=down_xfcp_in_tlast,
down_xfcp_in_tuser=down_xfcp_in_tuser,
down_xfcp_out_tdata=down_xfcp_out_tdata,
down_xfcp_out_tvalid=down_xfcp_out_tvalid,
down_xfcp_out_tready=down_xfcp_out_tready,
down_xfcp_out_tlast=down_xfcp_out_tlast,
down_xfcp_out_tuser=down_xfcp_out_tuser,
local_mac=local_mac,
local_ip=local_ip,
local_port=local_port,
gateway_ip=gateway_ip,
subnet_mask=subnet_mask)
@always(delay(4))
def clkgen():
clk.next = not clk
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
# testbench stimulus
local_mac.next = 0x020000000000
local_ip.next = 0xc0a80180
local_port.next = 14000
gateway_ip.next = 0xc0a80101
subnet_mask.next = 0xffffff00
yield clk.posedge
print("test 1: test UDP RX packet")
current_test.next = 1
pkt = xfcp.XFCPFrame()
pkt.path = [1, 2, 3]
pkt.rpath = [4]
pkt.ptype = 1
pkt.payload = bytearray(range(32))
test_frame = udp_ep.UDPFrame()
test_frame.eth_dest_mac = 0x020000000000
test_frame.eth_src_mac = 0xDAD1D2D3D4D5
test_frame.eth_type = 0x0800
test_frame.ip_version = 4
test_frame.ip_ihl = 5
test_frame.ip_dscp = 0
test_frame.ip_ecn = 0
test_frame.ip_length = None
test_frame.ip_identification = 0
test_frame.ip_flags = 2
test_frame.ip_fragment_offset = 0
test_frame.ip_ttl = 64
test_frame.ip_protocol = 0x11
test_frame.ip_header_checksum = None
test_frame.ip_source_ip = 0xc0a80181
test_frame.ip_dest_ip = 0xc0a80180
test_frame.udp_source_port = 1234
test_frame.udp_dest_port = 14000
test_frame.payload = pkt.build_axis()
test_frame.build()
eth_source.send(test_frame.build_eth().build_axis())
yield down_xfcp_port.wait()
rx_pkt = down_xfcp_port.recv()
print(rx_pkt)
assert rx_pkt == pkt
assert eth_source.empty()
assert eth_sink.empty()
yield delay(100)
yield clk.posedge
print("test 2: test UDP TX packet")
current_test.next = 2
pkt = xfcp.XFCPFrame()
pkt.path = [1, 2, 3]
pkt.rpath = [4]
pkt.ptype = 1
pkt.payload = bytearray(range(32))
down_xfcp_port.send(pkt)
# wait for ARP request packet
yield eth_sink.wait()
rx_frame = eth_sink.recv()
check_eth_frame = eth_ep.EthFrame()
check_eth_frame.parse_axis(rx_frame.data)
check_frame = arp_ep.ARPFrame()
check_frame.parse_eth(check_eth_frame)
print(check_frame)
assert check_frame.eth_dest_mac == 0xFFFFFFFFFFFF
assert check_frame.eth_src_mac == 0x020000000000
assert check_frame.eth_type == 0x0806
assert check_frame.arp_htype == 0x0001
assert check_frame.arp_ptype == 0x0800
assert check_frame.arp_hlen == 6
assert check_frame.arp_plen == 4
assert check_frame.arp_oper == 1
assert check_frame.arp_sha == 0x020000000000
assert check_frame.arp_spa == 0xc0a80180
assert check_frame.arp_tha == 0x000000000000
assert check_frame.arp_tpa == 0xc0a80181
# generate response
arp_frame = arp_ep.ARPFrame()
arp_frame.eth_dest_mac = 0x020000000000
arp_frame.eth_src_mac = 0xDAD1D2D3D4D5
arp_frame.eth_type = 0x0806
arp_frame.arp_htype = 0x0001
arp_frame.arp_ptype = 0x0800
arp_frame.arp_hlen = 6
arp_frame.arp_plen = 4
arp_frame.arp_oper = 2
arp_frame.arp_sha = 0xDAD1D2D3D4D5
arp_frame.arp_spa = 0xc0a80181
arp_frame.arp_tha = 0x020000000000
arp_frame.arp_tpa = 0xc0a80180
eth_source.send(arp_frame.build_eth().build_axis())
yield eth_sink.wait()
rx_frame = eth_sink.recv()
check_eth_frame = eth_ep.EthFrame()
check_eth_frame.parse_axis(rx_frame.data)
check_frame = udp_ep.UDPFrame()
check_frame.parse_eth(check_eth_frame)
print(check_frame)
assert check_frame.eth_dest_mac == 0xDAD1D2D3D4D5
assert check_frame.eth_src_mac == 0x020000000000
assert check_frame.eth_type == 0x0800
assert check_frame.ip_version == 4
assert check_frame.ip_ihl == 5
assert check_frame.ip_dscp == 0
assert check_frame.ip_ecn == 0
assert check_frame.ip_identification == 0
assert check_frame.ip_flags == 2
assert check_frame.ip_fragment_offset == 0
assert check_frame.ip_ttl == 64
assert check_frame.ip_protocol == 0x11
assert check_frame.ip_source_ip == 0xc0a80180
assert check_frame.ip_dest_ip == 0xc0a80181
assert check_frame.udp_source_port == 14000
assert check_frame.udp_dest_port == 1234
rx_pkt = xfcp.XFCPFrame()
rx_pkt.parse_axis(check_frame.payload.data)
print(rx_pkt)
assert rx_pkt == pkt
assert eth_source.empty()
assert eth_sink.empty()
yield delay(100)
raise StopSimulation
return instances()
def bench():
# Parameters
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
uart_rxd = Signal(bool(1))
down_xfcp_in_tdata = Signal(intbv(0)[8:])
down_xfcp_in_tvalid = Signal(bool(0))
down_xfcp_in_tlast = Signal(bool(0))
down_xfcp_in_tuser = Signal(bool(0))
down_xfcp_out_tready = Signal(bool(0))
prescale = Signal(intbv(0)[16:])
# Outputs
uart_txd = Signal(bool(1))
down_xfcp_in_tready = Signal(bool(0))
down_xfcp_out_tdata = Signal(intbv(0)[8:])
down_xfcp_out_tvalid = Signal(bool(0))
down_xfcp_out_tlast = Signal(bool(0))
down_xfcp_out_tuser = Signal(bool(0))
# sources and sinks
uart_source = uart_ep.UARTSource()
uart_source_logic = uart_source.create_logic(clk,
rst,
txd=uart_rxd,
prescale=prescale,
name='uart_source')
uart_sink = uart_ep.UARTSink()
uart_sink_logic = uart_sink.create_logic(clk,
rst,
rxd=uart_txd,
prescale=prescale,
name='uart_sink')
# XFCP ports
down_xfcp_port = xfcp.XFCPPort()
down_xfcp_port_logic = down_xfcp_port.create_logic(
clk=clk,
rst=rst,
xfcp_in_tdata=down_xfcp_out_tdata,
xfcp_in_tvalid=down_xfcp_out_tvalid,
xfcp_in_tready=down_xfcp_out_tready,
xfcp_in_tlast=down_xfcp_out_tlast,
xfcp_in_tuser=down_xfcp_out_tuser,
xfcp_out_tdata=down_xfcp_in_tdata,
xfcp_out_tvalid=down_xfcp_in_tvalid,
xfcp_out_tready=down_xfcp_in_tready,
xfcp_out_tlast=down_xfcp_in_tlast,
xfcp_out_tuser=down_xfcp_in_tuser,
name='down_xfcp_port')
# DUT
if os.system(build_cmd):
raise Exception("Error running build command")
dut = Cosimulation("vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
uart_rxd=uart_rxd,
uart_txd=uart_txd,
down_xfcp_in_tdata=down_xfcp_in_tdata,
down_xfcp_in_tvalid=down_xfcp_in_tvalid,
down_xfcp_in_tready=down_xfcp_in_tready,
down_xfcp_in_tlast=down_xfcp_in_tlast,
down_xfcp_in_tuser=down_xfcp_in_tuser,
down_xfcp_out_tdata=down_xfcp_out_tdata,
down_xfcp_out_tvalid=down_xfcp_out_tvalid,
down_xfcp_out_tready=down_xfcp_out_tready,
down_xfcp_out_tlast=down_xfcp_out_tlast,
down_xfcp_out_tuser=down_xfcp_out_tuser,
prescale=prescale)
@always(delay(4))
def clkgen():
clk.next = not clk
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
prescale.next = 1
# testbench stimulus
yield clk.posedge
print("test 1: receive")
current_test.next = 1
pkt = xfcp.XFCPFrame()
pkt.path = [1, 2, 3]
pkt.rpath = [4]
pkt.ptype = 1
pkt.payload = bytearray(range(32))
uart_source.write(pkt.build_axis_cobs().data + b'\x00')
rx_pkt = None
while rx_pkt is None:
yield clk.posedge
rx_pkt = down_xfcp_port.recv()
print(rx_pkt)
assert rx_pkt == pkt
yield delay(100)
yield clk.posedge
print("test 2: transmit")
current_test.next = 2
pkt = xfcp.XFCPFrame()
pkt.path = [1, 2, 3]
pkt.rpath = [4]
pkt.ptype = 1
pkt.payload = bytearray(range(32))
down_xfcp_port.send(pkt)
yield clk.posedge
rx_data = b''
while True:
if not uart_sink.empty():
b = bytearray(uart_sink.read(1))
rx_data += b
if b[0] == 0:
break
yield clk.posedge
rx_pkt = xfcp.XFCPFrame()
rx_pkt.parse_axis_cobs(rx_data[:-1])
print(rx_pkt)
assert rx_pkt == pkt
yield delay(100)
raise StopSimulation
return instances()
def bench():
# Parameters
XFCP_ID_TYPE = 0x0001
XFCP_ID_STR = "AXIL Master"
XFCP_EXT_ID = 0
XFCP_EXT_ID_STR = ""
COUNT_SIZE = 16
DATA_WIDTH = 32
ADDR_WIDTH = 32
STRB_WIDTH = (DATA_WIDTH / 8)
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
up_xfcp_in_tdata = Signal(intbv(0)[8:])
up_xfcp_in_tvalid = Signal(bool(0))
up_xfcp_in_tlast = Signal(bool(0))
up_xfcp_in_tuser = Signal(bool(0))
up_xfcp_out_tready = Signal(bool(0))
m_axil_awready = Signal(bool(0))
m_axil_wready = Signal(bool(0))
m_axil_bresp = Signal(intbv(0)[2:])
m_axil_bvalid = Signal(bool(0))
m_axil_arready = Signal(bool(0))
m_axil_rdata = Signal(intbv(0)[DATA_WIDTH:])
m_axil_rresp = Signal(intbv(0)[2:])
m_axil_rvalid = Signal(bool(0))
# Outputs
up_xfcp_in_tready = Signal(bool(0))
up_xfcp_out_tdata = Signal(intbv(0)[8:])
up_xfcp_out_tvalid = Signal(bool(0))
up_xfcp_out_tlast = Signal(bool(0))
up_xfcp_out_tuser = Signal(bool(0))
m_axil_awaddr = Signal(intbv(0)[ADDR_WIDTH:])
m_axil_awprot = Signal(intbv(0)[3:])
m_axil_awvalid = Signal(bool(0))
m_axil_wdata = Signal(intbv(0)[DATA_WIDTH:])
m_axil_wstrb = Signal(intbv(0)[STRB_WIDTH:])
m_axil_wvalid = Signal(bool(0))
m_axil_bready = Signal(bool(0))
m_axil_araddr = Signal(intbv(0)[ADDR_WIDTH:])
m_axil_arprot = Signal(intbv(0)[3:])
m_axil_arvalid = Signal(bool(0))
m_axil_rready = Signal(bool(0))
# XFCP ports
up_xfcp_port_out_pause = Signal(bool(0))
up_xfcp_port_in_pause = Signal(bool(0))
up_xfcp_port = xfcp.XFCPPort()
up_xfcp_port_logic = up_xfcp_port.create_logic(
clk=clk,
rst=rst,
xfcp_in_tdata=up_xfcp_out_tdata,
xfcp_in_tvalid=up_xfcp_out_tvalid,
xfcp_in_tready=up_xfcp_out_tready,
xfcp_in_tlast=up_xfcp_out_tlast,
xfcp_in_tuser=up_xfcp_out_tuser,
xfcp_out_tdata=up_xfcp_in_tdata,
xfcp_out_tvalid=up_xfcp_in_tvalid,
xfcp_out_tready=up_xfcp_in_tready,
xfcp_out_tlast=up_xfcp_in_tlast,
xfcp_out_tuser=up_xfcp_in_tuser,
pause_source=up_xfcp_port_in_pause,
pause_sink=up_xfcp_port_out_pause,
name='up_xfcp_port')
# AXI4-Lite RAM model
axil_ram_inst = axil.AXILiteRam(2**16)
axil_ram_pause = Signal(bool(False))
axil_ram_port0 = axil_ram_inst.create_port(clk,
s_axil_awaddr=m_axil_awaddr,
s_axil_awprot=m_axil_awprot,
s_axil_awvalid=m_axil_awvalid,
s_axil_awready=m_axil_awready,
s_axil_wdata=m_axil_wdata,
s_axil_wstrb=m_axil_wstrb,
s_axil_wvalid=m_axil_wvalid,
s_axil_wready=m_axil_wready,
s_axil_bresp=m_axil_bresp,
s_axil_bvalid=m_axil_bvalid,
s_axil_bready=m_axil_bready,
s_axil_araddr=m_axil_araddr,
s_axil_arprot=m_axil_arprot,
s_axil_arvalid=m_axil_arvalid,
s_axil_arready=m_axil_arready,
s_axil_rdata=m_axil_rdata,
s_axil_rresp=m_axil_rresp,
s_axil_rvalid=m_axil_rvalid,
s_axil_rready=m_axil_rready,
pause=axil_ram_pause,
name='port0')
# DUT
if os.system(build_cmd):
raise Exception("Error running build command")
dut = Cosimulation("vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
up_xfcp_in_tdata=up_xfcp_in_tdata,
up_xfcp_in_tvalid=up_xfcp_in_tvalid,
up_xfcp_in_tready=up_xfcp_in_tready,
up_xfcp_in_tlast=up_xfcp_in_tlast,
up_xfcp_in_tuser=up_xfcp_in_tuser,
up_xfcp_out_tdata=up_xfcp_out_tdata,
up_xfcp_out_tvalid=up_xfcp_out_tvalid,
up_xfcp_out_tready=up_xfcp_out_tready,
up_xfcp_out_tlast=up_xfcp_out_tlast,
up_xfcp_out_tuser=up_xfcp_out_tuser,
m_axil_awaddr=m_axil_awaddr,
m_axil_awprot=m_axil_awprot,
m_axil_awvalid=m_axil_awvalid,
m_axil_awready=m_axil_awready,
m_axil_wdata=m_axil_wdata,
m_axil_wstrb=m_axil_wstrb,
m_axil_wvalid=m_axil_wvalid,
m_axil_wready=m_axil_wready,
m_axil_bresp=m_axil_bresp,
m_axil_bvalid=m_axil_bvalid,
m_axil_bready=m_axil_bready,
m_axil_araddr=m_axil_araddr,
m_axil_arprot=m_axil_arprot,
m_axil_arvalid=m_axil_arvalid,
m_axil_arready=m_axil_arready,
m_axil_rdata=m_axil_rdata,
m_axil_rresp=m_axil_rresp,
m_axil_rvalid=m_axil_rvalid,
m_axil_rready=m_axil_rready)
@always(delay(4))
def clkgen():
clk.next = not clk
def wait_normal():
i = 4
while i > 0:
i = max(0, i - 1)
if not up_xfcp_port.idle(
) or m_axil_awvalid or m_axil_wvalid or m_axil_bvalid or m_axil_arvalid or m_axil_rvalid:
i = 4
yield clk.posedge
def wait_pause_source():
i = 2
while i > 0:
i = max(0, i - 1)
if not up_xfcp_port.idle(
) or m_axil_awvalid or m_axil_wvalid or m_axil_bvalid or m_axil_arvalid or m_axil_rvalid:
i = 2
up_xfcp_port_in_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
up_xfcp_port_in_pause.next = False
yield clk.posedge
def wait_pause_sink():
i = 2
while i > 0:
i = max(0, i - 1)
if not up_xfcp_port.idle(
) or m_axil_awvalid or m_axil_wvalid or m_axil_bvalid or m_axil_arvalid or m_axil_rvalid:
i = 2
up_xfcp_port_out_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
up_xfcp_port_out_pause.next = False
yield clk.posedge
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
# testbench stimulus
yield clk.posedge
print("test 1: test write")
current_test.next = 1
pkt = xfcp.XFCPFrame()
pkt.ptype = 0x12
pkt.payload = bytearray(struct.pack('<IH', 0, 4) + b'\x11\x22\x33\x44')
for wait in wait_normal, wait_pause_source, wait_pause_sink:
up_xfcp_port.send(pkt)
yield clk.posedge
yield wait()
yield clk.posedge
data = axil_ram_inst.read_mem(0, 32)
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c) for c in bytearray(data[i:i + 16]))))
assert axil_ram_inst.read_mem(0, 4) == b'\x11\x22\x33\x44'
rx_pkt = up_xfcp_port.recv()
print(rx_pkt)
assert rx_pkt.ptype == 0x13
assert rx_pkt.payload.data == struct.pack('<IH', 0, 4)
yield delay(100)
yield clk.posedge
print("test 2: test read")
current_test.next = 2
pkt = xfcp.XFCPFrame()
pkt.ptype = 0x10
pkt.payload = bytearray(struct.pack('<IH', 0, 4))
for wait in wait_normal, wait_pause_source, wait_pause_sink:
up_xfcp_port.send(pkt)
yield clk.posedge
yield wait()
yield clk.posedge
rx_pkt = up_xfcp_port.recv()
print(rx_pkt)
assert rx_pkt.ptype == 0x11
assert rx_pkt.payload.data == struct.pack('<IH', 0,
4) + b'\x11\x22\x33\x44'
yield delay(100)
yield clk.posedge
print("test 3: various writes")
current_test.next = 3
for length in range(1, 8):
for offset in range(4):
pkt = xfcp.XFCPFrame()
pkt.ptype = 0x12
pkt.payload = bytearray(
struct.pack('<IH', 256 *
(16 * offset + length) + offset, length) +
b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length])
for wait in wait_normal, wait_pause_source, wait_pause_sink:
up_xfcp_port.send(pkt)
yield clk.posedge
yield wait()
yield clk.posedge
data = axil_ram_inst.read_mem(256 * (16 * offset + length),
32)
for i in range(0, len(data), 16):
print(" ".join(("{:02x}".format(c)
for c in bytearray(data[i:i + 16]))))
assert axil_ram_inst.read_mem(
256 * (16 * offset + length) + offset, length
) == b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length]
rx_pkt = up_xfcp_port.recv()
print(rx_pkt)
assert rx_pkt.ptype == 0x13
assert rx_pkt.payload.data == struct.pack(
'<IH', 256 * (16 * offset + length) + offset, length)
yield delay(100)
yield clk.posedge
print("test 4: various reads")
current_test.next = 4
for length in range(1, 8):
for offset in range(4):
pkt = xfcp.XFCPFrame()
pkt.ptype = 0x10
pkt.payload = bytearray(
struct.pack('<IH', 256 * (16 * offset + length) + offset,
length))
for wait in wait_normal, wait_pause_source, wait_pause_sink:
up_xfcp_port.send(pkt)
yield clk.posedge
yield wait()
yield clk.posedge
rx_pkt = up_xfcp_port.recv()
print(rx_pkt)
assert rx_pkt.ptype == 0x11
assert rx_pkt.payload.data == struct.pack(
'<IH', 256 * (16 * offset + length) + offset,
length) + b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length]
yield delay(100)
yield clk.posedge
print("test 5: test trailing padding")
current_test.next = 5
pkt1 = xfcp.XFCPFrame()
pkt1.ptype = 0x12
pkt1.payload = bytearray(struct.pack('<IH', 7, 1) + b'\xAA')
pkt2 = xfcp.XFCPFrame()
pkt2.ptype = 0x12
pkt2.payload = bytearray(
struct.pack('<IH', 8, 1) + b'\xBB' + b'\x00' * 8)
pkt3 = xfcp.XFCPFrame()
pkt3.ptype = 0x10
pkt3.payload = bytearray(struct.pack('<IH', 7, 1) + b'\x00' * 8)
pkt4 = xfcp.XFCPFrame()
pkt4.ptype = 0x10
pkt4.payload = bytearray(struct.pack('<IH', 7, 1) + b'\x00' * 1)
pkt5 = xfcp.XFCPFrame()
pkt5.ptype = 0x12
pkt5.payload = bytearray(struct.pack('<IH', 9, 1) + b'\xCC')
for wait in wait_normal, wait_pause_source, wait_pause_sink:
up_xfcp_port.send(pkt1)
up_xfcp_port.send(pkt2)
up_xfcp_port.send(pkt3)
up_xfcp_port.send(pkt4)
up_xfcp_port.send(pkt5)
yield clk.posedge
yield wait()
yield clk.posedge
data = axil_ram_inst.read_mem(0, 32)
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c) for c in bytearray(data[i:i + 16]))))
assert axil_ram_inst.read_mem(7, 3) == b'\xAA\xBB\xCC'
rx_pkt = up_xfcp_port.recv()
print(rx_pkt)
assert rx_pkt.ptype == 0x13
assert rx_pkt.payload.data == struct.pack('<IH', 7, 1)
rx_pkt = up_xfcp_port.recv()
print(rx_pkt)
assert rx_pkt.ptype == 0x13
assert rx_pkt.payload.data == struct.pack('<IH', 8, 1)
rx_pkt = up_xfcp_port.recv()
print(rx_pkt)
assert rx_pkt.ptype == 0x11
assert rx_pkt.payload.data == struct.pack('<IH', 7, 1) + b'\xAA'
rx_pkt = up_xfcp_port.recv()
print(rx_pkt)
assert rx_pkt.ptype == 0x11
assert rx_pkt.payload.data == struct.pack('<IH', 7, 1) + b'\xAA'
rx_pkt = up_xfcp_port.recv()
print(rx_pkt)
assert rx_pkt.ptype == 0x13
assert rx_pkt.payload.data == struct.pack('<IH', 9, 1)
yield delay(100)
yield clk.posedge
print("test 6: test id")
current_test.next = 6
pkt = xfcp.XFCPFrame()
pkt.ptype = 0xFE
pkt.payload = b''
for wait in wait_normal, wait_pause_source, wait_pause_sink:
up_xfcp_port.send(pkt)
yield clk.posedge
yield wait()
yield clk.posedge
rx_pkt = up_xfcp_port.recv()
print(rx_pkt)
assert rx_pkt.ptype == 0xff
assert len(rx_pkt.payload.data) == 32
yield delay(100)
yield clk.posedge
print("test 7: test id with trailing bytes")
current_test.next = 7
pkt1 = xfcp.XFCPFrame()
pkt1.ptype = 0xFE
pkt1.payload = b'\0' * 256
pkt2 = xfcp.XFCPFrame()
pkt2.ptype = 0xFE
pkt2.payload = b'\0' * 8
for wait in wait_normal, wait_pause_source, wait_pause_sink:
up_xfcp_port.send(pkt1)
up_xfcp_port.send(pkt2)
yield clk.posedge
yield wait()
yield clk.posedge
rx_pkt = up_xfcp_port.recv()
print(rx_pkt)
assert rx_pkt.ptype == 0xff
assert len(rx_pkt.payload.data) == 32
rx_pkt = up_xfcp_port.recv()
print(rx_pkt)
assert rx_pkt.ptype == 0xff
assert len(rx_pkt.payload.data) == 32
yield delay(100)
yield clk.posedge
print("test 8: test with rpath")
current_test.next = 8
pkt1 = xfcp.XFCPFrame()
pkt1.rpath = [1, 2, 3]
pkt1.ptype = 0xFE
pkt1.payload = b'\0' * 8
pkt2 = xfcp.XFCPFrame()
pkt2.rpath = [4, 5, 6]
pkt2.ptype = 0x10
pkt2.payload = bytearray(struct.pack('<IH', 0, 4))
for wait in wait_normal, wait_pause_source, wait_pause_sink:
up_xfcp_port.send(pkt1)
up_xfcp_port.send(pkt2)
yield clk.posedge
yield wait()
yield clk.posedge
rx_pkt = up_xfcp_port.recv()
print(rx_pkt)
assert rx_pkt.rpath == [1, 2, 3]
assert rx_pkt.ptype == 0xff
assert len(rx_pkt.payload.data) == 32
rx_pkt = up_xfcp_port.recv()
print(rx_pkt)
assert rx_pkt.rpath == [4, 5, 6]
assert rx_pkt.ptype == 0x11
assert rx_pkt.payload.data == struct.pack('<IH', 0,
4) + b'\x11\x22\x33\x44'
yield delay(100)
yield clk.posedge
print("test 9: test invalid packets")
current_test.next = 9
pkt1 = xfcp.XFCPFrame()
pkt1.ptype = 0x99
pkt1.payload = b'\x00' * 8
pkt2 = xfcp.XFCPFrame()
pkt2.path = [0]
pkt2.ptype = 0xFE
pkt2.payload = b''
for wait in wait_normal, wait_pause_source, wait_pause_sink:
up_xfcp_port.send(pkt1)
up_xfcp_port.send(pkt2)
yield clk.posedge
yield wait()
yield clk.posedge
rx_pkt = up_xfcp_port.recv()
assert rx_pkt is None
yield delay(100)
raise StopSimulation
return instances()
def bench():
# Parameters
TARGET = "SIM"
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
btnu = Signal(bool(0))
btnl = Signal(bool(0))
btnd = Signal(bool(0))
btnr = Signal(bool(0))
btnc = Signal(bool(0))
sw = Signal(intbv(0)[4:])
i2c_scl_i = Signal(bool(1))
i2c_sda_i = Signal(bool(1))
phy_gmii_clk = Signal(bool(0))
phy_gmii_rst = Signal(bool(0))
phy_gmii_clk_en = Signal(bool(0))
phy_gmii_rxd = Signal(intbv(0)[8:])
phy_gmii_rx_dv = Signal(bool(0))
phy_gmii_rx_er = Signal(bool(0))
phy_int_n = Signal(bool(1))
uart_rxd = Signal(bool(1))
uart_cts = Signal(bool(1))
xfcp_mgt_up_tdata = Signal(intbv(0)[8:])
xfcp_mgt_up_tvalid = Signal(bool(0))
xfcp_mgt_up_tlast = Signal(bool(0))
xfcp_mgt_up_tuser = Signal(bool(0))
xfcp_mgt_down_tready = Signal(bool(0))
s1_scl_i = Signal(bool(1))
s1_sda_i = Signal(bool(1))
s2_scl_i = Signal(bool(1))
s2_sda_i = Signal(bool(1))
# Outputs
led = Signal(intbv(0)[8:])
i2c_scl_o = Signal(bool(1))
i2c_scl_t = Signal(bool(1))
i2c_sda_o = Signal(bool(1))
i2c_sda_t = Signal(bool(1))
phy_gmii_txd = Signal(intbv(0)[8:])
phy_gmii_tx_en = Signal(bool(0))
phy_gmii_tx_er = Signal(bool(0))
phy_reset_n = Signal(bool(0))
uart_txd = Signal(bool(1))
uart_rts = Signal(bool(1))
xfcp_mgt_up_tready = Signal(bool(0))
xfcp_mgt_down_tdata = Signal(intbv(0)[8:])
xfcp_mgt_down_tvalid = Signal(bool(0))
xfcp_mgt_down_tlast = Signal(bool(0))
xfcp_mgt_down_tuser = Signal(bool(0))
s1_scl_o = Signal(bool(1))
s1_scl_t = Signal(bool(1))
s1_sda_o = Signal(bool(1))
s1_sda_t = Signal(bool(1))
s2_scl_o = Signal(bool(1))
s2_scl_t = Signal(bool(1))
s2_sda_o = Signal(bool(1))
s2_sda_t = Signal(bool(1))
# sources and sinks
gmii_source = gmii_ep.GMIISource()
gmii_source_logic = gmii_source.create_logic(phy_gmii_clk,
phy_gmii_rst,
txd=phy_gmii_rxd,
tx_en=phy_gmii_rx_dv,
tx_er=phy_gmii_rx_er,
clk_enable=phy_gmii_clk_en,
name='gmii_source')
gmii_sink = gmii_ep.GMIISink()
gmii_sink_logic = gmii_sink.create_logic(phy_gmii_clk,
phy_gmii_rst,
rxd=phy_gmii_txd,
rx_dv=phy_gmii_tx_en,
rx_er=phy_gmii_tx_er,
clk_enable=phy_gmii_clk_en,
name='gmii_sink')
uart_source = uart_ep.UARTSource()
uart_source_logic = uart_source.create_logic(clk,
rst,
txd=uart_rxd,
prescale=int(125000000 /
(115200 * 8)),
name='uart_source')
uart_sink = uart_ep.UARTSink()
uart_sink_logic = uart_sink.create_logic(clk,
rst,
rxd=uart_txd,
prescale=int(125000000 /
(115200 * 8)),
name='uart_sink')
xfcp_mgt_port_out_pause = Signal(bool(0))
xfcp_mgt_port_in_pause = Signal(bool(0))
xfcp_mgt_port = xfcp.XFCPPort()
xfcp_mgt_port_logic = xfcp_mgt_port.create_logic(
clk=clk,
rst=rst,
xfcp_in_tdata=xfcp_mgt_down_tdata,
xfcp_in_tvalid=xfcp_mgt_down_tvalid,
xfcp_in_tready=xfcp_mgt_down_tready,
xfcp_in_tlast=xfcp_mgt_down_tlast,
xfcp_in_tuser=xfcp_mgt_down_tuser,
xfcp_out_tdata=xfcp_mgt_up_tdata,
xfcp_out_tvalid=xfcp_mgt_up_tvalid,
xfcp_out_tready=xfcp_mgt_up_tready,
xfcp_out_tlast=xfcp_mgt_up_tlast,
xfcp_out_tuser=xfcp_mgt_up_tuser,
pause_source=xfcp_mgt_port_in_pause,
pause_sink=xfcp_mgt_port_out_pause,
name='xfcp_mgt_port')
# I2C memory model 1
i2c_mem1 = i2c.I2CMem(1024)
i2c_mem_logic1 = i2c_mem1.create_logic(scl_i=s1_scl_i,
scl_o=s1_scl_o,
scl_t=s1_scl_t,
sda_i=s1_sda_i,
sda_o=s1_sda_o,
sda_t=s1_sda_t,
abw=2,
address=0x50,
latency=0,
name='slave1')
# I2C memory model 2
i2c_mem2 = i2c.I2CMem(1024)
i2c_mem_logic2 = i2c_mem2.create_logic(scl_i=s2_scl_i,
scl_o=s2_scl_o,
scl_t=s2_scl_t,
sda_i=s2_sda_i,
sda_o=s2_sda_o,
sda_t=s2_sda_t,
abw=2,
address=0x51,
latency=1000,
name='slave2')
# DUT
if os.system(build_cmd):
raise Exception("Error running build command")
dut = Cosimulation("vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
btnu=btnu,
btnl=btnl,
btnd=btnd,
btnr=btnr,
btnc=btnc,
sw=sw,
led=led,
i2c_scl_i=i2c_scl_i,
i2c_scl_o=i2c_scl_o,
i2c_scl_t=i2c_scl_t,
i2c_sda_i=i2c_sda_i,
i2c_sda_o=i2c_sda_o,
i2c_sda_t=i2c_sda_t,
phy_gmii_clk=phy_gmii_clk,
phy_gmii_rst=phy_gmii_rst,
phy_gmii_clk_en=phy_gmii_clk_en,
phy_gmii_rxd=phy_gmii_rxd,
phy_gmii_rx_dv=phy_gmii_rx_dv,
phy_gmii_rx_er=phy_gmii_rx_er,
phy_gmii_txd=phy_gmii_txd,
phy_gmii_tx_en=phy_gmii_tx_en,
phy_gmii_tx_er=phy_gmii_tx_er,
phy_reset_n=phy_reset_n,
phy_int_n=phy_int_n,
uart_rxd=uart_rxd,
uart_txd=uart_txd,
uart_rts=uart_rts,
uart_cts=uart_cts,
xfcp_mgt_up_tdata=xfcp_mgt_up_tdata,
xfcp_mgt_up_tvalid=xfcp_mgt_up_tvalid,
xfcp_mgt_up_tready=xfcp_mgt_up_tready,
xfcp_mgt_up_tlast=xfcp_mgt_up_tlast,
xfcp_mgt_up_tuser=xfcp_mgt_up_tuser,
xfcp_mgt_down_tdata=xfcp_mgt_down_tdata,
xfcp_mgt_down_tvalid=xfcp_mgt_down_tvalid,
xfcp_mgt_down_tready=xfcp_mgt_down_tready,
xfcp_mgt_down_tlast=xfcp_mgt_down_tlast,
xfcp_mgt_down_tuser=xfcp_mgt_down_tuser)
@always_comb
def bus():
# emulate I2C wired AND
i2c_scl_i.next = i2c_scl_o & s1_scl_o & s2_scl_o
i2c_sda_i.next = i2c_sda_o & s1_sda_o & s2_sda_o
s1_scl_i.next = i2c_scl_o & s1_scl_o & s2_scl_o
s1_sda_i.next = i2c_sda_o & s1_sda_o & s2_sda_o
s2_scl_i.next = i2c_scl_o & s1_scl_o & s2_scl_o
s2_sda_i.next = i2c_sda_o & s1_sda_o & s2_sda_o
@always(delay(4))
def clkgen():
clk.next = not clk
phy_gmii_clk.next = not phy_gmii_clk
clk_enable_rate = Signal(int(0))
clk_enable_div = Signal(int(0))
@always(clk.posedge)
def clk_enable_gen():
if clk_enable_div.next > 0:
phy_gmii_clk_en.next = 0
clk_enable_div.next = clk_enable_div - 1
else:
phy_gmii_clk_en.next = 1
clk_enable_div.next = clk_enable_rate - 1
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
phy_gmii_rst.next = 1
yield clk.posedge
rst.next = 0
phy_gmii_rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
# testbench stimulus
yield clk.posedge
print("test 1: enumerate via UDP")
current_test.next = 1
pkt = xfcp.XFCPFrame()
pkt.path = []
pkt.rpath = []
pkt.ptype = 0xfe
pkt.payload = b''
test_frame = udp_ep.UDPFrame()
test_frame.eth_dest_mac = 0x020000000000
test_frame.eth_src_mac = 0xDAD1D2D3D4D5
test_frame.eth_type = 0x0800
test_frame.ip_version = 4
test_frame.ip_ihl = 5
test_frame.ip_dscp = 0
test_frame.ip_ecn = 0
test_frame.ip_length = None
test_frame.ip_identification = 0
test_frame.ip_flags = 2
test_frame.ip_fragment_offset = 0
test_frame.ip_ttl = 64
test_frame.ip_protocol = 0x11
test_frame.ip_header_checksum = None
test_frame.ip_source_ip = 0xc0a80181
test_frame.ip_dest_ip = 0xc0a80180
test_frame.udp_source_port = 1234
test_frame.udp_dest_port = 14000
test_frame.payload = pkt.build_axis()
test_frame.build()
gmii_source.send(b'\x55\x55\x55\x55\x55\x55\x55\xD5' +
test_frame.build_eth().build_axis_fcs().data)
# wait for ARP request packet
rx_frame = None
while rx_frame is None:
yield clk.posedge
rx_frame = gmii_sink.recv()
check_eth_frame = eth_ep.EthFrame()
check_eth_frame.parse_axis_fcs(rx_frame.data[8:])
check_frame = arp_ep.ARPFrame()
check_frame.parse_eth(check_eth_frame)
print(check_frame)
assert check_frame.eth_dest_mac == 0xFFFFFFFFFFFF
assert check_frame.eth_src_mac == 0x020000000000
assert check_frame.eth_type == 0x0806
assert check_frame.arp_htype == 0x0001
assert check_frame.arp_ptype == 0x0800
assert check_frame.arp_hlen == 6
assert check_frame.arp_plen == 4
assert check_frame.arp_oper == 1
assert check_frame.arp_sha == 0x020000000000
assert check_frame.arp_spa == 0xc0a80180
assert check_frame.arp_tha == 0x000000000000
assert check_frame.arp_tpa == 0xc0a80181
# generate response
arp_frame = arp_ep.ARPFrame()
arp_frame.eth_dest_mac = 0x020000000000
arp_frame.eth_src_mac = 0xDAD1D2D3D4D5
arp_frame.eth_type = 0x0806
arp_frame.arp_htype = 0x0001
arp_frame.arp_ptype = 0x0800
arp_frame.arp_hlen = 6
arp_frame.arp_plen = 4
arp_frame.arp_oper = 2
arp_frame.arp_sha = 0xDAD1D2D3D4D5
arp_frame.arp_spa = 0xc0a80181
arp_frame.arp_tha = 0x020000000000
arp_frame.arp_tpa = 0xc0a80180
gmii_source.send(b'\x55\x55\x55\x55\x55\x55\x55\xD5' +
arp_frame.build_eth().build_axis_fcs().data)
rx_frame = None
while rx_frame is None:
yield clk.posedge
rx_frame = gmii_sink.recv()
check_eth_frame = eth_ep.EthFrame()
check_eth_frame.parse_axis_fcs(rx_frame.data[8:])
check_frame = udp_ep.UDPFrame()
check_frame.parse_eth(check_eth_frame)
print(check_frame)
assert check_frame.eth_dest_mac == 0xDAD1D2D3D4D5
assert check_frame.eth_src_mac == 0x020000000000
assert check_frame.eth_type == 0x0800
assert check_frame.ip_version == 4
assert check_frame.ip_ihl == 5
assert check_frame.ip_dscp == 0
assert check_frame.ip_ecn == 0
assert check_frame.ip_identification == 0
assert check_frame.ip_flags == 2
assert check_frame.ip_fragment_offset == 0
assert check_frame.ip_ttl == 64
assert check_frame.ip_protocol == 0x11
assert check_frame.ip_source_ip == 0xc0a80180
assert check_frame.ip_dest_ip == 0xc0a80181
assert check_frame.udp_source_port == 14000
assert check_frame.udp_dest_port == 1234
rx_pkt = xfcp.XFCPFrame()
rx_pkt.parse_axis(check_frame.payload.data)
print(rx_pkt)
assert rx_pkt.ptype == 0xff
assert rx_pkt.path == []
assert rx_pkt.rpath == []
assert len(rx_pkt.payload.data) == 64
pkt = xfcp.XFCPFrame()
pkt.path = [0]
pkt.rpath = []
pkt.ptype = 0xfe
pkt.payload = b''
test_frame = udp_ep.UDPFrame()
test_frame.eth_dest_mac = 0x020000000000
test_frame.eth_src_mac = 0xDAD1D2D3D4D5
test_frame.eth_type = 0x0800
test_frame.ip_version = 4
test_frame.ip_ihl = 5
test_frame.ip_dscp = 0
test_frame.ip_ecn = 0
test_frame.ip_length = None
test_frame.ip_identification = 0
test_frame.ip_flags = 2
test_frame.ip_fragment_offset = 0
test_frame.ip_ttl = 64
test_frame.ip_protocol = 0x11
test_frame.ip_header_checksum = None
test_frame.ip_source_ip = 0xc0a80181
test_frame.ip_dest_ip = 0xc0a80180
test_frame.udp_source_port = 1234
test_frame.udp_dest_port = 14000
test_frame.payload = pkt.build_axis()
test_frame.build()
gmii_source.send(b'\x55\x55\x55\x55\x55\x55\x55\xD5' +
test_frame.build_eth().build_axis_fcs().data)
rx_frame = None
while rx_frame is None:
yield clk.posedge
rx_frame = gmii_sink.recv()
check_eth_frame = eth_ep.EthFrame()
check_eth_frame.parse_axis_fcs(rx_frame.data[8:])
check_frame = udp_ep.UDPFrame()
check_frame.parse_eth(check_eth_frame)
print(check_frame)
assert check_frame.eth_dest_mac == 0xDAD1D2D3D4D5
assert check_frame.eth_src_mac == 0x020000000000
assert check_frame.eth_type == 0x0800
assert check_frame.ip_version == 4
assert check_frame.ip_ihl == 5
assert check_frame.ip_dscp == 0
assert check_frame.ip_ecn == 0
assert check_frame.ip_identification == 0
assert check_frame.ip_flags == 2
assert check_frame.ip_fragment_offset == 0
assert check_frame.ip_ttl == 64
assert check_frame.ip_protocol == 0x11
assert check_frame.ip_source_ip == 0xc0a80180
assert check_frame.ip_dest_ip == 0xc0a80181
assert check_frame.udp_source_port == 14000
assert check_frame.udp_dest_port == 1234
rx_pkt = xfcp.XFCPFrame()
rx_pkt.parse_axis(check_frame.payload.data)
print(rx_pkt)
assert rx_pkt.ptype == 0xff
assert rx_pkt.path == [0]
assert rx_pkt.rpath == []
assert len(rx_pkt.payload.data) == 32
assert gmii_source.empty()
assert gmii_sink.empty()
yield delay(100)
yield clk.posedge
print("test 2: enumerate MGT via UDP")
current_test.next = 2
pkt = xfcp.XFCPFrame()
pkt.path = [3]
pkt.rpath = []
pkt.ptype = 0xfe
pkt.payload = b''
test_frame = udp_ep.UDPFrame()
test_frame.eth_dest_mac = 0x020000000000
test_frame.eth_src_mac = 0xDAD1D2D3D4D5
test_frame.eth_type = 0x0800
test_frame.ip_version = 4
test_frame.ip_ihl = 5
test_frame.ip_dscp = 0
test_frame.ip_ecn = 0
test_frame.ip_length = None
test_frame.ip_identification = 0
test_frame.ip_flags = 2
test_frame.ip_fragment_offset = 0
test_frame.ip_ttl = 64
test_frame.ip_protocol = 0x11
test_frame.ip_header_checksum = None
test_frame.ip_source_ip = 0xc0a80181
test_frame.ip_dest_ip = 0xc0a80180
test_frame.udp_source_port = 1234
test_frame.udp_dest_port = 14000
test_frame.payload = pkt.build_axis()
test_frame.build()
gmii_source.send(b'\x55\x55\x55\x55\x55\x55\x55\xD5' +
test_frame.build_eth().build_axis_fcs().data)
# wait for XFCP packet at MGT port
rx_pkt = None
while rx_pkt is None:
yield clk.posedge
rx_pkt = xfcp_mgt_port.recv()
print(rx_pkt)
assert rx_pkt.ptype == 0xfe
assert rx_pkt.path == []
assert rx_pkt.rpath == [1]
assert len(rx_pkt.payload.data) == 0
pkt2 = xfcp.XFCPFrame(rx_pkt)
pkt2.ptype = 0xff
pkt2.payload = b'MGT ID DATA'
xfcp_mgt_port.send(pkt2)
rx_frame = None
while rx_frame is None:
yield clk.posedge
rx_frame = gmii_sink.recv()
check_eth_frame = eth_ep.EthFrame()
check_eth_frame.parse_axis_fcs(rx_frame.data[8:])
check_frame = udp_ep.UDPFrame()
check_frame.parse_eth(check_eth_frame)
print(check_frame)
assert check_frame.eth_dest_mac == 0xDAD1D2D3D4D5
assert check_frame.eth_src_mac == 0x020000000000
assert check_frame.eth_type == 0x0800
assert check_frame.ip_version == 4
assert check_frame.ip_ihl == 5
assert check_frame.ip_dscp == 0
assert check_frame.ip_ecn == 0
assert check_frame.ip_identification == 0
assert check_frame.ip_flags == 2
assert check_frame.ip_fragment_offset == 0
assert check_frame.ip_ttl == 64
assert check_frame.ip_protocol == 0x11
assert check_frame.ip_source_ip == 0xc0a80180
assert check_frame.ip_dest_ip == 0xc0a80181
assert check_frame.udp_source_port == 14000
assert check_frame.udp_dest_port == 1234
rx_pkt = xfcp.XFCPFrame()
rx_pkt.parse_axis(check_frame.payload.data)
print(rx_pkt)
assert rx_pkt.ptype == 0xff
assert rx_pkt.path == [3]
assert rx_pkt.rpath == []
assert rx_pkt.payload == pkt2.payload
assert gmii_source.empty()
assert gmii_sink.empty()
yield delay(100)
yield clk.posedge
print("test 3: test write and read RAM 0")
current_test.next = 3
pkt1 = xfcp.XFCPFrame()
pkt1.path = [0]
pkt1.ptype = 0x12
pkt1.payload = bytearray(
struct.pack('<BH', 0, 4) + b'\x11\x22\x33\x44')
pkt2 = xfcp.XFCPFrame()
pkt2.path = [0]
pkt2.ptype = 0x10
pkt2.payload = bytearray(struct.pack('<BH', 0, 4))
test_frame1 = udp_ep.UDPFrame()
test_frame1.eth_dest_mac = 0x020000000000
test_frame1.eth_src_mac = 0xDAD1D2D3D4D5
test_frame1.eth_type = 0x0800
test_frame1.ip_version = 4
test_frame1.ip_ihl = 5
test_frame1.ip_dscp = 0
test_frame1.ip_ecn = 0
test_frame1.ip_length = None
test_frame1.ip_identification = 0
test_frame1.ip_flags = 2
test_frame1.ip_fragment_offset = 0
test_frame1.ip_ttl = 64
test_frame1.ip_protocol = 0x11
test_frame1.ip_header_checksum = None
test_frame1.ip_source_ip = 0xc0a80181
test_frame1.ip_dest_ip = 0xc0a80180
test_frame1.udp_source_port = 1234
test_frame1.udp_dest_port = 14000
test_frame1.payload = pkt1.build_axis()
test_frame1.build()
test_frame2 = udp_ep.UDPFrame(test_frame1)
test_frame2.payload = pkt2.build_axis()
test_frame2.build()
gmii_source.send(b'\x55\x55\x55\x55\x55\x55\x55\xD5' +
test_frame1.build_eth().build_axis_fcs().data)
gmii_source.send(b'\x55\x55\x55\x55\x55\x55\x55\xD5' +
test_frame2.build_eth().build_axis_fcs().data)
rx_frame = None
while rx_frame is None:
yield clk.posedge
rx_frame = gmii_sink.recv()
check_eth_frame = eth_ep.EthFrame()
check_eth_frame.parse_axis_fcs(rx_frame.data[8:])
check_frame = udp_ep.UDPFrame()
check_frame.parse_eth(check_eth_frame)
print(check_frame)
rx_pkt = xfcp.XFCPFrame()
rx_pkt.parse_axis(check_frame.payload.data)
print(rx_pkt)
assert rx_pkt.ptype == 0x13
assert rx_pkt.payload.data == struct.pack('<BH', 0, 4)
rx_frame = None
while rx_frame is None:
yield clk.posedge
rx_frame = gmii_sink.recv()
check_eth_frame = eth_ep.EthFrame()
check_eth_frame.parse_axis_fcs(rx_frame.data[8:])
check_frame = udp_ep.UDPFrame()
check_frame.parse_eth(check_eth_frame)
print(check_frame)
rx_pkt = xfcp.XFCPFrame()
rx_pkt.parse_axis(check_frame.payload.data)
print(rx_pkt)
assert rx_pkt.ptype == 0x11
assert rx_pkt.payload.data == struct.pack('<BH', 0,
4) + b'\x11\x22\x33\x44'
assert gmii_source.empty()
assert gmii_sink.empty()
yield delay(100)
yield clk.posedge
print("test 3: enumerate via UART")
current_test.next = 3
pkt = xfcp.XFCPFrame()
pkt.path = []
pkt.rpath = []
pkt.ptype = 0xfe
pkt.payload = b''
uart_source.write(pkt.build_axis_cobs().data + b'\x00')
yield clk.posedge
rx_data = b''
while True:
if not uart_sink.empty():
b = bytearray(uart_sink.read(1))
rx_data += b
if b[0] == 0:
break
yield clk.posedge
rx_pkt = xfcp.XFCPFrame()
rx_pkt.parse_axis_cobs(rx_data[:-1])
print(rx_pkt)
assert rx_pkt.ptype == 0xff
assert rx_pkt.path == []
assert rx_pkt.rpath == []
assert len(rx_pkt.payload.data) == 64
pkt = xfcp.XFCPFrame()
pkt.path = [0]
pkt.rpath = []
pkt.ptype = 0xfe
pkt.payload = b''
uart_source.write(pkt.build_axis_cobs().data + b'\x00')
yield clk.posedge
rx_data = b''
while True:
if not uart_sink.empty():
b = bytearray(uart_sink.read(1))
rx_data += b
if b[0] == 0:
break
yield clk.posedge
rx_pkt = xfcp.XFCPFrame()
rx_pkt.parse_axis_cobs(rx_data[:-1])
print(rx_pkt)
assert rx_pkt.ptype == 0xff
assert rx_pkt.path == [0]
assert rx_pkt.rpath == []
assert len(rx_pkt.payload.data) == 32
yield delay(100)
raise StopSimulation
return instances()
def bench():
# Parameters
XFCP_ID_TYPE = 0x2C00
XFCP_ID_STR = "I2C Master"
XFCP_EXT_ID = 0
XFCP_EXT_ID_STR = ""
DEFAULT_PRESCALE = 1
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
up_xfcp_in_tdata = Signal(intbv(0)[8:])
up_xfcp_in_tvalid = Signal(bool(0))
up_xfcp_in_tlast = Signal(bool(0))
up_xfcp_in_tuser = Signal(bool(0))
up_xfcp_out_tready = Signal(bool(0))
i2c_scl_i = Signal(bool(1))
i2c_sda_i = Signal(bool(1))
s1_scl_i = Signal(bool(1))
s1_sda_i = Signal(bool(1))
s2_scl_i = Signal(bool(1))
s2_sda_i = Signal(bool(1))
# Outputs
up_xfcp_in_tready = Signal(bool(0))
up_xfcp_out_tdata = Signal(intbv(0)[8:])
up_xfcp_out_tvalid = Signal(bool(0))
up_xfcp_out_tlast = Signal(bool(0))
up_xfcp_out_tuser = Signal(bool(0))
i2c_scl_o = Signal(bool(1))
i2c_scl_t = Signal(bool(1))
i2c_sda_o = Signal(bool(1))
i2c_sda_t = Signal(bool(1))
s1_scl_o = Signal(bool(1))
s1_scl_t = Signal(bool(1))
s1_sda_o = Signal(bool(1))
s1_sda_t = Signal(bool(1))
s2_scl_o = Signal(bool(1))
s2_scl_t = Signal(bool(1))
s2_sda_o = Signal(bool(1))
s2_sda_t = Signal(bool(1))
# XFCP ports
up_xfcp_port_out_pause = Signal(bool(0))
up_xfcp_port_in_pause = Signal(bool(0))
up_xfcp_port = xfcp.XFCPPort()
up_xfcp_port_logic = up_xfcp_port.create_logic(
clk=clk,
rst=rst,
xfcp_in_tdata=up_xfcp_out_tdata,
xfcp_in_tvalid=up_xfcp_out_tvalid,
xfcp_in_tready=up_xfcp_out_tready,
xfcp_in_tlast=up_xfcp_out_tlast,
xfcp_in_tuser=up_xfcp_out_tuser,
xfcp_out_tdata=up_xfcp_in_tdata,
xfcp_out_tvalid=up_xfcp_in_tvalid,
xfcp_out_tready=up_xfcp_in_tready,
xfcp_out_tlast=up_xfcp_in_tlast,
xfcp_out_tuser=up_xfcp_in_tuser,
pause_source=up_xfcp_port_in_pause,
pause_sink=up_xfcp_port_out_pause,
name='up_xfcp_port')
# I2C memory model 1
i2c_mem1 = i2c.I2CMem(1024)
i2c_mem_logic1 = i2c_mem1.create_logic(scl_i=s1_scl_i,
scl_o=s1_scl_o,
scl_t=s1_scl_t,
sda_i=s1_sda_i,
sda_o=s1_sda_o,
sda_t=s1_sda_t,
abw=2,
address=0x50,
latency=0,
name='slave1')
# I2C memory model 2
i2c_mem2 = i2c.I2CMem(1024)
i2c_mem_logic2 = i2c_mem2.create_logic(scl_i=s2_scl_i,
scl_o=s2_scl_o,
scl_t=s2_scl_t,
sda_i=s2_sda_i,
sda_o=s2_sda_o,
sda_t=s2_sda_t,
abw=2,
address=0x51,
latency=1000,
name='slave2')
# DUT
if os.system(build_cmd):
raise Exception("Error running build command")
dut = Cosimulation("vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
up_xfcp_in_tdata=up_xfcp_in_tdata,
up_xfcp_in_tvalid=up_xfcp_in_tvalid,
up_xfcp_in_tready=up_xfcp_in_tready,
up_xfcp_in_tlast=up_xfcp_in_tlast,
up_xfcp_in_tuser=up_xfcp_in_tuser,
up_xfcp_out_tdata=up_xfcp_out_tdata,
up_xfcp_out_tvalid=up_xfcp_out_tvalid,
up_xfcp_out_tready=up_xfcp_out_tready,
up_xfcp_out_tlast=up_xfcp_out_tlast,
up_xfcp_out_tuser=up_xfcp_out_tuser,
i2c_scl_i=i2c_scl_i,
i2c_scl_o=i2c_scl_o,
i2c_scl_t=i2c_scl_t,
i2c_sda_i=i2c_sda_i,
i2c_sda_o=i2c_sda_o,
i2c_sda_t=i2c_sda_t)
@always_comb
def bus():
# emulate I2C wired AND
i2c_scl_i.next = i2c_scl_o & s1_scl_o & s2_scl_o
i2c_sda_i.next = i2c_sda_o & s1_sda_o & s2_sda_o
s1_scl_i.next = i2c_scl_o & s1_scl_o & s2_scl_o
s1_sda_i.next = i2c_sda_o & s1_sda_o & s2_sda_o
s2_scl_i.next = i2c_scl_o & s1_scl_o & s2_scl_o
s2_sda_i.next = i2c_sda_o & s1_sda_o & s2_sda_o
@always(delay(4))
def clkgen():
clk.next = not clk
def wait_normal():
i = 8
while i > 0:
i = max(0, i - 1)
if not up_xfcp_port.idle() or not i2c_scl_i or not i2c_sda_i:
i = 8
yield clk.posedge
def wait_pause_source():
i = 4
while i > 0:
i = max(0, i - 1)
if not up_xfcp_port.idle() or not i2c_scl_i or not i2c_sda_i:
i = 4
up_xfcp_port_in_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
up_xfcp_port_in_pause.next = False
yield clk.posedge
def wait_pause_sink():
i = 4
while i > 0:
i = max(0, i - 1)
if not up_xfcp_port.idle() or not i2c_scl_i or not i2c_sda_i:
i = 4
up_xfcp_port_out_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
up_xfcp_port_out_pause.next = False
yield clk.posedge
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
# testbench stimulus
yield clk.posedge
print("test 1: write")
current_test.next = 1
pkt = xfcp.XFCPFrame()
pkt.ptype = 0x2C
pkt.payload = b'\xD0\x1C\x06\x00\x04\x11\x22\x33\x44'
for wait in wait_normal, wait_pause_source, wait_pause_sink:
up_xfcp_port.send(pkt)
yield clk.posedge
yield wait()
yield clk.posedge
data = i2c_mem1.read_mem(0, 32)
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c) for c in bytearray(data[i:i + 16]))))
assert i2c_mem1.read_mem(4, 4) == b'\x11\x22\x33\x44'
rx_pkt = up_xfcp_port.recv()
print(rx_pkt)
assert rx_pkt.ptype == 0x2D
assert rx_pkt.payload.data == b'\xD0\x1C\x06\x00\x04\x11\x22\x33\x44'
yield delay(100)
yield clk.posedge
print("test 2: read")
current_test.next = 2
pkt = xfcp.XFCPFrame()
pkt.ptype = 0x2C
pkt.payload = b'\xD0\x14\x02\x00\x04\x1A\x04'
for wait in wait_normal, wait_pause_source, wait_pause_sink:
up_xfcp_port.send(pkt)
yield clk.posedge
yield wait()
yield clk.posedge
rx_pkt = up_xfcp_port.recv()
print(rx_pkt)
assert rx_pkt.ptype == 0x2D
assert rx_pkt.payload.data == b'\xD0\x14\x02\x00\x04\x1A\x04\x11\x22\x33\x44'
yield delay(100)
yield clk.posedge
print("test 3: write to slave 2")
current_test.next = 3
pkt = xfcp.XFCPFrame()
pkt.ptype = 0x2C
pkt.payload = b'\xD1\x04\x00\x04\x04\x04\x44\x04\x33\x04\x22\x0C\x11'
for wait in wait_normal, wait_pause_source, wait_pause_sink:
up_xfcp_port.send(pkt)
yield clk.posedge
yield wait()
yield clk.posedge
data = i2c_mem2.read_mem(0, 32)
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c) for c in bytearray(data[i:i + 16]))))
assert i2c_mem2.read_mem(4, 4) == b'\x44\x33\x22\x11'
rx_pkt = up_xfcp_port.recv()
print(rx_pkt)
assert rx_pkt.ptype == 0x2D
assert rx_pkt.payload.data == b'\xD1\x04\x00\x04\x04\x04\x44\x04\x33\x04\x22\x0C\x11'
yield delay(100)
yield clk.posedge
print("test 4: read from slave 2")
current_test.next = 4
pkt = xfcp.XFCPFrame()
pkt.ptype = 0x2C
pkt.payload = b'\xD1\x04\x00\x04\x04\x02\x02\x02\x0A'
for wait in wait_normal, wait_pause_source, wait_pause_sink:
up_xfcp_port.send(pkt)
yield clk.posedge
yield wait()
yield clk.posedge
rx_pkt = up_xfcp_port.recv()
print(rx_pkt)
assert rx_pkt.ptype == 0x2D
assert rx_pkt.payload.data == b'\xD1\x04\x00\x04\x04\x02\x44\x02\x33\x02\x22\x0A\x11'
yield delay(100)
yield clk.posedge
print("test 5: test configuration and status")
current_test.next = 5
pkt = xfcp.XFCPFrame()
pkt.ptype = 0x2C
pkt.payload = b'\x60\x04\x00\x60\x01\x00\x40'
for wait in wait_normal, wait_pause_source, wait_pause_sink:
up_xfcp_port.send(pkt)
yield clk.posedge
yield wait()
yield clk.posedge
rx_pkt = up_xfcp_port.recv()
print(rx_pkt)
assert rx_pkt.ptype == 0x2D
assert rx_pkt.payload.data == b'\x60\x04\x00\x60\x01\x00\x40\x00'
yield delay(100)
yield clk.posedge
print("test 6: test id")
current_test.next = 6
pkt = xfcp.XFCPFrame()
pkt.ptype = 0xFE
pkt.payload = b''
for wait in wait_normal, wait_pause_source, wait_pause_sink:
up_xfcp_port.send(pkt)
yield clk.posedge
yield wait()
yield clk.posedge
rx_pkt = up_xfcp_port.recv()
print(rx_pkt)
assert rx_pkt.ptype == 0xff
assert len(rx_pkt.payload.data) == 32
yield delay(100)
yield clk.posedge
print("test 7: test id with trailing bytes")
current_test.next = 7
pkt1 = xfcp.XFCPFrame()
pkt1.ptype = 0xFE
pkt1.payload = b'\0' * 256
pkt2 = xfcp.XFCPFrame()
pkt2.ptype = 0xFE
pkt2.payload = b'\0' * 8
for wait in wait_normal, wait_pause_source, wait_pause_sink:
up_xfcp_port.send(pkt1)
up_xfcp_port.send(pkt2)
yield clk.posedge
yield wait()
yield clk.posedge
rx_pkt = up_xfcp_port.recv()
print(rx_pkt)
assert rx_pkt.ptype == 0xff
assert len(rx_pkt.payload.data) == 32
rx_pkt = up_xfcp_port.recv()
print(rx_pkt)
assert rx_pkt.ptype == 0xff
assert len(rx_pkt.payload.data) == 32
yield delay(100)
yield clk.posedge
print("test 8: test with rpath")
current_test.next = 8
pkt1 = xfcp.XFCPFrame()
pkt1.rpath = [1, 2, 3]
pkt1.ptype = 0xFE
pkt1.payload = b'\0' * 8
pkt2 = xfcp.XFCPFrame()
pkt2.rpath = [4, 5, 6]
pkt2.ptype = 0x2C
pkt2.payload = b'\xD0\x04\x00\x04\x04\x02\x02\x02\x0A'
for wait in wait_normal, wait_pause_source, wait_pause_sink:
up_xfcp_port.send(pkt1)
up_xfcp_port.send(pkt2)
yield clk.posedge
yield wait()
yield clk.posedge
rx_pkt = up_xfcp_port.recv()
print(rx_pkt)
assert rx_pkt.rpath == [1, 2, 3]
assert rx_pkt.ptype == 0xff
assert len(rx_pkt.payload.data) == 32
rx_pkt = up_xfcp_port.recv()
print(rx_pkt)
assert rx_pkt.rpath == [4, 5, 6]
assert rx_pkt.ptype == 0x2D
assert rx_pkt.payload.data == b'\xD0\x04\x00\x04\x04\x02\x11\x02\x22\x02\x33\x0A\x44'
yield delay(100)
yield clk.posedge
print("test 9: test invalid packets")
current_test.next = 9
pkt1 = xfcp.XFCPFrame()
pkt1.ptype = 0x99
pkt1.payload = b'\x00' * 8
pkt2 = xfcp.XFCPFrame()
pkt2.path = [0]
pkt2.ptype = 0xFE
pkt2.payload = b''
for wait in wait_normal, wait_pause_source, wait_pause_sink:
up_xfcp_port.send(pkt1)
up_xfcp_port.send(pkt2)
yield clk.posedge
yield wait()
yield clk.posedge
rx_pkt = up_xfcp_port.recv()
assert rx_pkt is None
yield delay(100)
raise StopSimulation
return instances()
