def check(): yield delay(100) yield clk.posedge rst.next = 1 tx_rst.next = 1 rx_rst.next = 1 yield clk.posedge rst.next = 0 tx_rst.next = 0 rx_rst.next = 0 yield clk.posedge yield delay(100) yield clk.posedge # testbench stimulus yield clk.posedge print("test 1: test RX packet") current_test.next = 1 test_frame = bytearray(range(128)) xgmii_frame = xgmii_ep.XGMIIFrame(b'\x55\x55\x55\x55\x55\x55\x55\xD5' + test_frame) xgmii_source.send(xgmii_frame) yield serdes_sink.wait() rx_frame = serdes_sink.recv() assert rx_frame.data == xgmii_frame.data assert xgmii_sink.empty() assert serdes_sink.empty() yield delay(100) yield clk.posedge print("test 2: test TX packet") current_test.next = 2 test_frame = bytearray(range(128)) xgmii_frame = xgmii_ep.XGMIIFrame(b'\x55\x55\x55\x55\x55\x55\x55\xD5' + test_frame) serdes_source.send(xgmii_frame) yield xgmii_sink.wait() rx_frame = xgmii_sink.recv() assert rx_frame.data == xgmii_frame.data assert xgmii_sink.empty() assert serdes_sink.empty() yield delay(100) raise StopSimulation
def check(): yield delay(100) yield clk.posedge rst.next = 1 yield clk.posedge rst.next = 0 yield clk.posedge yield delay(100) yield clk.posedge # testbench stimulus test_frame = eth_ep.EthFrame() test_frame.eth_dest_mac = 0xDAD1D2D3D4D5 test_frame.eth_src_mac = 0x5A5152535455 test_frame.eth_type = 0x8000 test_frame.payload = bytearray(range(46)) test_frame.update_fcs() axis_frame = test_frame.build_axis_fcs() xgmii_frame = xgmii_ep.XGMIIFrame(b'\x55\x55\x55\x55\x55\x55\x55\xD5' + bytearray(axis_frame)) eth_l0_source.send(xgmii_frame) while eth_l0_sink.empty(): yield clk.posedge check_frame = eth_l0_sink.recv() assert check_frame == xgmii_frame test_frame = eth_ep.EthFrame() test_frame.eth_dest_mac = 0xDAD1D2D3D4D5 test_frame.eth_src_mac = 0x5A5152535455 test_frame.eth_type = 0x8099 test_frame.payload = bytearray(range(15, -1, -1)) + bytearray( [0] * (46 - 16)) test_frame.update_fcs() axis_frame = test_frame.build_axis_fcs() xgmii_frame = xgmii_ep.XGMIIFrame(b'\x55\x55\x55\x55\x55\x55\x55\xD5' + bytearray(axis_frame)) eth_l11_source.send(xgmii_frame) yield delay(400) test_frame = eth_ep.EthFrame() test_frame.eth_dest_mac = 0xDAD1D2D3D4D5 test_frame.eth_src_mac = 0x5A5152535455 test_frame.eth_type = 0x8000 test_frame.payload = bytearray(range(46)) test_frame.update_fcs() axis_frame = test_frame.build_axis_fcs() xgmii_frame = xgmii_ep.XGMIIFrame(b'\x55\x55\x55\x55\x55\x55\x55\xD5' + bytearray(axis_frame)) eth_l0_source.send(xgmii_frame) while eth_r7_sink.empty(): yield clk.posedge check_frame = eth_r7_sink.recv() assert check_frame == xgmii_frame yield delay(100) raise StopSimulation
def check(): yield delay(100) yield clk.posedge rst.next = 1 yield clk.posedge rst.next = 0 yield clk.posedge yield delay(100) yield clk.posedge # testbench stimulus for payload_len in list(range(16,34)): yield clk.posedge print("test 1: test packet, length %d" % payload_len) current_test.next = 1 test_frame = bytearray(range(payload_len)) xgmii_frame = xgmii_ep.XGMIIFrame(b'\x55\x55\x55\x55\x55\x55\x55\xD5'+test_frame) source.send(xgmii_frame) yield sink.wait() rx_frame = sink.recv() assert rx_frame.data == xgmii_frame.data assert sink.empty() yield delay(100) yield clk.posedge print("test 2: back-to-back packets, length %d" % payload_len) current_test.next = 2 test_frame1 = bytearray(range(payload_len)) test_frame2 = bytearray(range(payload_len)) xgmii_frame1 = xgmii_ep.XGMIIFrame(b'\x55\x55\x55\x55\x55\x55\x55\xD5'+test_frame1) xgmii_frame2 = xgmii_ep.XGMIIFrame(b'\x55\x55\x55\x55\x55\x55\x55\xD5'+test_frame2) source.send(xgmii_frame1) source.send(xgmii_frame2) yield sink.wait() rx_frame = sink.recv() assert rx_frame.data == xgmii_frame1.data yield sink.wait() rx_frame = sink.recv() assert rx_frame.data == xgmii_frame2.data assert sink.empty() yield delay(100) yield clk.posedge print("test 3: errored frame, length %d" % payload_len) current_test.next = 3 test_frame1 = bytearray(range(payload_len)) test_frame2 = bytearray(range(payload_len)) xgmii_frame1 = xgmii_ep.XGMIIFrame(b'\x55\x55\x55\x55\x55\x55\x55\xD5'+test_frame1) xgmii_frame2 = xgmii_ep.XGMIIFrame(b'\x55\x55\x55\x55\x55\x55\x55\xD5'+test_frame2) xgmii_frame1.error = 1 source.send(xgmii_frame1) source.send(xgmii_frame2) yield sink.wait() rx_frame = sink.recv() #assert rx_frame.data == xgmii_frame1.data yield sink.wait() rx_frame = sink.recv() assert rx_frame.data == xgmii_frame2.data assert sink.empty() yield delay(100) yield clk.posedge print("test 4: test frame sync") current_test.next = 4 assert rx_block_lock load_bit_offset.append(33) yield delay(600) assert not rx_block_lock assert rx_high_ber yield delay(3000) assert rx_block_lock yield delay(2000) assert not rx_high_ber yield delay(100) raise StopSimulation
def logic(): frame = None d = [] c = [] scrambler_state = 0 while True: yield clk.posedge if enable: data = int(rx_data) header = int(rx_header) if reverse: # bit reverse data = sum(1 << (63 - i) for i in range(64) if (data >> i) & 1) header = sum(1 << (1 - i) for i in range(2) if (header >> i) & 1) if scramble: # 64b66b descrambler b = 0 for i in range(len(rx_data)): if bool(scrambler_state & (1 << 38)) ^ bool( scrambler_state & (1 << 57)) ^ bool(data & (1 << i)): b = b | (1 << i) scrambler_state = (scrambler_state & 0x1ffffffffffffff ) << 1 | bool(data & (1 << i)) data = b # 10GBASE-R decoding # remap control characters ctrl = [0] * 8 for i in range(8): if (data >> i * 7 + 8) & 0x7f == CTRL_IDLE: # idle ctrl[i] = XGMII_IDLE elif (data >> i * 7 + 8) & 0x7f == CTRL_LPI: # LPI ctrl[i] = XGMII_LPI elif (data >> i * 7 + 8) & 0x7f == CTRL_ERROR: # error ctrl[i] = XGMII_ERROR elif (data >> i * 7 + 8) & 0x7f == CTRL_RES_0: # reserved0 ctrl[i] = XGMII_RES_0 elif (data >> i * 7 + 8) & 0x7f == CTRL_RES_1: # reserved1 ctrl[i] = XGMII_RES_1 elif (data >> i * 7 + 8) & 0x7f == CTRL_RES_2: # reserved2 ctrl[i] = XGMII_RES_2 elif (data >> i * 7 + 8) & 0x7f == CTRL_RES_3: # reserved3 ctrl[i] = XGMII_RES_3 elif (data >> i * 7 + 8) & 0x7f == CTRL_RES_4: # reserved4 ctrl[i] = XGMII_RES_4 elif (data >> i * 7 + 8) & 0x7f == CTRL_RES_5: # reserved5 ctrl[i] = XGMII_RES_5 else: # invalid ctrl[i] = XGMII_ERROR dl = [] cl = [] if header == SYNC_DATA: # data for k in range(8): dl.append((data >> k * 8) & 0xff) cl.append(0) elif header == SYNC_CTRL: if data & 0xff == BLOCK_TYPE_CTRL: # C7 C6 C5 C4 C3 C2 C1 C0 BT dl = ctrl cl = [1] * 8 elif data & 0xff == BLOCK_TYPE_OS_4: # D7 D6 D5 O4 C3 C2 C1 C0 BT dl = ctrl[0:4] cl = [1] * 4 if (data >> 36) & 0xf == O_SEQ_OS: dl.append(XGMII_SEQ_OS) elif (data >> 36) & 0xf == O_SIG_OS: dl.append(XGMII_SIG_OS) else: dl.append(XGMII_ERROR) cl.append(1) for k in range(4, 7): dl.append((data >> (k + 1) * 8) & 0xff) cl.append(0) elif data & 0xff == BLOCK_TYPE_START_4: # D7 D6 D5 C3 C2 C1 C0 BT dl = ctrl[0:4] cl = [1] * 4 dl.append(XGMII_START) cl.append(1) for k in range(4, 7): dl.append((data >> (k + 1) * 8) & 0xff) cl.append(0) elif data & 0xff == BLOCK_TYPE_OS_START: # D7 D6 D5 O0 D3 D2 D1 BT if (data >> 32) & 0xf == O_SEQ_OS: dl.append(XGMII_SEQ_OS) elif (data >> 32) & 0xf == O_SIG_OS: dl.append(XGMII_SIG_OS) else: dl.append(XGMII_ERROR) cl.append(1) for k in range(0, 3): dl.append((data >> (k + 1) * 8) & 0xff) cl.append(0) dl.append(XGMII_START) cl.append(1) for k in range(4, 7): dl.append((data >> (k + 1) * 8) & 0xff) cl.append(0) elif data & 0xff == BLOCK_TYPE_OS_04: # D7 D6 D5 O4 O0 D3 D2 D1 BT if (data >> 32) & 0xf == O_SEQ_OS: dl.append(XGMII_SEQ_OS) elif (data >> 32) & 0xf == O_SIG_OS: dl.append(XGMII_SIG_OS) else: dl.append(XGMII_ERROR) cl.append(1) for k in range(0, 3): dl.append((data >> (k + 1) * 8) & 0xff) cl.append(0) if (data >> 36) & 0xf == O_SEQ_OS: dl.append(XGMII_SEQ_OS) elif (data >> 36) & 0xf == O_SIG_OS: dl.append(XGMII_SIG_OS) else: dl.append(XGMII_ERROR) cl.append(1) for k in range(4, 7): dl.append((data >> (k + 1) * 8) & 0xff) cl.append(0) elif data & 0xff == BLOCK_TYPE_START_0: # D7 D6 D5 D4 D3 D2 D1 BT dl.append(XGMII_START) cl.append(1) for k in range(7): dl.append((data >> (k + 1) * 8) & 0xff) cl.append(0) elif data & 0xff == BLOCK_TYPE_OS_0: # C7 C6 C5 C4 O0 D3 D2 D1 BT if (data >> 32) & 0xf == O_SEQ_OS: dl.append(XGMII_SEQ_OS) elif (data >> 32) & 0xf == O_SIG_OS: dl.append(XGMII_SEQ_OS) else: dl.append(XGMII_ERROR) cl.append(1) for k in range(0, 3): dl.append((data >> (k + 1) * 8) & 0xff) cl.append(0) dl.extend(ctrl[4:8]) cl.extend([1] * 4) elif data & 0xff == BLOCK_TYPE_TERM_0: # C7 C6 C5 C4 C3 C2 C1 BT dl.append(XGMII_TERM) cl.append(1) dl.extend(ctrl[1:]) cl.extend([1] * 7) elif data & 0xff == BLOCK_TYPE_TERM_1: # C7 C6 C5 C4 C3 C2 D0 BT dl.append((data >> 8) & 0xff) cl.append(0) dl.append(XGMII_TERM) cl.append(1) dl.extend(ctrl[2:]) cl.extend([1] * 6) elif data & 0xff == BLOCK_TYPE_TERM_2: # C7 C6 C5 C4 C3 D1 D0 BT for k in range(2): dl.append((data >> (k + 1) * 8) & 0xff) cl.append(0) dl.append(XGMII_TERM) cl.append(1) dl.extend(ctrl[3:]) cl.extend([1] * 5) elif data & 0xff == BLOCK_TYPE_TERM_3: # C7 C6 C5 C4 D2 D1 D0 BT for k in range(3): dl.append((data >> (k + 1) * 8) & 0xff) cl.append(0) dl.append(XGMII_TERM) cl.append(1) dl.extend(ctrl[4:]) cl.extend([1] * 4) elif data & 0xff == BLOCK_TYPE_TERM_4: # C7 C6 C5 D3 D2 D1 D0 BT for k in range(4): dl.append((data >> (k + 1) * 8) & 0xff) cl.append(0) dl.append(XGMII_TERM) cl.append(1) dl.extend(ctrl[5:]) cl.extend([1] * 3) elif data & 0xff == BLOCK_TYPE_TERM_5: # C7 C6 D4 D3 D2 D1 D0 BT for k in range(5): dl.append((data >> (k + 1) * 8) & 0xff) cl.append(0) dl.append(XGMII_TERM) cl.append(1) dl.extend(ctrl[6:]) cl.extend([1] * 2) elif data & 0xff == BLOCK_TYPE_TERM_6: # C7 D5 D4 D3 D2 D1 D0 BT for k in range(6): dl.append((data >> (k + 1) * 8) & 0xff) cl.append(0) dl.append(XGMII_TERM) cl.append(1) dl.extend(ctrl[7:]) cl.extend([1] * 1) elif data & 0xff == BLOCK_TYPE_TERM_7: # D6 D5 D4 D3 D2 D1 D0 BT for k in range(7): dl.append((data >> (k + 1) * 8) & 0xff) cl.append(0) dl.append(XGMII_TERM) cl.append(1) else: # invalid block type dl = [XGMII_ERROR] * 8 cl = [1] * 8 else: # invalid sync header dl = [XGMII_ERROR] * 8 cl = [1] * 8 if frame is None: if cl[0] and dl[0] == XGMII_START: # start in lane 0 frame = xgmii_ep.XGMIIFrame() d = [ETH_PRE] c = [0] for i in range(1, bw): d.append(dl[i]) c.append(cl[i]) elif bw == 8 and cl[4] and dl[4] == XGMII_START: # start in lane 4 frame = xgmii_ep.XGMIIFrame() d = [ETH_PRE] c = [0] for i in range(5, bw): d.append(dl[i]) c.append(cl[i]) else: for i in range(bw): if cl[i]: # got a control character; terminate frame reception if dl[i] != XGMII_TERM: # store control character if it's not a termination d.append(dl[i]) c.append(cl[i]) frame.parse(d, c) self.queue.append(frame) self.sync.next = not self.sync if name is not None: print("[%s] Got frame %s" % (name, repr(frame))) frame = None d = [] c = [] break else: d.append(dl[i]) c.append(cl[i])
def send(self, frame): self.queue.append(xgmii_ep.XGMIIFrame(frame))
def check(): yield delay(100) yield clk.posedge rst.next = 1 yield clk.posedge rst.next = 0 yield clk.posedge yield delay(100) yield clk.posedge # testbench stimulus for payload_len in list(range(1, 18)) + list(range(64, 82)): yield clk.posedge print("test 1: test packet, length %d" % payload_len) current_test.next = 1 test_frame = eth_ep.EthFrame() test_frame.eth_dest_mac = 0xDAD1D2D3D4D5 test_frame.eth_src_mac = 0x5A5152535455 test_frame.eth_type = 0x8000 test_frame.payload = bytearray(range(payload_len)) test_frame.update_fcs() axis_frame = test_frame.build_axis_fcs() xgmii_frame = xgmii_ep.XGMIIFrame( b'\x55\x55\x55\x55\x55\x55\x55\xD5' + bytearray(axis_frame)) source.send(xgmii_frame) yield sink.wait() rx_frame = sink.recv() eth_frame = eth_ep.EthFrame() eth_frame.parse_axis(rx_frame) eth_frame.update_fcs() assert eth_frame == test_frame assert sink.empty() yield delay(100) yield clk.posedge print("test 2: back-to-back packets, length %d" % payload_len) current_test.next = 2 test_frame1 = eth_ep.EthFrame() test_frame1.eth_dest_mac = 0xDAD1D2D3D4D5 test_frame1.eth_src_mac = 0x5A5152535455 test_frame1.eth_type = 0x8000 test_frame1.payload = bytearray(range(payload_len)) test_frame1.update_fcs() test_frame2 = eth_ep.EthFrame() test_frame2.eth_dest_mac = 0xDAD1D2D3D4D5 test_frame2.eth_src_mac = 0x5A5152535455 test_frame2.eth_type = 0x8000 test_frame2.payload = bytearray(range(payload_len)) test_frame2.update_fcs() axis_frame1 = test_frame1.build_axis_fcs() axis_frame2 = test_frame2.build_axis_fcs() xgmii_frame1 = xgmii_ep.XGMIIFrame( b'\x55\x55\x55\x55\x55\x55\x55\xD5' + bytearray(axis_frame1)) xgmii_frame2 = xgmii_ep.XGMIIFrame( b'\x55\x55\x55\x55\x55\x55\x55\xD5' + bytearray(axis_frame2)) source.send(xgmii_frame1) source.send(xgmii_frame2) yield sink.wait() rx_frame = sink.recv() eth_frame = eth_ep.EthFrame() eth_frame.parse_axis(rx_frame) eth_frame.update_fcs() assert eth_frame == test_frame1 yield sink.wait() rx_frame = sink.recv() eth_frame = eth_ep.EthFrame() eth_frame.parse_axis(rx_frame) eth_frame.update_fcs() assert eth_frame == test_frame2 assert sink.empty() yield delay(100) yield clk.posedge print("test 3: truncated frame, length %d" % payload_len) current_test.next = 3 test_frame1 = eth_ep.EthFrame() test_frame1.eth_dest_mac = 0xDAD1D2D3D4D5 test_frame1.eth_src_mac = 0x5A5152535455 test_frame1.eth_type = 0x8000 test_frame1.payload = bytearray(range(payload_len)) test_frame1.update_fcs() test_frame2 = eth_ep.EthFrame() test_frame2.eth_dest_mac = 0xDAD1D2D3D4D5 test_frame2.eth_src_mac = 0x5A5152535455 test_frame2.eth_type = 0x8000 test_frame2.payload = bytearray(range(payload_len)) test_frame2.update_fcs() axis_frame1 = test_frame1.build_axis_fcs() axis_frame2 = test_frame2.build_axis_fcs() axis_frame1.data = axis_frame1.data[:-1] error_bad_frame_asserted.next = 0 error_bad_fcs_asserted.next = 0 xgmii_frame1 = xgmii_ep.XGMIIFrame( b'\x55\x55\x55\x55\x55\x55\x55\xD5' + bytearray(axis_frame1)) xgmii_frame2 = xgmii_ep.XGMIIFrame( b'\x55\x55\x55\x55\x55\x55\x55\xD5' + bytearray(axis_frame2)) source.send(xgmii_frame1) source.send(xgmii_frame2) yield sink.wait() rx_frame = sink.recv() assert error_bad_frame_asserted assert error_bad_fcs_asserted assert rx_frame.user[-1] yield sink.wait() rx_frame = sink.recv() eth_frame = eth_ep.EthFrame() eth_frame.parse_axis(rx_frame) eth_frame.update_fcs() assert eth_frame == test_frame2 assert sink.empty() yield delay(100) yield clk.posedge print("test 4: errored frame, length %d" % payload_len) current_test.next = 4 test_frame1 = eth_ep.EthFrame() test_frame1.eth_dest_mac = 0xDAD1D2D3D4D5 test_frame1.eth_src_mac = 0x5A5152535455 test_frame1.eth_type = 0x8000 test_frame1.payload = bytearray(range(payload_len)) test_frame1.update_fcs() test_frame2 = eth_ep.EthFrame() test_frame2.eth_dest_mac = 0xDAD1D2D3D4D5 test_frame2.eth_src_mac = 0x5A5152535455 test_frame2.eth_type = 0x8000 test_frame2.payload = bytearray(range(payload_len)) test_frame2.update_fcs() axis_frame1 = test_frame1.build_axis_fcs() axis_frame2 = test_frame2.build_axis_fcs() error_bad_frame_asserted.next = 0 error_bad_fcs_asserted.next = 0 xgmii_frame1 = xgmii_ep.XGMIIFrame( b'\x55\x55\x55\x55\x55\x55\x55\xD5' + bytearray(axis_frame1)) xgmii_frame2 = xgmii_ep.XGMIIFrame( b'\x55\x55\x55\x55\x55\x55\x55\xD5' + bytearray(axis_frame2)) xgmii_frame1.error = 1 source.send(xgmii_frame1) source.send(xgmii_frame2) yield sink.wait() rx_frame = sink.recv() assert error_bad_frame_asserted assert not error_bad_fcs_asserted assert rx_frame.last_cycle_user yield sink.wait() rx_frame = sink.recv() eth_frame = eth_ep.EthFrame() eth_frame.parse_axis(rx_frame) eth_frame.update_fcs() assert eth_frame == test_frame2 assert sink.empty() yield delay(100) for payload_len in list(range(46, 54)): yield clk.posedge print("test 5: test stream, length %d" % payload_len) current_test.next = 5 for i in range(10): test_frame = eth_ep.EthFrame() test_frame.eth_dest_mac = 0xDAD1D2D3D4D5 test_frame.eth_src_mac = 0x5A5152535455 test_frame.eth_type = 0x8000 test_frame.payload = bytearray(range(payload_len)) test_frame.update_fcs() axis_frame = test_frame.build_axis_fcs() source.send(b'\x55\x55\x55\x55\x55\x55\x55\xD5' + bytearray(axis_frame)) for i in range(10): yield sink.wait() rx_frame = sink.recv() eth_frame = eth_ep.EthFrame() eth_frame.parse_axis(rx_frame) eth_frame.update_fcs() assert eth_frame == test_frame yield delay(100) for payload_len in list(range(46, 54)): yield clk.posedge print("test 6: test stream with zero IFG, length %d" % payload_len) current_test.next = 6 source.ifg = 0 for i in range(10): test_frame = eth_ep.EthFrame() test_frame.eth_dest_mac = 0xDAD1D2D3D4D5 test_frame.eth_src_mac = 0x5A5152535455 test_frame.eth_type = 0x8000 test_frame.payload = bytearray(range(payload_len)) test_frame.update_fcs() axis_frame = test_frame.build_axis_fcs() source.send(b'\x55\x55\x55\x55\x55\x55\x55\xD5' + bytearray(axis_frame)) for i in range(10): yield sink.wait() rx_frame = sink.recv() eth_frame = eth_ep.EthFrame() eth_frame.parse_axis(rx_frame) eth_frame.update_fcs() assert eth_frame == test_frame source.ifg = 12 yield delay(100) yield clk.posedge print( "test 7: Ensure 0xfb in FCS in lane 4 is not detected as start code in lane 0" ) current_test.next = 7 test_frame = eth_ep.EthFrame() test_frame.eth_dest_mac = 0xDAD1D2D3D4D5 test_frame.eth_src_mac = 0x5A5152535455 test_frame.eth_type = 0x806f test_frame.payload = bytearray(range(60)) test_frame.update_fcs() axis_frame = test_frame.build_axis_fcs() error_bad_frame_asserted.next = 0 error_bad_fcs_asserted.next = 0 xgmii_frame = xgmii_ep.XGMIIFrame(b'\x55\x55\x55\x55\x55\x55\x55\xD5' + bytearray(axis_frame)) source.send(xgmii_frame) yield sink.wait() rx_frame = sink.recv() assert not error_bad_frame_asserted assert not error_bad_fcs_asserted assert not rx_frame.last_cycle_user eth_frame = eth_ep.EthFrame() eth_frame.parse_axis(rx_frame) eth_frame.update_fcs() assert eth_frame == test_frame assert sink.empty() yield delay(100) raise StopSimulation
def check(): yield delay(100) yield clk.posedge rst.next = 1 yield clk.posedge rst.next = 0 yield clk.posedge yield delay(100) yield clk.posedge # testbench stimulus for payload_len in list(range(1,18))+list(range(64,82)): yield clk.posedge print("test 1: test packet, length %d" % payload_len) current_test.next = 1 test_frame = eth_ep.EthFrame() test_frame.eth_dest_mac = 0xDAD1D2D3D4D5 test_frame.eth_src_mac = 0x5A5152535455 test_frame.eth_type = 0x8000 test_frame.payload = bytearray(range(payload_len)) test_frame.update_fcs() axis_frame = test_frame.build_axis_fcs() xgmii_frame = xgmii_ep.XGMIIFrame(b'\x55\x55\x55\x55\x55\x55\x55\xD5'+bytearray(axis_frame)) source_queue.put(xgmii_frame) yield clk.posedge yield clk.posedge while xgmii_rxc != 0xff or output_axis_tvalid or not source_queue.empty(): yield clk.posedge yield clk.posedge yield clk.posedge yield clk.posedge rx_frame = None if not sink_queue.empty(): rx_frame = sink_queue.get() eth_frame = eth_ep.EthFrame() eth_frame.parse_axis(rx_frame) eth_frame.update_fcs() assert eth_frame == test_frame assert sink_queue.empty() yield delay(100) yield clk.posedge print("test 2: back-to-back packets, length %d" % payload_len) current_test.next = 2 test_frame1 = eth_ep.EthFrame() test_frame1.eth_dest_mac = 0xDAD1D2D3D4D5 test_frame1.eth_src_mac = 0x5A5152535455 test_frame1.eth_type = 0x8000 test_frame1.payload = bytearray(range(payload_len)) test_frame1.update_fcs() test_frame2 = eth_ep.EthFrame() test_frame2.eth_dest_mac = 0xDAD1D2D3D4D5 test_frame2.eth_src_mac = 0x5A5152535455 test_frame2.eth_type = 0x8000 test_frame2.payload = bytearray(range(payload_len)) test_frame2.update_fcs() axis_frame1 = test_frame1.build_axis_fcs() axis_frame2 = test_frame2.build_axis_fcs() xgmii_frame1 = xgmii_ep.XGMIIFrame(b'\x55\x55\x55\x55\x55\x55\x55\xD5'+bytearray(axis_frame1)) xgmii_frame2 = xgmii_ep.XGMIIFrame(b'\x55\x55\x55\x55\x55\x55\x55\xD5'+bytearray(axis_frame2)) source_queue.put(xgmii_frame1) source_queue.put(xgmii_frame2) yield clk.posedge yield clk.posedge while xgmii_rxc != 0xff or output_axis_tvalid or not source_queue.empty(): yield clk.posedge yield clk.posedge while xgmii_rxc != 0xff or output_axis_tvalid or not source_queue.empty(): yield clk.posedge yield clk.posedge yield clk.posedge yield clk.posedge rx_frame = None if not sink_queue.empty(): rx_frame = sink_queue.get() eth_frame = eth_ep.EthFrame() eth_frame.parse_axis(rx_frame) eth_frame.update_fcs() assert eth_frame == test_frame1 rx_frame = None if not sink_queue.empty(): rx_frame = sink_queue.get() eth_frame = eth_ep.EthFrame() eth_frame.parse_axis(rx_frame) eth_frame.update_fcs() assert eth_frame == test_frame2 assert sink_queue.empty() yield delay(100) yield clk.posedge print("test 3: truncated frame, length %d" % payload_len) current_test.next = 3 test_frame1 = eth_ep.EthFrame() test_frame1.eth_dest_mac = 0xDAD1D2D3D4D5 test_frame1.eth_src_mac = 0x5A5152535455 test_frame1.eth_type = 0x8000 test_frame1.payload = bytearray(range(payload_len)) test_frame1.update_fcs() test_frame2 = eth_ep.EthFrame() test_frame2.eth_dest_mac = 0xDAD1D2D3D4D5 test_frame2.eth_src_mac = 0x5A5152535455 test_frame2.eth_type = 0x8000 test_frame2.payload = bytearray(range(payload_len)) test_frame2.update_fcs() axis_frame1 = test_frame1.build_axis_fcs() axis_frame2 = test_frame2.build_axis_fcs() axis_frame1.data = axis_frame1.data[:-1] error_bad_frame_asserted.next = 0 error_bad_fcs_asserted.next = 0 xgmii_frame1 = xgmii_ep.XGMIIFrame(b'\x55\x55\x55\x55\x55\x55\x55\xD5'+bytearray(axis_frame1)) xgmii_frame2 = xgmii_ep.XGMIIFrame(b'\x55\x55\x55\x55\x55\x55\x55\xD5'+bytearray(axis_frame2)) source_queue.put(xgmii_frame1) source_queue.put(xgmii_frame2) yield clk.posedge yield clk.posedge while xgmii_rxc != 0xff or output_axis_tvalid or not source_queue.empty(): yield clk.posedge yield clk.posedge while xgmii_rxc != 0xff or output_axis_tvalid or not source_queue.empty(): yield clk.posedge yield clk.posedge yield clk.posedge yield clk.posedge assert error_bad_frame_asserted assert error_bad_fcs_asserted rx_frame = None if not sink_queue.empty(): rx_frame = sink_queue.get() assert rx_frame.user[-1] rx_frame = None if not sink_queue.empty(): rx_frame = sink_queue.get() eth_frame = eth_ep.EthFrame() eth_frame.parse_axis(rx_frame) eth_frame.update_fcs() assert eth_frame == test_frame2 assert sink_queue.empty() yield delay(100) yield clk.posedge print("test 4: errored frame, length %d" % payload_len) current_test.next = 4 test_frame1 = eth_ep.EthFrame() test_frame1.eth_dest_mac = 0xDAD1D2D3D4D5 test_frame1.eth_src_mac = 0x5A5152535455 test_frame1.eth_type = 0x8000 test_frame1.payload = bytearray(range(payload_len)) test_frame1.update_fcs() test_frame2 = eth_ep.EthFrame() test_frame2.eth_dest_mac = 0xDAD1D2D3D4D5 test_frame2.eth_src_mac = 0x5A5152535455 test_frame2.eth_type = 0x8000 test_frame2.payload = bytearray(range(payload_len)) test_frame2.update_fcs() axis_frame1 = test_frame1.build_axis_fcs() axis_frame2 = test_frame2.build_axis_fcs() error_bad_frame_asserted.next = 0 error_bad_fcs_asserted.next = 0 xgmii_frame1 = xgmii_ep.XGMIIFrame(b'\x55\x55\x55\x55\x55\x55\x55\xD5'+bytearray(axis_frame1)) xgmii_frame2 = xgmii_ep.XGMIIFrame(b'\x55\x55\x55\x55\x55\x55\x55\xD5'+bytearray(axis_frame2)) xgmii_frame1.error = 1 source_queue.put(xgmii_frame1) source_queue.put(xgmii_frame2) yield clk.posedge yield clk.posedge while xgmii_rxc != 0xff or output_axis_tvalid or not source_queue.empty(): yield clk.posedge yield clk.posedge while xgmii_rxc != 0xff or output_axis_tvalid or not source_queue.empty(): yield clk.posedge yield clk.posedge yield clk.posedge yield clk.posedge assert error_bad_frame_asserted assert not error_bad_fcs_asserted rx_frame = None if not sink_queue.empty(): rx_frame = sink_queue.get() assert rx_frame.user[-1] rx_frame = None if not sink_queue.empty(): rx_frame = sink_queue.get() eth_frame = eth_ep.EthFrame() eth_frame.parse_axis(rx_frame) eth_frame.update_fcs() assert eth_frame == test_frame2 assert sink_queue.empty() yield delay(100) for payload_len in list(range(46,54)): yield clk.posedge print("test 5: test stream, length %d" % payload_len) current_test.next = 5 for i in range(10): test_frame = eth_ep.EthFrame() test_frame.eth_dest_mac = 0xDAD1D2D3D4D5 test_frame.eth_src_mac = 0x5A5152535455 test_frame.eth_type = 0x8000 test_frame.payload = bytearray(range(payload_len)) test_frame.update_fcs() axis_frame = test_frame.build_axis_fcs() source_queue.put(b'\x55\x55\x55\x55\x55\x55\x55\xD5'+bytearray(axis_frame)) yield clk.posedge yield clk.posedge while xgmii_rxc != 0xff or output_axis_tvalid or not source_queue.empty(): yield clk.posedge yield clk.posedge yield clk.posedge yield clk.posedge yield delay(100) raise StopSimulation
def check(): yield delay(100) yield clk.posedge rst.next = 1 yield clk.posedge rst.next = 0 yield clk.posedge yield delay(100) yield clk.posedge # testbench stimulus for payload_len in list(range(16, 34)): yield clk.posedge print("test 1: test packet, length %d" % payload_len) current_test.next = 1 test_frame = bytearray(range(payload_len)) xgmii_frame = xgmii_ep.XGMIIFrame( b'\x55\x55\x55\x55\x55\x55\x55\xD5' + test_frame) source.send(xgmii_frame) yield sink.wait() rx_frame = sink.recv() assert rx_frame.data == xgmii_frame.data assert sink.empty() yield delay(100) yield clk.posedge print("test 2: back-to-back packets, length %d" % payload_len) current_test.next = 2 test_frame1 = bytearray(range(payload_len)) test_frame2 = bytearray(range(payload_len)) xgmii_frame1 = xgmii_ep.XGMIIFrame( b'\x55\x55\x55\x55\x55\x55\x55\xD5' + test_frame1) xgmii_frame2 = xgmii_ep.XGMIIFrame( b'\x55\x55\x55\x55\x55\x55\x55\xD5' + test_frame2) source.send(xgmii_frame1) source.send(xgmii_frame2) yield sink.wait() rx_frame = sink.recv() assert rx_frame.data == xgmii_frame1.data yield sink.wait() rx_frame = sink.recv() assert rx_frame.data == xgmii_frame2.data assert sink.empty() yield delay(100) yield clk.posedge print("test 3: errored frame, length %d" % payload_len) current_test.next = 3 test_frame1 = bytearray(range(payload_len)) test_frame2 = bytearray(range(payload_len)) xgmii_frame1 = xgmii_ep.XGMIIFrame( b'\x55\x55\x55\x55\x55\x55\x55\xD5' + test_frame1) xgmii_frame2 = xgmii_ep.XGMIIFrame( b'\x55\x55\x55\x55\x55\x55\x55\xD5' + test_frame2) xgmii_frame1.error = 1 source.send(xgmii_frame1) source.send(xgmii_frame2) yield sink.wait() rx_frame = sink.recv() #assert rx_frame.data == xgmii_frame1.data yield sink.wait() rx_frame = sink.recv() assert rx_frame.data == xgmii_frame2.data assert sink.empty() yield delay(100) yield clk.posedge print("test 4: PRBS31 generation") current_test.next = 4 tx_prbs31_enable.next = True yield delay(100) prbs_gen = prbs31(66) prbs_data = [next(prbs_gen) for x in range(100)] for k in range(20): yield clk.posedge data = int(serdes_tx_data) << 2 | int(serdes_tx_hdr) assert data in prbs_data tx_prbs31_enable.next = False yield delay(100) raise StopSimulation
def check(): yield delay(100) yield clk.posedge rst.next = 1 yield clk.posedge rst.next = 0 yield clk.posedge yield delay(100) yield clk.posedge # testbench stimulus # wait for block lock while not rx_block_lock: yield clk.posedge # dump garbage while not sink.empty(): sink.recv() for payload_len in list(range(16,34)): yield clk.posedge print("test 1: test packet, length %d" % payload_len) current_test.next = 1 test_frame = bytearray(range(payload_len)) xgmii_frame = xgmii_ep.XGMIIFrame(b'\x55\x55\x55\x55\x55\x55\x55\xD5'+test_frame) source.send(xgmii_frame) yield sink.wait() rx_frame = sink.recv() assert rx_frame.data == xgmii_frame.data assert sink.empty() yield delay(100) yield clk.posedge print("test 2: back-to-back packets, length %d" % payload_len) current_test.next = 2 test_frame1 = bytearray(range(payload_len)) test_frame2 = bytearray(range(payload_len)) xgmii_frame1 = xgmii_ep.XGMIIFrame(b'\x55\x55\x55\x55\x55\x55\x55\xD5'+test_frame1) xgmii_frame2 = xgmii_ep.XGMIIFrame(b'\x55\x55\x55\x55\x55\x55\x55\xD5'+test_frame2) source.send(xgmii_frame1) source.send(xgmii_frame2) yield sink.wait() rx_frame = sink.recv() assert rx_frame.data == xgmii_frame1.data yield sink.wait() rx_frame = sink.recv() assert rx_frame.data == xgmii_frame2.data assert sink.empty() yield delay(100) yield clk.posedge print("test 3: errored frame, length %d" % payload_len) current_test.next = 3 test_frame1 = bytearray(range(payload_len)) test_frame2 = bytearray(range(payload_len)) xgmii_frame1 = xgmii_ep.XGMIIFrame(b'\x55\x55\x55\x55\x55\x55\x55\xD5'+test_frame1) xgmii_frame2 = xgmii_ep.XGMIIFrame(b'\x55\x55\x55\x55\x55\x55\x55\xD5'+test_frame2) xgmii_frame1.error = 1 source.send(xgmii_frame1) source.send(xgmii_frame2) yield sink.wait() rx_frame = sink.recv() #assert rx_frame.data == xgmii_frame1.data yield sink.wait() rx_frame = sink.recv() assert rx_frame.data == xgmii_frame2.data assert sink.empty() yield delay(100) yield clk.posedge print("test 4: test frame sync") current_test.next = 4 assert rx_block_lock load_bit_offset.append(33) yield delay(600) assert not rx_block_lock assert rx_high_ber yield delay(3000) assert rx_block_lock yield delay(2000) assert not rx_high_ber yield delay(100) yield clk.posedge print("test 5: PRBS31 check") current_test.next = 5 rx_prbs31_enable.next = True yield delay(100) for k in range(20): yield clk.posedge assert rx_error_count > 0 prbs_en.next = True yield delay(100) for k in range(20): yield clk.posedge assert rx_error_count == 0 prbs_en.next = False rx_prbs31_enable.next = False yield delay(100) raise StopSimulation