def __init__(self, memory_dict):
#______ Buses ______
self.Main_bus = Bus.Bus(4)
self.Memory_address_bus = Bus.Bus(4)
self.ALU_op_bus = Bus.Bus(1)
self.Register_address_bus = Bus.Bus(1)
self.Output_address_bus = Bus.Bus
self.Registers = Registers.Register_bank(self.Main_bus,
self.Register_address_bus)
self.Memory_address_register = Registers.Memory_address_register(
self.Main_bus, self.Memory_address_bus, 4)
self.Memory = Memory.Memory(self.Memory_address_bus, self.Main_bus,
memory_dict)
self.ALU = ALU.ALU(self.Main_bus, self.Main_bus, self.ALU_op_bus)
self.Output = Output.IO(self.Main_bus, self.Output_address_bus)
self.halt = 0
self.instruction_count = 0
def __init__(self, memory_dict):
#______ Buses ______
self.Main_bus = Bus.Bus(4)
self.Memory_address_bus = Bus.Bus(4)
self.ALU_op_bus = Bus.Bus(1)
self.Register_address_bus = Bus.Bus(1)
self.Output_address_bus = Bus.Bus
self.Registers = Registers.Register_bank(self.Main_bus,
self.Register_address_bus)
self.Memory_address_register = Registers.Memory_address_register(
self.Main_bus, self.Memory_address_bus, 4)
self.Memory = Memory.Memory(self.Memory_address_bus, self.Main_bus,
memory_dict)
self.ALU = ALU.ALU(self.Main_bus, self.Main_bus, self.ALU_op_bus)
self.Output = Output.IO(self.Main_bus, self.Output_address_bus)
self.halt = 0
self.instruction_count = 0
self.instr_dict = {
0: self.Halt,
1: self.Noop,
2: self.Move,
3: self.Load,
4: self.Store,
5: self.Compare_reg,
6: self.Compare_addr,
7: self.Out_reg,
8: self.Out_addr,
9: self.Outd_reg,
10: self.Outd_addr,
11: self.Load_byte,
12: self.Store_byte,
13: self.Load_word,
14: self.Store_word,
16: self.ALU_reg,
17: self.ALU_reg,
18: self.ALU_reg,
19: self.ALU_reg,
20: self.ALU_reg,
21: self.ALU_reg,
22: self.ALU_reg,
23: self.ALU_reg,
24: self.ALU_reg,
25: self.ALU_reg,
26: self.ALU_reg,
27: self.ALU_reg,
28: self.ALU_reg,
29: self.ALU_reg,
30: self.ALU_reg,
31: self.ALU_reg,
32: self.ALU_addr,
33: self.ALU_addr,
34: self.ALU_addr,
35: self.ALU_addr,
36: self.ALU_addr,
37: self.ALU_addr,
38: self.ALU_addr,
39: self.ALU_addr,
40: self.ALU_addr,
41: self.ALU_addr,
42: self.ALU_addr,
43: self.ALU_addr,
44: self.ALU_addr,
45: self.ALU_addr,
46: self.ALU_addr,
47: self.ALU_addr,
48: self.In_reg,
49: self.In_addr
}
