def constructDMem(): memory = [Bus(64) for i in range(5)] memory[0] = Bus(0, list(map(int, HexToBin('0x0000000000000001')))) memory[1] = Bus(0, list(map(int, HexToBin('0x000000000000000A')))) memory[2] = Bus(0, list(map(int, HexToBin('0x0000000000000005')))) memory[3] = Bus(0, list(map(int, HexToBin('0x123456789ABCEDFA')))) output = Memory(False) output.mem = memory return output
def __init__(self): self.branch = 0 self.uncondbranch = 0 self.memread = 0 self.memwrite = 0 self.mem2reg = 0 self.reg2loc = 0 self.aluop = Bus(4) self.signop = Bus(3) self.regwrite = 0 self.alusrc = 0
def TwosComp(self, source): one = Bus(source.size) invertedSource = Bus(source.size) for i in range(source.size): invertedSource.set(i, not source.at(i)) if (i == 0): one.set(0, 1) else: one.set(i, 0) outputBus, trash = self.add(invertedSource, one) return outputBus
def runCycle(self): #fetch the instruction from IMem instruction = self.IMem.performOp(self.PC, None, 1, 0) #get control signals self.Control.performOp(instruction.slice(31, 21)) #reg file Source1Loc = instruction.slice(9, 5) Source2UpperBound = [20] Source2LowerBound = [16] if (self.Control.reg2loc): Source2UpperBound = [4] Source2LowerBound = [0] Source2Loc = instruction.slice(Source2UpperBound[0], Source2LowerBound[0]) Source1, Source2 = self.regFile.performOp(0, Source1Loc, Source2Loc, None, None) #sign extension Imm26 = instruction.slice(25, 0) extendedImmediate = self.signExtender.performOp( self.Control.signop, Imm26) #ALU writeData = deepcopy(Source2) if (self.Control.alusrc): Source2 = extendedImmediate ALUOutput, self.aluZero = self.ALU.performOp(self.Control.aluop, Source1, Source2) #DMem DMemOutput = self.DMem.performOp(ALUOutput, writeData, self.Control.memread, self.Control.memwrite) #Write back to reg file writeReg = instruction.slice(4, 0) writeData = ALUOutput if (self.Control.mem2reg): writeData = DMemOutput self.regFile.performOp(self.Control.regwrite, Bus(5), Bus(5), writeReg, writeData) #NextPC self.PC = self.nextPCLogic.performOp(self.Control.uncondbranch, self.Control.branch, self.aluZero, extendedImmediate, self.PC) return (self.PC, DMemOutput)
def performOp(self, regwrite, loc1, loc2, writeLoc, writeData): #assume that we cannot write and read at the same time #the regwrite signal indicates whether we are writing or reading to the reg file if (regwrite): index = locToIndex(writeLoc) #preserve XZR if (index != 31): self.file[locToIndex(writeLoc)] = writeData return (Bus(64), Bus(64)) else: return1 = self.file[locToIndex(loc1)] return2 = self.file[locToIndex(loc2)] return (return1, return2)
def createImmFromSymbol(iNum, symbTable, symbol, immSize): desiredInstruction = symbTable[symbol] if (desiredInstruction == iNum): print('Error: symbol references current instruction') isNeg = False diff = desiredInstruction - iNum if (diff < 0): isNeg = True #create a bus of the immediate if (isNeg): binDiff = bin(diff)[3:] else: binDiff = bin(diff)[2:] lstBus = [] for bit in binDiff: lstBus.append(int(bit)) #adjust the size of the immediate if (len(lstBus) > immSize): print("Warning: sybol immediate greater than max immediate size") while (len(lstBus) < immSize): #sign extend lstBus.insert(0, 0) while (len(lstBus) > immSize): del lstBus[0] imm = Bus(0, lstBus) if (isNeg): twosComp = ALU() return twosComp.TwosComp(imm) return imm
def createRegister(reg): if (reg == 'XZR'): return Bus(0, [1, 1, 1, 1, 1]) #remove the extra X reg = reg[1:] binaryReg = bin(int(reg))[2:] if (len(binaryReg) > 5): print("Reg is too large") return Bus(5) while (len(binaryReg) < 5): binaryReg = '0' + binaryReg lstBus = [] for char in binaryReg: lstBus.append(int(char)) return Bus(0, lstBus)
def createImm(imm): #remove the 0x imm = imm[2:] binImm = '' for hexChar in imm: binImm += HexToBin('0x' + hexChar) lstBus = [] for char in binImm: lstBus.append(int(char)) return Bus(0, lstBus)
def createRTypeInstruction(args): op = deepcopy(instructionToOp[args[0]]) Rd = createRegister(args[1]) shamt = Bus(6) Rn = createRegister(args[2]) Rm = createRegister(args[3]) instruction = op + Rm instruction = instruction + shamt instruction = instruction + Rn instruction = instruction + Rd return instruction
def performOp(self, aluop, s1, s2, setFlags=False): outputBus = Bus(s1.size) zero = [1] if (aluop == AND): for i in range(s1.size): newBit = s1.at(i) and s2.at(i) if (newBit and zero): zero[0] = 0 outputBus.set(i, newBit) i -= 1 elif (aluop == ORR): for i in range(s1.size): newBit = s1.at(i) or s2.at(i) if (newBit and zero): zero[0] = 0 outputBus.set(i, newBit) i -= 1 elif (aluop == ADD): outputBus, zero[0] = self.add(s1, s2) elif (aluop == SUB): outputBus, zero[0] = self.add(s1, self.TwosComp(s2)) elif (aluop == PASSSB): outputBus = s2 for i in range(s2.size): if (s2.at(i)): zero[0] = 0 break else: print("Error with aluop") zero[0] = 0 return outputBus, zero[0]
def __init__(self, initialPC=Bus(64), IMem=Memory(True), DMem=Memory(False)): self.ALU = ALU() self.IMem = IMem self.DMem = DMem self.signExtender = SignExtender() self.regFile = RegisterFile() self.Control = Control() self.nextPCLogic = NextPCLogic() self.PC = initialPC self.aluZero = 0
def parseLine(line, instructionNumber, symbolTable): args = parseArgs(line) if (args == None): #symbol return None if (args[0] == "ADD"): #scan for ADD or ADDI isAddI = False for arg in args: if (arg[0:2] == '0x'): isAddI = True if (isAddI): return createITypeInstruction(args) else: return createRTypeInstruction(args) elif (args[0] == 'SUB'): #scan for SUB or SUBI isSubI = False for arg in args: if (arg[0:2] == '0x'): isSubI = True if (isSubI): return createITypeInstruction(args) else: return createRTypeInstruction(args) elif (args[0] == 'AND'): return createRTypeInstruction(args) elif (args[0] == "ORR"): return createRTypeInstruction(args) elif (args[0] == "LDUR"): return createDTypeInstruction(args) elif (args[0] == "STUR"): return createDTypeInstruction(args) elif (args[0] == 'B'): return createBTypeInstruction(args, symbolTable, instructionNumber) elif (args[0] == "CBZ"): return createCBTypeInstruction(args, symbolTable, instructionNumber) else: print('Could not interpret the opcode') return Bus(32)
def shiftImm(self, imm): newImm = Bus(64) newImm.set(0, 0) newImm.set(1, 0) i = 2 while(i < 64): newImm.set(i, imm.at(i-2)) i += 1 return newImm
def performOp(self, addr, writeData, memread, memwrite): index = 0 if (self.isIMem): index = indexToInstructionMemAddress(locToIndex(addr)) else: index = indexToDataMemAddress(locToIndex(addr)) if (memread and memwrite): print("Error, cannot read and write at the same time") elif (memread): return self.mem[index] elif (memwrite): self.mem[index] = writeData return Bus(64)
def createDTypeInstruction(args): op = deepcopy(instructionToOp[args[0]]) Rt = createRegister(args[1]) Rn = createRegister(args[2]) imm = createImm(args[3]) #correct the length of the immediate if (imm.size > 9): "Warnging: D-type immediate is too large" while (imm.size < 9): imm.bus.insert(0, 0) imm.size += 1 while (imm.size > 9): del imm.bus[0] imm.size -= 1 extra = Bus(2) instruction = op + imm instruction = instruction + extra instruction = instruction + Rn instruction = instruction + Rt return instruction
def performOp(self, signop, Imm26): extBit = [] extensionIndex = [] outputBus = Bus(64) if (signop == ITYPE): extBit.append(0) i = 10 j = 0 extensionIndex.append(12) while (i <= 21): outputBus.set(j, Imm26.at(i)) i += 1 j += 1 elif (signop == DTYPE): extBit.append(Imm26.at(20)) i = 12 j = 0 extensionIndex.append(9) while (i <= 20): outputBus.set(j, Imm26.at(i)) i += 1 j += 1 elif (signop == CBTYPE): extBit.append(Imm26.at(23)) i = 5 j = 0 extensionIndex.append(19) while (i <= 23): outputBus.set(j, Imm26.at(i)) i += 1 j += 1 elif (signop == BTYPE): extBit.append(Imm26.at(25)) i = 0 extensionIndex.append(25) while (i <= 25): outputBus.set(i, Imm26.at(i)) i += 1 else: print("Error in sign extender") i = extensionIndex[0] while (i < 64): outputBus.set(i, extBit[0]) i += 1 return outputBus
from Common import Bus ITYPE = Bus(0, [0, 0, 0]) DTYPE = Bus(0, [0, 0, 1]) CBTYPE = Bus(0, [0, 1, 0]) BTYPE = Bus(0, [0, 1, 1]) MOVZ = Bus(0, [1, 0, 0]) class SignExtender: def performOp(self, signop, Imm26): extBit = [] extensionIndex = [] outputBus = Bus(64) if (signop == ITYPE): extBit.append(0) i = 10 j = 0 extensionIndex.append(12) while (i <= 21): outputBus.set(j, Imm26.at(i)) i += 1 j += 1 elif (signop == DTYPE): extBit.append(Imm26.at(20)) i = 12 j = 0 extensionIndex.append(9) while (i <= 20): outputBus.set(j, Imm26.at(i))
def performOp(self, opcode): if (opcode == OPCODE_ADDREG): self.branch = 0 self.uncondbranch = 0 self.memread = 0 self.memwrite = 0 self.mem2reg = 0 self.reg2loc = 0 self.aluop = Bus(0, [0, 0, 1, 0]) self.signop = Bus(3) self.regwrite = 1 self.alusrc = 0 elif (opcode == OPCODE_SUBREG): self.branch = 0 self.uncondbranch = 0 self.memread = 0 self.memwrite = 0 self.mem2reg = 0 self.reg2loc = 0 self.aluop = Bus(0, [0, 0, 1, 1]) self.signop = Bus(3) self.regwrite = 1 self.alusrc = 0 elif (opcode == OPCODE_ANDREG): self.branch = 0 self.uncondbranch = 0 self.memread = 0 self.memwrite = 0 self.mem2reg = 0 self.reg2loc = 0 self.aluop = Bus(0, [0, 0, 0, 0]) self.signop = Bus(3) self.regwrite = 1 self.alusrc = 0 elif (opcode == OPCODE_ORRREG): self.branch = 0 self.uncondbranch = 0 self.memread = 0 self.memwrite = 0 self.mem2reg = 0 self.reg2loc = 0 self.aluop = Bus(0, [0, 0, 0, 1]) self.signop = Bus(3) self.regwrite = 1 self.alusrc = 0 elif (opcode == OPCODE_LDUR): self.branch = 0 self.uncondbranch = 0 self.memread = 1 self.memwrite = 0 self.mem2reg = 1 self.reg2loc = 1 self.aluop = Bus(0, [0, 0, 1, 0]) self.signop = Bus(0, [0, 0, 1]) self.regwrite = 1 self.alusrc = 1 elif (opcode == OPCODE_STUR): self.branch = 0 self.uncondbranch = 0 self.memread = 0 self.memwrite = 1 self.mem2reg = 0 self.reg2loc = 1 self.aluop = Bus(0, [0, 0, 1, 0]) self.signop = Bus(0, [0, 0, 1]) self.regwrite = 0 self.alusrc = 1 elif (opcode.slice(10, 1) == OPCODE_ADDIMM): self.branch = 0 self.uncondbranch = 0 self.memread = 0 self.memwrite = 0 self.mem2reg = 0 self.reg2loc = 0 self.aluop = Bus(0, [0, 0, 1, 0]) self.signop = Bus(3) self.regwrite = 1 self.alusrc = 1 elif (opcode.slice(10, 1) == OPCODE_SUBIMM): self.branch = 0 self.uncondbranch = 0 self.memread = 0 self.memwrite = 0 self.mem2reg = 0 self.reg2loc = 0 self.aluop = Bus(0, [0, 0, 1, 1]) self.signop = Bus(3) self.regwrite = 1 self.alusrc = 1 elif (opcode.slice(10, 5) == OPCODE_B): self.branch = 0 self.uncondbranch = 1 self.memread = 0 self.memwrite = 0 self.mem2reg = 0 self.reg2loc = 0 self.aluop = Bus(4) self.signop = Bus(0, [0, 1, 1]) self.regwrite = 0 self.alusrc = 0 elif (opcode.slice(10, 3) == OPCODE_CBZ): self.branch = 1 self.uncondbranch = 0 self.memread = 0 self.memwrite = 0 self.mem2reg = 0 self.reg2loc = 1 self.aluop = Bus(0, [0, 1, 0, 0]) self.signop = Bus(0, [0, 1, 0]) self.regwrite = 0 self.alusrc = 0 else: print("Error in control block") opcode.print() self.branch = 0 self.uncondbranch = 0 self.memread = 0 self.memwrite = 0 self.mem2reg = 0 self.reg2loc = 0 self.aluop = Bus(4) self.signop = Bus(3) self.regwrite = 0 self.alusrc = 0
import sys from Common import Bus from Common import HexToBin from ALU import ALU from Memory import Memory from Processor import Processor from Common import locToIndex from copy import deepcopy OPCODE_ADDREG = Bus(0, [1, 0, 0, 0, 1, 0, 1, 1, 0, 0, 0]) OPCODE_SUBREG = Bus(0, [1, 1, 0, 0, 1, 0, 1, 1, 0, 0, 0]) OPCODE_ANDREG = Bus(0, [1, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0]) OPCODE_ORRREG = Bus(0, [1, 0, 1, 0, 1, 0, 1, 0, 0, 0, 0]) OPCODE_LDUR = Bus(0, [1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 0]) OPCODE_STUR = Bus(0, [1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0]) OPCODE_ADDIMM = Bus(0, [1, 0, 0, 1, 0, 0, 0, 1, 0, 0]) OPCODE_SUBIMM = Bus(0, [1, 1, 0, 1, 0, 0, 0, 1, 0, 0]) OPCODE_B = Bus(0, [0, 0, 0, 1, 0, 1]) OPCODE_CBZ = Bus(0, [1, 0, 1, 1, 0, 1, 0, 0]) instructionToOp = { "ADD": OPCODE_ADDREG, "ADDI": OPCODE_ADDIMM, "SUB": OPCODE_SUBREG, "SUBI": OPCODE_SUBIMM, "AND": OPCODE_ANDREG, "ORR": OPCODE_ORRREG, "LDUR": OPCODE_LDUR, "STUR": OPCODE_STUR, "B": OPCODE_B, "CBZ": OPCODE_CBZ
from Common import Bus AND = Bus(0, [0, 0, 0, 0]) ORR = Bus(0, [0, 0, 0, 1]) ADD = Bus(0, [0, 0, 1, 0]) SUB = Bus(0, [0, 0, 1, 1]) PASSSB = Bus(0, [0, 1, 0, 0]) class ALU: def __init__(self): #flags will be implemented later, for now the only relevant flag is Zero self.zero = 0 def add(self, s1, s2): cin = 0 outputBus = Bus(s1.size) zero = 1 for i in range(s1.size): bit1 = s1.at(i) bit2 = s2.at(i) if (bit1 and bit2): if (cin): outputBus.set(i, 1) cin = 1 zero = 0 else: outputBus.set(i, 0) cin = 1 elif ((bit1 and not bit2) or (not bit1 and bit2)):
def constructIMem(): ''' /* Test Program 1: * Program loads constants from the data memory. Uses these constants to test * the following instructions: LDUR, ORR, AND, CBZ, ADD, SUB, STUR and B. * * Assembly code for test: * * 0: LDUR X9, [XZR, 0x0] //Load 1 into x9 * 4: LDUR X10, [XZR, 0x8] //Load a into x10 * 8: LDUR X11, [XZR, 0x10] //Load 5 into x11 * C: LDUR X12, [XZR, 0x18] //Load big constant into x12 * 10: LDUR X13, [XZR, 0x20] //load a 0 into X13 * * 14: ORR X10, X10, X11 //Create mask of 0xf * 18: AND X12, X12, X10 //Mask off low order bits of big constant * * loop: * 1C: CBZ X12, end //while X12 is not 0 * 20: ADD X13, X13, X9 //Increment counter in X13 * 24: SUB X12, X12, X9 //Decrement remainder of big constant in X12 * 28: B loop //Repeat till X12 is 0 * 2C: STUR X13, [XZR, 0x20] //store back the counter value into the memory location 0x20 * 30: LDUR X13, [XZR, 0x20] */ 63'h000: Data = 32'hF84003E9; 63'h004: Data = 32'hF84083EA; 63'h008: Data = 32'hF84103EB; 63'h00c: Data = 32'hF84183EC; 63'h010: Data = 32'hF84203ED; 63'h014: Data = 32'hAA0B014A; 63'h018: Data = 32'h8A0A018C; 63'h01c: Data = 32'hB400008C; 63'h020: Data = 32'h8B0901AD; 63'h024: Data = 32'hCB09018C; 63'h028: Data = 32'h17FFFFFD; 63'h02c: Data = 32'hF80203ED; 63'h030: Data = 32'hF84203ED; //One last load to place stored value on memdbus for test checking. ''' memory = [Bus(64) for i in range(13)] memory[0] = (Bus(0, list(map(int, HexToBin('0xF84003E9'))))) memory[1] = (Bus(0, list(map(int, HexToBin('0xF84083EA'))))) memory[2] = (Bus(0, list(map(int, HexToBin('0xF84103EB'))))) memory[3] = (Bus(0, list(map(int, HexToBin('0xF84183EC'))))) memory[4] = (Bus(0, list(map(int, HexToBin('0xF84203ED'))))) memory[5] = (Bus(0, list(map(int, HexToBin('0xAA0B014A'))))) memory[6] = (Bus(0, list(map(int, HexToBin('0x8A0A018C'))))) memory[7] = (Bus(0, list(map(int, HexToBin('0xB400008C'))))) memory[8] = (Bus(0, list(map(int, HexToBin('0x8B0901AD'))))) memory[9] = (Bus(0, list(map(int, HexToBin('0xCB09018C'))))) memory[10] = (Bus(0, list(map(int, HexToBin('0x17FFFFFD'))))) memory[11] = (Bus(0, list(map(int, HexToBin('0xF80203ED'))))) memory[12] = (Bus(0, list(map(int, HexToBin('0xF84203ED'))))) output = Memory(True) output.mem = memory return output
def __init__(self, width=32): self.width = width self.file = [Bus(64) for i in range(width)]
return (Bus(64), Bus(64)) else: return1 = self.file[locToIndex(loc1)] return2 = self.file[locToIndex(loc2)] return (return1, return2) def printRegFile(self, format=''): for i in range(self.width): print('[', i, '] ', sep='', end='') self.file[i].print(format) if __name__ == '__main__': rf = RegisterFile(8) rf.printRegFile('x') bus = Bus(0, [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 ]) loc = Bus(4) loc.set(2, 1) print() rf.performOp(1, Bus(4), Bus(4), loc, bus) trash, newBus = rf.performOp(0, Bus(4), loc, Bus(4), Bus(64)) newBus.print('x')
newImm.set(1, 0) i = 2 while(i < 64): newImm.set(i, imm.at(i-2)) i += 1 return newImm if __name__ == '__main__': npl = NextPCLogic() #shiftedImm = 0x8 imm = Bus(0, [1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0 ]) #currPC = 0x8 currPC = Bus(0, [0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0 ]) npl.performOp(1, 0, 1, imm, currPC).print('x') npl.performOp(0, 1, 1, imm, currPC).print('x') npl.performOp(0, 1, 0, imm, currPC).print('x') alu = ALU()
def runALU(aluop, s1, s2, setFlags=False): outputBus = Bus(s1.size) zero = 1 outputBus, zero = self.performOp(aluop, Source1, Source2) self.zero = zero return outputBus, zero
def __init__(self, isIMem, size=64): self.size = size self.mem = [Bus(64) for i in range(size)] self.isIMem = isIMem
memory[10] = (Bus(0, list(map(int, HexToBin('0x17FFFFFD'))))) memory[11] = (Bus(0, list(map(int, HexToBin('0xF80203ED'))))) memory[12] = (Bus(0, list(map(int, HexToBin('0xF84203ED'))))) output = Memory(True) output.mem = memory return output def constructDMem(): memory = [Bus(64) for i in range(5)] memory[0] = Bus(0, list(map(int, HexToBin('0x0000000000000001')))) memory[1] = Bus(0, list(map(int, HexToBin('0x000000000000000A')))) memory[2] = Bus(0, list(map(int, HexToBin('0x0000000000000005')))) memory[3] = Bus(0, list(map(int, HexToBin('0x123456789ABCEDFA')))) output = Memory(False) output.mem = memory return output if __name__ == '__main__': p = Processor(Bus(64), constructIMem(), constructDMem()) PC = Bus(64) while(locToIndex(PC) < 52): print("PC:", end='') PC.print('x') PC, output = p.runCycle() print('\n-----------------------------------------') print("Final Output: ") output.print() print('-----------------------------------------\n')
from Common import Bus OPCODE_ADDREG = Bus(0, [1, 0, 0, 0, 1, 0, 1, 1, 0, 0, 0]) OPCODE_SUBREG = Bus(0, [1, 1, 0, 0, 1, 0, 1, 1, 0, 0, 0]) OPCODE_ANDREG = Bus(0, [1, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0]) OPCODE_ORRREG = Bus(0, [1, 0, 1, 0, 1, 0, 1, 0, 0, 0, 0]) OPCODE_LDUR = Bus(0, [1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 0]) OPCODE_STUR = Bus(0, [1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0]) OPCODE_ADDIMM = Bus(0, [1, 0, 0, 1, 0, 0, 0, 1, 0, 0]) OPCODE_SUBIMM = Bus(0, [1, 1, 0, 1, 0, 0, 0, 1, 0, 0]) OPCODE_B = Bus(0, [0, 0, 0, 1, 0, 1]) OPCODE_CBZ = Bus(0, [1, 0, 1, 1, 0, 1, 0, 0]) class Control: def __init__(self): self.branch = 0 self.uncondbranch = 0 self.memread = 0 self.memwrite = 0 self.mem2reg = 0 self.reg2loc = 0 self.aluop = Bus(4) self.signop = Bus(3) self.regwrite = 0 self.alusrc = 0 def performOp(self, opcode): if (opcode == OPCODE_ADDREG): self.branch = 0 self.uncondbranch = 0
def generateFour(self): return Bus(0, [0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0 ])
def add(self, s1, s2): cin = 0 outputBus = Bus(s1.size) zero = 1 for i in range(s1.size): bit1 = s1.at(i) bit2 = s2.at(i) if (bit1 and bit2): if (cin): outputBus.set(i, 1) cin = 1 zero = 0 else: outputBus.set(i, 0) cin = 1 elif ((bit1 and not bit2) or (not bit1 and bit2)): if (cin): outputBus.set(i, 0) cin = 1 else: outputBus.set(i, 1) cin = 0 zero = 0 else: if (cin): outputBus.set(i, 1) cin = 0 zero = 0 else: outputBus.set(i, 0) cin = 0 return outputBus, zero