if force or changed_q: self.send_update_clock() def __freq_to_register_value(self,freq,twos_complement=False): """ Returns an integer that can be used to program the 6 byte frequency registers. """ if twos_complement: c1 = float(2**47) else: c1 = float(2**48) return int(freq*(c1/self.__SYSCLK)) def __get_frequency_resolution(self): c1 = float(2**48) return self.__SYSCLK/c1 if __name__ == "__main__": from Recipe import Recipe R = Recipe(r"D:\tmp\bcode.utb") R.start() D = DDS(address=30,refclock=15*10**6,refclock_multiplier=20) reg = Register("1f",D) reg.set(4,0,5) reg.set_bit(5,1) reg.set_bit(6,1) R.end() print reg
if force or changed_q: self.send_update_clock() def __freq_to_register_value(self, freq, twos_complement=False): """ Returns an integer that can be used to program the 6 byte frequency registers. """ if twos_complement: c1 = float(2**47) else: c1 = float(2**48) return int(freq * (c1 / self.__SYSCLK)) def __get_frequency_resolution(self): c1 = float(2**48) return self.__SYSCLK / c1 if __name__ == "__main__": from Recipe import Recipe R = Recipe(r"D:\tmp\bcode.utb") R.start() D = DDS(address=30, refclock=15 * 10**6, refclock_multiplier=20) reg = Register("1f", D) reg.set(4, 0, 5) reg.set_bit(5, 1) reg.set_bit(6, 1) R.end() print reg